ivpu_drv.h (cdfad4db7756563db7d458216d9e3c2651dddc7d) ivpu_drv.h (2c3801b17459da806f44d3f63f89e999f23e9e60)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_DRV_H__
7#define __IVPU_DRV_H__
8

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162 bool bound;
163};
164
165extern int ivpu_dbg_mask;
166extern u8 ivpu_pll_min_ratio;
167extern u8 ivpu_pll_max_ratio;
168extern int ivpu_sched_mode;
169extern bool ivpu_disable_mmu_cont_pages;
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6#ifndef __IVPU_DRV_H__
7#define __IVPU_DRV_H__
8

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162 bool bound;
163};
164
165extern int ivpu_dbg_mask;
166extern u8 ivpu_pll_min_ratio;
167extern u8 ivpu_pll_max_ratio;
168extern int ivpu_sched_mode;
169extern bool ivpu_disable_mmu_cont_pages;
170extern bool ivpu_force_snoop;
170
171#define IVPU_TEST_MODE_FW_TEST BIT(0)
172#define IVPU_TEST_MODE_NULL_HW BIT(1)
173#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
174#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
175#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
176#define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6)
177#define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7)

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236 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
237}
238
239static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
240{
241 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
242}
243
171
172#define IVPU_TEST_MODE_FW_TEST BIT(0)
173#define IVPU_TEST_MODE_NULL_HW BIT(1)
174#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
175#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
176#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
177#define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6)
178#define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7)

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237 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
238}
239
240static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
241{
242 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
243}
244
245static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
246{
247 return ivpu_force_snoop;
248}
249
244#endif /* __IVPU_DRV_H__ */
250#endif /* __IVPU_DRV_H__ */