1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020-2024 Intel Corporation 4 */ 5 6 #ifndef __IVPU_DRV_H__ 7 #define __IVPU_DRV_H__ 8 9 #include <drm/drm_device.h> 10 #include <drm/drm_drv.h> 11 #include <drm/drm_managed.h> 12 #include <drm/drm_mm.h> 13 #include <drm/drm_print.h> 14 15 #include <linux/pci.h> 16 #include <linux/xarray.h> 17 #include <uapi/drm/ivpu_accel.h> 18 19 #include "ivpu_mmu_context.h" 20 #include "ivpu_ipc.h" 21 22 #define DRIVER_NAME "intel_vpu" 23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)" 24 #define DRIVER_DATE "20230117" 25 26 #define PCI_DEVICE_ID_MTL 0x7d1d 27 #define PCI_DEVICE_ID_ARL 0xad1d 28 #define PCI_DEVICE_ID_LNL 0x643e 29 30 #define IVPU_HW_37XX 37 31 #define IVPU_HW_40XX 40 32 33 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 34 /* SSID 1 is used by the VPU to represent reserved context */ 35 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 36 #define IVPU_USER_CONTEXT_MIN_SSID 2 37 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63) 38 39 #define IVPU_MIN_DB 1 40 #define IVPU_MAX_DB 255 41 42 #define IVPU_NUM_ENGINES 2 43 #define IVPU_NUM_PRIORITIES 4 44 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_ENGINES * IVPU_NUM_PRIORITIES) 45 46 #define IVPU_CMDQ_INDEX(engine, priority) ((engine) * IVPU_NUM_PRIORITIES + (priority)) 47 48 #define IVPU_PLATFORM_SILICON 0 49 #define IVPU_PLATFORM_SIMICS 2 50 #define IVPU_PLATFORM_FPGA 3 51 #define IVPU_PLATFORM_INVALID 8 52 53 #define IVPU_DBG_REG BIT(0) 54 #define IVPU_DBG_IRQ BIT(1) 55 #define IVPU_DBG_MMU BIT(2) 56 #define IVPU_DBG_FILE BIT(3) 57 #define IVPU_DBG_MISC BIT(4) 58 #define IVPU_DBG_FW_BOOT BIT(5) 59 #define IVPU_DBG_PM BIT(6) 60 #define IVPU_DBG_IPC BIT(7) 61 #define IVPU_DBG_BO BIT(8) 62 #define IVPU_DBG_JOB BIT(9) 63 #define IVPU_DBG_JSM BIT(10) 64 #define IVPU_DBG_KREF BIT(11) 65 #define IVPU_DBG_RPM BIT(12) 66 #define IVPU_DBG_MMU_MAP BIT(13) 67 68 #define ivpu_err(vdev, fmt, ...) \ 69 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 70 71 #define ivpu_err_ratelimited(vdev, fmt, ...) \ 72 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 73 74 #define ivpu_warn(vdev, fmt, ...) \ 75 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 76 77 #define ivpu_warn_ratelimited(vdev, fmt, ...) \ 78 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) 79 80 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) 81 82 #define ivpu_dbg(vdev, type, fmt, args...) do { \ 83 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \ 84 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \ 85 } while (0) 86 87 #define IVPU_WA(wa_name) (vdev->wa.wa_name) 88 89 #define IVPU_PRINT_WA(wa_name) do { \ 90 if (IVPU_WA(wa_name)) \ 91 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ 92 } while (0) 93 94 struct ivpu_wa_table { 95 bool punit_disabled; 96 bool clear_runtime_mem; 97 bool interrupt_clear_with_0; 98 bool disable_clock_relinquish; 99 bool disable_d0i3_msg; 100 }; 101 102 struct ivpu_hw_info; 103 struct ivpu_mmu_info; 104 struct ivpu_fw_info; 105 struct ivpu_ipc_info; 106 struct ivpu_pm_info; 107 108 struct ivpu_device { 109 struct drm_device drm; 110 void __iomem *regb; 111 void __iomem *regv; 112 u32 platform; 113 u32 irq; 114 115 struct ivpu_wa_table wa; 116 struct ivpu_hw_info *hw; 117 struct ivpu_mmu_info *mmu; 118 struct ivpu_fw_info *fw; 119 struct ivpu_ipc_info *ipc; 120 struct ivpu_pm_info *pm; 121 122 struct ivpu_mmu_context gctx; 123 struct ivpu_mmu_context rctx; 124 struct mutex context_list_lock; /* Protects user context addition/removal */ 125 struct xarray context_xa; 126 struct xa_limit context_xa_limit; 127 128 struct xarray db_xa; 129 130 struct mutex bo_list_lock; /* Protects bo_list */ 131 struct list_head bo_list; 132 133 struct xarray submitted_jobs_xa; 134 struct ivpu_ipc_consumer job_done_consumer; 135 136 atomic64_t unique_id_counter; 137 138 struct { 139 int boot; 140 int jsm; 141 int tdr; 142 int reschedule_suspend; 143 int autosuspend; 144 int d0i3_entry_msg; 145 } timeout; 146 }; 147 148 /* 149 * file_priv has its own refcount (ref) that allows user space to close the fd 150 * without blocking even if VPU is still processing some jobs. 151 */ 152 struct ivpu_file_priv { 153 struct kref ref; 154 struct ivpu_device *vdev; 155 struct mutex lock; /* Protects cmdq */ 156 struct ivpu_cmdq *cmdq[IVPU_NUM_CMDQS_PER_CTX]; 157 struct ivpu_mmu_context ctx; 158 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */ 159 struct list_head ms_instance_list; 160 struct ivpu_bo *ms_info_bo; 161 bool has_mmu_faults; 162 bool bound; 163 }; 164 165 extern int ivpu_dbg_mask; 166 extern u8 ivpu_pll_min_ratio; 167 extern u8 ivpu_pll_max_ratio; 168 extern int ivpu_sched_mode; 169 extern bool ivpu_disable_mmu_cont_pages; 170 171 #define IVPU_TEST_MODE_FW_TEST BIT(0) 172 #define IVPU_TEST_MODE_NULL_HW BIT(1) 173 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) 174 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) 175 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) 176 #define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6) 177 #define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7) 178 extern int ivpu_test_mode; 179 180 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv); 181 void ivpu_file_priv_put(struct ivpu_file_priv **link); 182 183 int ivpu_boot(struct ivpu_device *vdev); 184 int ivpu_shutdown(struct ivpu_device *vdev); 185 void ivpu_prepare_for_reset(struct ivpu_device *vdev); 186 187 static inline u8 ivpu_revision(struct ivpu_device *vdev) 188 { 189 return to_pci_dev(vdev->drm.dev)->revision; 190 } 191 192 static inline u16 ivpu_device_id(struct ivpu_device *vdev) 193 { 194 return to_pci_dev(vdev->drm.dev)->device; 195 } 196 197 static inline int ivpu_hw_gen(struct ivpu_device *vdev) 198 { 199 switch (ivpu_device_id(vdev)) { 200 case PCI_DEVICE_ID_MTL: 201 case PCI_DEVICE_ID_ARL: 202 return IVPU_HW_37XX; 203 case PCI_DEVICE_ID_LNL: 204 return IVPU_HW_40XX; 205 default: 206 ivpu_err(vdev, "Unknown NPU device\n"); 207 return 0; 208 } 209 } 210 211 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) 212 { 213 return container_of(dev, struct ivpu_device, drm); 214 } 215 216 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev) 217 { 218 struct xa_limit ctx_limit = vdev->context_xa_limit; 219 220 return (ctx_limit.max - ctx_limit.min + 1); 221 } 222 223 static inline u32 ivpu_get_platform(struct ivpu_device *vdev) 224 { 225 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID); 226 return vdev->platform; 227 } 228 229 static inline bool ivpu_is_silicon(struct ivpu_device *vdev) 230 { 231 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON; 232 } 233 234 static inline bool ivpu_is_simics(struct ivpu_device *vdev) 235 { 236 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS; 237 } 238 239 static inline bool ivpu_is_fpga(struct ivpu_device *vdev) 240 { 241 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA; 242 } 243 244 #endif /* __IVPU_DRV_H__ */ 245