io.h (5a2dd72abdae75ea2960145e0549635ce4e0be96) io.h (2f47f44790a9c8fc43e515df3c6be19a35ee5de5)
1#ifndef __ASM_SH_IO_H
2#define __ASM_SH_IO_H
3/*
4 * Convention:
5 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
6 * while in{b,w,l}/out{b,w,l} are for ISA
7 *
8 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p

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233#define __iounmap(addr) do { } while (0)
234#define onchip_remap(addr, size, name) (addr)
235#define onchip_unmap(addr) do { } while (0)
236#endif /* CONFIG_MMU */
237
238static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{
1#ifndef __ASM_SH_IO_H
2#define __ASM_SH_IO_H
3/*
4 * Convention:
5 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
6 * while in{b,w,l}/out{b,w,l} are for ISA
7 *
8 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p

--- 224 unchanged lines hidden (view full) ---

233#define __iounmap(addr) do { } while (0)
234#define onchip_remap(addr, size, name) (addr)
235#define onchip_unmap(addr) do { } while (0)
236#endif /* CONFIG_MMU */
237
238static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{
241#ifdef CONFIG_SUPERH32
241#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
242 unsigned long last_addr = offset + size - 1;
243#endif
244 void __iomem *ret;
245
246 ret = __ioremap_trapped(offset, size);
247 if (ret)
248 return ret;
249
242 unsigned long last_addr = offset + size - 1;
243#endif
244 void __iomem *ret;
245
246 ret = __ioremap_trapped(offset, size);
247 if (ret)
248 return ret;
249
250#ifdef CONFIG_SUPERH32
250#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED)
251 /*
252 * For P1 and P2 space this is trivial, as everything is already
253 * mapped. Uncached access for P1 addresses are done through P2.
254 * In the P3 case or for addresses outside of the 29-bit space,
255 * mapping must be done by the PMB or by using page tables.
256 */
257 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
258 if (unlikely(flags & _PAGE_CACHABLE))

--- 48 unchanged lines hidden --- 		251 /*
252 * For P1 and P2 space this is trivial, as everything is already
253 * mapped. Uncached access for P1 addresses are done through P2.
254 * In the P3 case or for addresses outside of the 29-bit space,
255 * mapping must be done by the PMB or by using page tables.
256 */
257 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
258 if (unlikely(flags & _PAGE_CACHABLE))

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