pci-sh7751.c (5ba7205fc49ff72e88784c94fb661f93e7ae7d36) pci-sh7751.c (757e3c16f8bafa2a470aebf9b04671c5d4d18f49)
1/*
1/*
2 * Low-Level PCI Support for the SH7751
2 * Low-Level PCI Support for the SH7751
3 *
3 *
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
4 * Copyright (C) 2003 - 2009 Paul Mundt
5 * Copyright (C) 2001 Dustin McIntire
7 *
6 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
7 * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
10 *
8 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
14 */
12 */
15#undef DEBUG
16
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/types.h>
20#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/types.h>
16#include <linux/errno.h>
21#include <linux/delay.h>
17#include <linux/io.h>
22#include "pci-sh4.h"
23#include <asm/addrspace.h>
18#include "pci-sh4.h"
19#include <asm/addrspace.h>
24#include <asm/io.h>
25
20
26/*
27 * Initialization. Try all known PCI access methods. Note that we support
28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
29 * to access config space.
30 *
31 * Note that the platform specific initialization (BSC registers, and memory
32 * space mapping) will be called via the platform defined function
33 * pcibios_init_platform().
34 */
35int __init sh7751_pci_init(struct pci_channel *chan)
36{
37 unsigned int id;
38 int ret;
39
40 pr_debug("PCI: Starting intialization.\n");
41
42 chan->reg_base = 0xfe200000;
43
44 /* check for SH7751/SH7751R hardware */
45 id = pci_read_reg(chan, SH7751_PCICONF0);
46 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
47 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
48 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
49 return -ENODEV;
50 }
51
52 if ((ret = sh4_pci_check_direct(chan)) != 0)
53 return ret;
54
55 return pcibios_init_platform();
56}
57
58static int __init __area_sdram_check(struct pci_channel *chan,
59 unsigned int area)
60{
21static int __init __area_sdram_check(struct pci_channel *chan,
22 unsigned int area)
23{
61 u32 word;
24 unsigned long word;
62
25
63 word = ctrl_inl(SH7751_BCR1);
26 word = __raw_readl(SH7751_BCR1);
64 /* check BCR for SDRAM in area */
65 if (((word >> area) & 1) == 0) {
27 /* check BCR for SDRAM in area */
28 if (((word >> area) & 1) == 0) {
66 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
29 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
67 area, word);
68 return 0;
69 }
70 pci_write_reg(chan, word, SH4_PCIBCR1);
71
30 area, word);
31 return 0;
32 }
33 pci_write_reg(chan, word, SH4_PCIBCR1);
34
72 word = (u16)ctrl_inw(SH7751_BCR2);
35 word = __raw_readw(SH7751_BCR2);
73 /* check BCR2 for 32bit SDRAM interface*/
74 if (((word >> (area << 1)) & 0x3) != 0x3) {
36 /* check BCR2 for 32bit SDRAM interface*/
37 if (((word >> (area << 1)) & 0x3) != 0x3) {
75 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
38 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
76 area, word);
77 return 0;
78 }
79 pci_write_reg(chan, word, SH4_PCIBCR2);
80
81 return 1;
82}
83
39 area, word);
40 return 0;
41 }
42 pci_write_reg(chan, word, SH4_PCIBCR2);
43
44 return 1;
45}
46
84int __init sh7751_pcic_init(struct pci_channel *chan,
85 struct sh4_pci_address_map *map)
47static struct resource sh7751_io_resource = {
48 .name = "SH7751_IO",
49 .start = SH7751_PCI_IO_BASE,
50 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
51 .flags = IORESOURCE_IO
52};
53
54static struct resource sh7751_mem_resource = {
55 .name = "SH7785_mem",
56 .start = SH7751_PCI_MEMORY_BASE,
57 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
58 .flags = IORESOURCE_MEM
59};
60
61static struct pci_channel sh7751_pci_controller = {
62 .pci_ops = &sh4_pci_ops,
63 .mem_resource = &sh7751_mem_resource,
64 .mem_offset = 0x00000000,
65 .io_resource = &sh7751_io_resource,
66 .io_offset = 0x00000000,
67};
68
69static struct sh4_pci_address_map sh7751_pci_map = {
70 .window0 = {
71 .base = SH7751_CS3_BASE_ADDR,
72 .size = 0x04000000,
73 },
74};
75
76static int __init sh7751_pci_init(void)
86{
77{
87 u32 reg;
88 u32 word;
78 struct pci_channel *chan = &sh7751_pci_controller;
79 unsigned int id;
80 u32 word, reg;
81 int ret;
89
82
83 printk(KERN_NOTICE "PCI: Starting intialization.\n");
84
85 chan->reg_base = 0xfe200000;
86
87 /* check for SH7751/SH7751R hardware */
88 id = pci_read_reg(chan, SH7751_PCICONF0);
89 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
90 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
91 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
92 return -ENODEV;
93 }
94
95 if ((ret = sh4_pci_check_direct(chan)) != 0)
96 return ret;
97
90 /* Set the BCR's to enable PCI access */
91 reg = ctrl_inl(SH7751_BCR1);
92 reg |= 0x80000;
93 ctrl_outl(reg, SH7751_BCR1);
94
95 /* Turn the clocks back on (not done in reset)*/
96 pci_write_reg(chan, 0, SH4_PCICLKR);
97 /* Clear Powerdown IRQ's (not done in reset) */

--- 9 unchanged lines hidden (view full) ---

107 pci_write_reg(chan, word, SH7751_PCICONF1);
108
109 /* define this host as the host bridge */
110 word = PCI_BASE_CLASS_BRIDGE << 24;
111 pci_write_reg(chan, word, SH7751_PCICONF2);
112
113 /* Set IO and Mem windows to local address
114 * Make PCI and local address the same for easy 1 to 1 mapping
98 /* Set the BCR's to enable PCI access */
99 reg = ctrl_inl(SH7751_BCR1);
100 reg |= 0x80000;
101 ctrl_outl(reg, SH7751_BCR1);
102
103 /* Turn the clocks back on (not done in reset)*/
104 pci_write_reg(chan, 0, SH4_PCICLKR);
105 /* Clear Powerdown IRQ's (not done in reset) */

--- 9 unchanged lines hidden (view full) ---

115 pci_write_reg(chan, word, SH7751_PCICONF1);
116
117 /* define this host as the host bridge */
118 word = PCI_BASE_CLASS_BRIDGE << 24;
119 pci_write_reg(chan, word, SH7751_PCICONF2);
120
121 /* Set IO and Mem windows to local address
122 * Make PCI and local address the same for easy 1 to 1 mapping
115 * Window0 = map->window0.size @ non-cached area base = SDRAM
116 * Window1 = map->window1.size @ cached area base = SDRAM
117 */
123 */
118 word = map->window0.size - 1;
124 word = sh7751_pci_map.window0.size - 1;
119 pci_write_reg(chan, word, SH4_PCILSR0);
125 pci_write_reg(chan, word, SH4_PCILSR0);
120 word = map->window1.size - 1;
121 pci_write_reg(chan, word, SH4_PCILSR1);
122 /* Set the values on window 0 PCI config registers */
126 /* Set the values on window 0 PCI config registers */
123 word = P2SEGADDR(map->window0.base);
127 word = P2SEGADDR(sh7751_pci_map.window0.base);
124 pci_write_reg(chan, word, SH4_PCILAR0);
125 pci_write_reg(chan, word, SH7751_PCICONF5);
128 pci_write_reg(chan, word, SH4_PCILAR0);
129 pci_write_reg(chan, word, SH7751_PCICONF5);
126 /* Set the values on window 1 PCI config registers */
127 word = PHYSADDR(map->window1.base);
128 pci_write_reg(chan, word, SH4_PCILAR1);
129 pci_write_reg(chan, word, SH7751_PCICONF6);
130
131 /* Set the local 16MB PCI memory space window to
132 * the lowest PCI mapped address
133 */
134 word = chan->mem_resource->start & SH4_PCIMBR_MASK;
135 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
136 pci_write_reg(chan, word , SH4_PCIMBR);
137
138 /* Make sure the MSB's of IO window are set to access PCI space
139 * correctly */
140 word = chan->io_resource->start & SH4_PCIIOBR_MASK;
141 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
142 pci_write_reg(chan, word, SH4_PCIIOBR);
143
144 /* Set PCI WCRx, BCRx's, copy from BSC locations */
145
146 /* check BCR for SDRAM in specified area */
130
131 /* Set the local 16MB PCI memory space window to
132 * the lowest PCI mapped address
133 */
134 word = chan->mem_resource->start & SH4_PCIMBR_MASK;
135 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
136 pci_write_reg(chan, word , SH4_PCIMBR);
137
138 /* Make sure the MSB's of IO window are set to access PCI space
139 * correctly */
140 word = chan->io_resource->start & SH4_PCIIOBR_MASK;
141 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
142 pci_write_reg(chan, word, SH4_PCIIOBR);
143
144 /* Set PCI WCRx, BCRx's, copy from BSC locations */
145
146 /* check BCR for SDRAM in specified area */
147 switch (map->window0.base) {
147 switch (sh7751_pci_map.window0.base) {
148 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
149 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
150 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
151 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
152 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
153 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
154 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
155 }

--- 18 unchanged lines hidden (view full) ---

174
175 pci_fixup_pcic(chan);
176
177 /* SH7751 init done, set central function init complete */
178 /* use round robin mode to stop a device starving/overruning */
179 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
180 pci_write_reg(chan, word, SH4_PCICR);
181
148 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
149 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
150 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
151 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
152 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
153 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
154 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
155 }

--- 18 unchanged lines hidden (view full) ---

174
175 pci_fixup_pcic(chan);
176
177 /* SH7751 init done, set central function init complete */
178 /* use round robin mode to stop a device starving/overruning */
179 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
180 pci_write_reg(chan, word, SH4_PCICR);
181
182 __set_io_port_base(SH7751_PCI_IO_BASE);
183
184 register_pci_controller(chan);
185
182 return 0;
183}
186 return 0;
187}
188arch_initcall(sh7751_pci_init);