1 /* 2 * Low-Level PCI Support for the SH7751 3 * 4 * Copyright (C) 2003 - 2009 Paul Mundt 5 * Copyright (C) 2001 Dustin McIntire 6 * 7 * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003. 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/types.h> 16 #include <linux/errno.h> 17 #include <linux/io.h> 18 #include "pci-sh4.h" 19 #include <asm/addrspace.h> 20 21 static int __init __area_sdram_check(struct pci_channel *chan, 22 unsigned int area) 23 { 24 unsigned long word; 25 26 word = __raw_readl(SH7751_BCR1); 27 /* check BCR for SDRAM in area */ 28 if (((word >> area) & 1) == 0) { 29 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", 30 area, word); 31 return 0; 32 } 33 pci_write_reg(chan, word, SH4_PCIBCR1); 34 35 word = __raw_readw(SH7751_BCR2); 36 /* check BCR2 for 32bit SDRAM interface*/ 37 if (((word >> (area << 1)) & 0x3) != 0x3) { 38 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", 39 area, word); 40 return 0; 41 } 42 pci_write_reg(chan, word, SH4_PCIBCR2); 43 44 return 1; 45 } 46 47 static struct resource sh7751_io_resource = { 48 .name = "SH7751_IO", 49 .start = SH7751_PCI_IO_BASE, 50 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, 51 .flags = IORESOURCE_IO 52 }; 53 54 static struct resource sh7751_mem_resource = { 55 .name = "SH7785_mem", 56 .start = SH7751_PCI_MEMORY_BASE, 57 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, 58 .flags = IORESOURCE_MEM 59 }; 60 61 static struct pci_channel sh7751_pci_controller = { 62 .pci_ops = &sh4_pci_ops, 63 .mem_resource = &sh7751_mem_resource, 64 .mem_offset = 0x00000000, 65 .io_resource = &sh7751_io_resource, 66 .io_offset = 0x00000000, 67 }; 68 69 static struct sh4_pci_address_map sh7751_pci_map = { 70 .window0 = { 71 .base = SH7751_CS3_BASE_ADDR, 72 .size = 0x04000000, 73 }, 74 }; 75 76 static int __init sh7751_pci_init(void) 77 { 78 struct pci_channel *chan = &sh7751_pci_controller; 79 unsigned int id; 80 u32 word, reg; 81 int ret; 82 83 printk(KERN_NOTICE "PCI: Starting intialization.\n"); 84 85 chan->reg_base = 0xfe200000; 86 87 /* check for SH7751/SH7751R hardware */ 88 id = pci_read_reg(chan, SH7751_PCICONF0); 89 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && 90 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { 91 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); 92 return -ENODEV; 93 } 94 95 if ((ret = sh4_pci_check_direct(chan)) != 0) 96 return ret; 97 98 /* Set the BCR's to enable PCI access */ 99 reg = ctrl_inl(SH7751_BCR1); 100 reg |= 0x80000; 101 ctrl_outl(reg, SH7751_BCR1); 102 103 /* Turn the clocks back on (not done in reset)*/ 104 pci_write_reg(chan, 0, SH4_PCICLKR); 105 /* Clear Powerdown IRQ's (not done in reset) */ 106 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; 107 pci_write_reg(chan, word, SH4_PCIPINT); 108 109 /* set the command/status bits to: 110 * Wait Cycle Control + Parity Enable + Bus Master + 111 * Mem space enable 112 */ 113 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 114 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 115 pci_write_reg(chan, word, SH7751_PCICONF1); 116 117 /* define this host as the host bridge */ 118 word = PCI_BASE_CLASS_BRIDGE << 24; 119 pci_write_reg(chan, word, SH7751_PCICONF2); 120 121 /* Set IO and Mem windows to local address 122 * Make PCI and local address the same for easy 1 to 1 mapping 123 */ 124 word = sh7751_pci_map.window0.size - 1; 125 pci_write_reg(chan, word, SH4_PCILSR0); 126 /* Set the values on window 0 PCI config registers */ 127 word = P2SEGADDR(sh7751_pci_map.window0.base); 128 pci_write_reg(chan, word, SH4_PCILAR0); 129 pci_write_reg(chan, word, SH7751_PCICONF5); 130 131 /* Set the local 16MB PCI memory space window to 132 * the lowest PCI mapped address 133 */ 134 word = chan->mem_resource->start & SH4_PCIMBR_MASK; 135 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 136 pci_write_reg(chan, word , SH4_PCIMBR); 137 138 /* Make sure the MSB's of IO window are set to access PCI space 139 * correctly */ 140 word = chan->io_resource->start & SH4_PCIIOBR_MASK; 141 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 142 pci_write_reg(chan, word, SH4_PCIIOBR); 143 144 /* Set PCI WCRx, BCRx's, copy from BSC locations */ 145 146 /* check BCR for SDRAM in specified area */ 147 switch (sh7751_pci_map.window0.base) { 148 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break; 149 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break; 150 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break; 151 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break; 152 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break; 153 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break; 154 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break; 155 } 156 157 if (!word) 158 return -1; 159 160 /* configure the wait control registers */ 161 word = ctrl_inl(SH7751_WCR1); 162 pci_write_reg(chan, word, SH4_PCIWCR1); 163 word = ctrl_inl(SH7751_WCR2); 164 pci_write_reg(chan, word, SH4_PCIWCR2); 165 word = ctrl_inl(SH7751_WCR3); 166 pci_write_reg(chan, word, SH4_PCIWCR3); 167 word = ctrl_inl(SH7751_MCR); 168 pci_write_reg(chan, word, SH4_PCIMCR); 169 170 /* NOTE: I'm ignoring the PCI error IRQs for now.. 171 * TODO: add support for the internal error interrupts and 172 * DMA interrupts... 173 */ 174 175 pci_fixup_pcic(chan); 176 177 /* SH7751 init done, set central function init complete */ 178 /* use round robin mode to stop a device starving/overruning */ 179 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 180 pci_write_reg(chan, word, SH4_PCICR); 181 182 __set_io_port_base(SH7751_PCI_IO_BASE); 183 184 register_pci_controller(chan); 185 186 return 0; 187 } 188 arch_initcall(sh7751_pci_init); 189