taishan.dts (96916090f488986a4ebb8e9ffa6a3b50881d5ccd) | taishan.dts (71f349799b34c8b6ce3df42126b4de6cfa16456d) |
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1/* 2 * Device Tree Source for IBM/AMCC Taishan 3 * 4 * Copyright 2007 IBM Corp. 5 * Hugh Blemings <hugh@au.ibm.com> based off code by 6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without 10 * any warranty of any kind, whether express or implied. 11 */ 12 | 1/* 2 * Device Tree Source for IBM/AMCC Taishan 3 * 4 * Copyright 2007 IBM Corp. 5 * Hugh Blemings <hugh@au.ibm.com> based off code by 6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without 10 * any warranty of any kind, whether express or implied. 11 */ 12 |
13/dts-v1/; 14 |
|
13/ { 14 #address-cells = <2>; 15 #size-cells = <1>; 16 model = "amcc,taishan"; 17 compatible = "amcc,taishan"; | 15/ { 16 #address-cells = <2>; 17 #size-cells = <1>; 18 model = "amcc,taishan"; 19 compatible = "amcc,taishan"; |
18 dcr-parent = <&/cpus/cpu@0>; | 20 dcr-parent = <&{/cpus/cpu@0}>; |
19 20 aliases { 21 ethernet0 = &EMAC2; 22 ethernet1 = &EMAC3; 23 serial0 = &UART0; 24 serial1 = &UART1; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 model = "PowerPC,440GX"; | 21 22 aliases { 23 ethernet0 = &EMAC2; 24 ethernet1 = &EMAC3; 25 serial0 = &UART0; 26 serial1 = &UART1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 model = "PowerPC,440GX"; |
34 reg = <0>; 35 clock-frequency = <2FAF0800>; // 800MHz | 36 reg = <0x00000000>; 37 clock-frequency = <800000000>; // 800MHz |
36 timebase-frequency = <0>; // Filled in by zImage | 38 timebase-frequency = <0>; // Filled in by zImage |
37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; 39 i-cache-size = <8000>; /* 32 kB */ 40 d-cache-size = <8000>; /* 32 kB */ | 39 i-cache-line-size = <50>; 40 d-cache-line-size = <50>; 41 i-cache-size = <32768>; /* 32 kB */ 42 d-cache-size = <32768>; /* 32 kB */ |
41 dcr-controller; 42 dcr-access-method = "native"; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; | 43 dcr-controller; 44 dcr-access-method = "native"; 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; |
48 reg = <0 0 0>; // Filled in by zImage | 50 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage |
49 }; 50 51 52 UICB0: interrupt-controller-base { 53 compatible = "ibm,uic-440gx", "ibm,uic"; 54 interrupt-controller; 55 cell-index = <3>; | 51 }; 52 53 54 UICB0: interrupt-controller-base { 55 compatible = "ibm,uic-440gx", "ibm,uic"; 56 interrupt-controller; 57 cell-index = <3>; |
56 dcr-reg = <200 009>; | 58 dcr-reg = <0x200 0x009>; |
57 #address-cells = <0>; 58 #size-cells = <0>; 59 #interrupt-cells = <2>; 60 }; 61 62 63 UIC0: interrupt-controller0 { 64 compatible = "ibm,uic-440gx", "ibm,uic"; 65 interrupt-controller; 66 cell-index = <0>; | 59 #address-cells = <0>; 60 #size-cells = <0>; 61 #interrupt-cells = <2>; 62 }; 63 64 65 UIC0: interrupt-controller0 { 66 compatible = "ibm,uic-440gx", "ibm,uic"; 67 interrupt-controller; 68 cell-index = <0>; |
67 dcr-reg = <0c0 009>; | 69 dcr-reg = <0x0c0 0x009>; |
68 #address-cells = <0>; 69 #size-cells = <0>; 70 #interrupt-cells = <2>; | 70 #address-cells = <0>; 71 #size-cells = <0>; 72 #interrupt-cells = <2>; |
71 interrupts = <01 4 00 4>; /* cascade - first non-critical */ | 73 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */ |
72 interrupt-parent = <&UICB0>; 73 74 }; 75 76 UIC1: interrupt-controller1 { 77 compatible = "ibm,uic-440gx", "ibm,uic"; 78 interrupt-controller; 79 cell-index = <1>; | 74 interrupt-parent = <&UICB0>; 75 76 }; 77 78 UIC1: interrupt-controller1 { 79 compatible = "ibm,uic-440gx", "ibm,uic"; 80 interrupt-controller; 81 cell-index = <1>; |
80 dcr-reg = <0d0 009>; | 82 dcr-reg = <0x0d0 0x009>; |
81 #address-cells = <0>; 82 #size-cells = <0>; 83 #interrupt-cells = <2>; | 83 #address-cells = <0>; 84 #size-cells = <0>; 85 #interrupt-cells = <2>; |
84 interrupts = <03 4 02 4>; /* cascade */ | 86 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */ |
85 interrupt-parent = <&UICB0>; 86 }; 87 88 UIC2: interrupt-controller2 { 89 compatible = "ibm,uic-440gx", "ibm,uic"; 90 interrupt-controller; 91 cell-index = <2>; /* was 1 */ | 87 interrupt-parent = <&UICB0>; 88 }; 89 90 UIC2: interrupt-controller2 { 91 compatible = "ibm,uic-440gx", "ibm,uic"; 92 interrupt-controller; 93 cell-index = <2>; /* was 1 */ |
92 dcr-reg = <210 009>; | 94 dcr-reg = <0x210 0x009>; |
93 #address-cells = <0>; 94 #size-cells = <0>; 95 #interrupt-cells = <2>; | 95 #address-cells = <0>; 96 #size-cells = <0>; 97 #interrupt-cells = <2>; |
96 interrupts = <05 4 04 4>; /* cascade */ | 98 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */ |
97 interrupt-parent = <&UICB0>; 98 }; 99 100 101 CPC0: cpc { 102 compatible = "ibm,cpc-440gp"; | 99 interrupt-parent = <&UICB0>; 100 }; 101 102 103 CPC0: cpc { 104 compatible = "ibm,cpc-440gp"; |
103 dcr-reg = <0b0 003 0e0 010>; | 105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>; |
104 // FIXME: anything else? 105 }; 106 107 L2C0: l2c { 108 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; | 106 // FIXME: anything else? 107 }; 108 109 L2C0: l2c { 110 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; |
109 dcr-reg = <20 8 /* Internal SRAM DCR's */ 110 30 8>; /* L2 cache DCR's */ 111 cache-line-size = <20>; /* 32 bytes */ 112 cache-size = <40000>; /* L2, 256K */ | 111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 112 0x030 0x008>; /* L2 cache DCR's */ 113 cache-line-size = <32>; /* 32 bytes */ 114 cache-size = <262144>; /* L2, 256K */ |
113 interrupt-parent = <&UIC2>; | 115 interrupt-parent = <&UIC2>; |
114 interrupts = <17 1>; | 116 interrupts = <0x17 0x1>; |
115 }; 116 117 plb { 118 compatible = "ibm,plb-440gx", "ibm,plb4"; 119 #address-cells = <2>; 120 #size-cells = <1>; 121 ranges; | 117 }; 118 119 plb { 120 compatible = "ibm,plb-440gx", "ibm,plb4"; 121 #address-cells = <2>; 122 #size-cells = <1>; 123 ranges; |
122 clock-frequency = <9896800>; // 160MHz | 124 clock-frequency = <160000000>; // 160MHz |
123 124 SDRAM0: memory-controller { 125 compatible = "ibm,sdram-440gp"; | 125 126 SDRAM0: memory-controller { 127 compatible = "ibm,sdram-440gp"; |
126 dcr-reg = <010 2>; | 128 dcr-reg = <0x010 0x002>; |
127 // FIXME: anything else? 128 }; 129 130 SRAM0: sram { 131 compatible = "ibm,sram-440gp"; | 129 // FIXME: anything else? 130 }; 131 132 SRAM0: sram { 133 compatible = "ibm,sram-440gp"; |
132 dcr-reg = <020 8 00a 1>; | 134 dcr-reg = <0x020 0x008 0x00a 0x001>; |
133 }; 134 135 DMA0: dma { 136 // FIXME: ??? 137 compatible = "ibm,dma-440gp"; | 135 }; 136 137 DMA0: dma { 138 // FIXME: ??? 139 compatible = "ibm,dma-440gp"; |
138 dcr-reg = <100 027>; | 140 dcr-reg = <0x100 0x027>; |
139 }; 140 141 MAL0: mcmal { 142 compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; | 141 }; 142 143 MAL0: mcmal { 144 compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; |
143 dcr-reg = <180 62>; | 145 dcr-reg = <0x180 0x062>; |
144 num-tx-chans = <4>; 145 num-rx-chans = <4>; 146 interrupt-parent = <&MAL0>; | 146 num-tx-chans = <4>; 147 num-rx-chans = <4>; 148 interrupt-parent = <&MAL0>; |
147 interrupts = <0 1 2 3 4>; | 149 interrupts = <0x0 0x1 0x2 0x3 0x4>; |
148 #interrupt-cells = <1>; 149 #address-cells = <0>; 150 #size-cells = <0>; | 150 #interrupt-cells = <1>; 151 #address-cells = <0>; 152 #size-cells = <0>; |
151 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 152 /*RXEOB*/ 1 &UIC0 b 4 153 /*SERR*/ 2 &UIC1 0 4 154 /*TXDE*/ 3 &UIC1 1 4 155 /*RXDE*/ 4 &UIC1 2 4>; 156 interrupt-map-mask = <ffffffff>; | 153 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 154 /*RXEOB*/ 0x1 &UIC0 0xb 0x4 155 /*SERR*/ 0x2 &UIC1 0x0 0x4 156 /*TXDE*/ 0x3 &UIC1 0x1 0x4 157 /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 158 interrupt-map-mask = <0xffffffff>; |
157 }; 158 159 POB0: opb { 160 compatible = "ibm,opb-440gx", "ibm,opb"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 /* Wish there was a nicer way of specifying a full 32-bit 164 range */ | 159 }; 160 161 POB0: opb { 162 compatible = "ibm,opb-440gx", "ibm,opb"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 /* Wish there was a nicer way of specifying a full 32-bit 166 range */ |
165 ranges = <00000000 1 00000000 80000000 166 80000000 1 80000000 80000000>; 167 dcr-reg = <090 00b>; | 167 ranges = <0x00000000 0x00000001 0x00000000 0x80000000 168 0x80000000 0x00000001 0x80000000 0x80000000>; 169 dcr-reg = <0x090 0x00b>; |
168 interrupt-parent = <&UIC1>; | 170 interrupt-parent = <&UIC1>; |
169 interrupts = <7 4>; 170 clock-frequency = <4C4B400>; // 80MHz | 171 interrupts = <0x7 0x4>; 172 clock-frequency = <80000000>; // 80MHz |
171 172 173 EBC0: ebc { 174 compatible = "ibm,ebc-440gx", "ibm,ebc"; | 173 174 175 EBC0: ebc { 176 compatible = "ibm,ebc-440gx", "ibm,ebc"; |
175 dcr-reg = <012 2>; | 177 dcr-reg = <0x012 0x002>; |
176 #address-cells = <2>; 177 #size-cells = <1>; | 178 #address-cells = <2>; 179 #size-cells = <1>; |
178 clock-frequency = <4C4B400>; // 80MHz | 180 clock-frequency = <80000000>; // 80MHz |
179 180 /* ranges property is supplied by zImage 181 * based on firmware's configuration of the 182 * EBC bridge */ 183 | 181 182 /* ranges property is supplied by zImage 183 * based on firmware's configuration of the 184 * EBC bridge */ 185 |
184 interrupts = <5 4>; | 186 interrupts = <0x5 0x4>; |
185 interrupt-parent = <&UIC1>; 186 187 /* TODO: Add other EBC devices */ 188 }; 189 190 191 192 UART0: serial@40000200 { 193 device_type = "serial"; 194 compatible = "ns16550"; | 187 interrupt-parent = <&UIC1>; 188 189 /* TODO: Add other EBC devices */ 190 }; 191 192 193 194 UART0: serial@40000200 { 195 device_type = "serial"; 196 compatible = "ns16550"; |
195 reg = <40000200 8>; 196 virtual-reg = <e0000200>; 197 clock-frequency = <A8C000>; 198 current-speed = <1C200>; /* 115200 */ | 197 reg = <0x40000200 0x00000008>; 198 virtual-reg = <0xe0000200>; 199 clock-frequency = <11059200>; 200 current-speed = <115200>; /* 115200 */ |
199 interrupt-parent = <&UIC0>; | 201 interrupt-parent = <&UIC0>; |
200 interrupts = <0 4>; | 202 interrupts = <0x0 0x4>; |
201 }; 202 203 UART1: serial@40000300 { 204 device_type = "serial"; 205 compatible = "ns16550"; | 203 }; 204 205 UART1: serial@40000300 { 206 device_type = "serial"; 207 compatible = "ns16550"; |
206 reg = <40000300 8>; 207 virtual-reg = <e0000300>; 208 clock-frequency = <A8C000>; 209 current-speed = <1C200>; /* 115200 */ | 208 reg = <0x40000300 0x00000008>; 209 virtual-reg = <0xe0000300>; 210 clock-frequency = <11059200>; 211 current-speed = <115200>; /* 115200 */ |
210 interrupt-parent = <&UIC0>; | 212 interrupt-parent = <&UIC0>; |
211 interrupts = <1 4>; | 213 interrupts = <0x1 0x4>; |
212 }; 213 214 IIC0: i2c@40000400 { 215 /* FIXME */ 216 compatible = "ibm,iic-440gp", "ibm,iic"; | 214 }; 215 216 IIC0: i2c@40000400 { 217 /* FIXME */ 218 compatible = "ibm,iic-440gp", "ibm,iic"; |
217 reg = <40000400 14>; | 219 reg = <0x40000400 0x00000014>; |
218 interrupt-parent = <&UIC0>; | 220 interrupt-parent = <&UIC0>; |
219 interrupts = <2 4>; | 221 interrupts = <0x2 0x4>; |
220 }; 221 IIC1: i2c@40000500 { 222 /* FIXME */ 223 compatible = "ibm,iic-440gp", "ibm,iic"; | 222 }; 223 IIC1: i2c@40000500 { 224 /* FIXME */ 225 compatible = "ibm,iic-440gp", "ibm,iic"; |
224 reg = <40000500 14>; | 226 reg = <0x40000500 0x00000014>; |
225 interrupt-parent = <&UIC0>; | 227 interrupt-parent = <&UIC0>; |
226 interrupts = <3 4>; | 228 interrupts = <0x3 0x4>; |
227 }; 228 229 GPIO0: gpio@40000700 { 230 /* FIXME */ 231 compatible = "ibm,gpio-440gp"; | 229 }; 230 231 GPIO0: gpio@40000700 { 232 /* FIXME */ 233 compatible = "ibm,gpio-440gp"; |
232 reg = <40000700 20>; | 234 reg = <0x40000700 0x00000020>; |
233 }; 234 235 ZMII0: emac-zmii@40000780 { 236 compatible = "ibm,zmii-440gx", "ibm,zmii"; | 235 }; 236 237 ZMII0: emac-zmii@40000780 { 238 compatible = "ibm,zmii-440gx", "ibm,zmii"; |
237 reg = <40000780 c>; | 239 reg = <0x40000780 0x0000000c>; |
238 }; 239 240 RGMII0: emac-rgmii@40000790 { 241 compatible = "ibm,rgmii"; | 240 }; 241 242 RGMII0: emac-rgmii@40000790 { 243 compatible = "ibm,rgmii"; |
242 reg = <40000790 8>; | 244 reg = <0x40000790 0x00000008>; |
243 }; 244 245 TAH0: emac-tah@40000b50 { 246 compatible = "ibm,tah-440gx", "ibm,tah"; | 245 }; 246 247 TAH0: emac-tah@40000b50 { 248 compatible = "ibm,tah-440gx", "ibm,tah"; |
247 reg = <40000b50 30>; | 249 reg = <0x40000b50 0x00000030>; |
248 }; 249 250 TAH1: emac-tah@40000d50 { 251 compatible = "ibm,tah-440gx", "ibm,tah"; | 250 }; 251 252 TAH1: emac-tah@40000d50 { 253 compatible = "ibm,tah-440gx", "ibm,tah"; |
252 reg = <40000d50 30>; | 254 reg = <0x40000d50 0x00000030>; |
253 }; 254 255 EMAC0: ethernet@40000800 { | 255 }; 256 257 EMAC0: ethernet@40000800 { |
256 unused = <1>; | 258 unused = <0x1>; |
257 device_type = "network"; 258 compatible = "ibm,emac-440gx", "ibm,emac4"; 259 interrupt-parent = <&UIC1>; | 259 device_type = "network"; 260 compatible = "ibm,emac-440gx", "ibm,emac4"; 261 interrupt-parent = <&UIC1>; |
260 interrupts = <1c 4 1d 4>; 261 reg = <40000800 70>; | 262 interrupts = <0x1c 0x4 0x1d 0x4>; 263 reg = <0x40000800 0x00000070>; |
262 local-mac-address = [000000000000]; // Filled in by zImage 263 mal-device = <&MAL0>; 264 mal-tx-channel = <0>; 265 mal-rx-channel = <0>; 266 cell-index = <0>; | 264 local-mac-address = [000000000000]; // Filled in by zImage 265 mal-device = <&MAL0>; 266 mal-tx-channel = <0>; 267 mal-rx-channel = <0>; 268 cell-index = <0>; |
267 max-frame-size = <5dc>; 268 rx-fifo-size = <1000>; 269 tx-fifo-size = <800>; | 269 max-frame-size = <1500>; 270 rx-fifo-size = <4096>; 271 tx-fifo-size = <2048>; |
270 phy-mode = "rmii"; | 272 phy-mode = "rmii"; |
271 phy-map = <00000001>; | 273 phy-map = <0x00000001>; |
272 zmii-device = <&ZMII0>; 273 zmii-channel = <0>; 274 }; 275 EMAC1: ethernet@40000900 { | 274 zmii-device = <&ZMII0>; 275 zmii-channel = <0>; 276 }; 277 EMAC1: ethernet@40000900 { |
276 unused = <1>; | 278 unused = <0x1>; |
277 device_type = "network"; 278 compatible = "ibm,emac-440gx", "ibm,emac4"; 279 interrupt-parent = <&UIC1>; | 279 device_type = "network"; 280 compatible = "ibm,emac-440gx", "ibm,emac4"; 281 interrupt-parent = <&UIC1>; |
280 interrupts = <1e 4 1f 4>; 281 reg = <40000900 70>; | 282 interrupts = <0x1e 0x4 0x1f 0x4>; 283 reg = <0x40000900 0x00000070>; |
282 local-mac-address = [000000000000]; // Filled in by zImage 283 mal-device = <&MAL0>; 284 mal-tx-channel = <1>; 285 mal-rx-channel = <1>; 286 cell-index = <1>; | 284 local-mac-address = [000000000000]; // Filled in by zImage 285 mal-device = <&MAL0>; 286 mal-tx-channel = <1>; 287 mal-rx-channel = <1>; 288 cell-index = <1>; |
287 max-frame-size = <5dc>; 288 rx-fifo-size = <1000>; 289 tx-fifo-size = <800>; | 289 max-frame-size = <1500>; 290 rx-fifo-size = <4096>; 291 tx-fifo-size = <2048>; |
290 phy-mode = "rmii"; | 292 phy-mode = "rmii"; |
291 phy-map = <00000001>; | 293 phy-map = <0x00000001>; |
292 zmii-device = <&ZMII0>; 293 zmii-channel = <1>; 294 }; 295 296 EMAC2: ethernet@40000c00 { 297 device_type = "network"; 298 compatible = "ibm,emac-440gx", "ibm,emac4"; 299 interrupt-parent = <&UIC2>; | 294 zmii-device = <&ZMII0>; 295 zmii-channel = <1>; 296 }; 297 298 EMAC2: ethernet@40000c00 { 299 device_type = "network"; 300 compatible = "ibm,emac-440gx", "ibm,emac4"; 301 interrupt-parent = <&UIC2>; |
300 interrupts = <0 4 1 4>; 301 reg = <40000c00 70>; | 302 interrupts = <0x0 0x4 0x1 0x4>; 303 reg = <0x40000c00 0x00000070>; |
302 local-mac-address = [000000000000]; // Filled in by zImage 303 mal-device = <&MAL0>; 304 mal-tx-channel = <2>; 305 mal-rx-channel = <2>; 306 cell-index = <2>; | 304 local-mac-address = [000000000000]; // Filled in by zImage 305 mal-device = <&MAL0>; 306 mal-tx-channel = <2>; 307 mal-rx-channel = <2>; 308 cell-index = <2>; |
307 max-frame-size = <2328>; 308 rx-fifo-size = <1000>; 309 tx-fifo-size = <800>; | 309 max-frame-size = <9000>; 310 rx-fifo-size = <4096>; 311 tx-fifo-size = <2048>; |
310 phy-mode = "rgmii"; | 312 phy-mode = "rgmii"; |
311 phy-map = <00000001>; | 313 phy-map = <0x00000001>; |
312 rgmii-device = <&RGMII0>; 313 rgmii-channel = <0>; 314 zmii-device = <&ZMII0>; 315 zmii-channel = <2>; 316 tah-device = <&TAH0>; 317 tah-channel = <0>; 318 }; 319 320 EMAC3: ethernet@40000e00 { 321 device_type = "network"; 322 compatible = "ibm,emac-440gx", "ibm,emac4"; 323 interrupt-parent = <&UIC2>; | 314 rgmii-device = <&RGMII0>; 315 rgmii-channel = <0>; 316 zmii-device = <&ZMII0>; 317 zmii-channel = <2>; 318 tah-device = <&TAH0>; 319 tah-channel = <0>; 320 }; 321 322 EMAC3: ethernet@40000e00 { 323 device_type = "network"; 324 compatible = "ibm,emac-440gx", "ibm,emac4"; 325 interrupt-parent = <&UIC2>; |
324 interrupts = <2 4 3 4>; 325 reg = <40000e00 70>; | 326 interrupts = <0x2 0x4 0x3 0x4>; 327 reg = <0x40000e00 0x00000070>; |
326 local-mac-address = [000000000000]; // Filled in by zImage 327 mal-device = <&MAL0>; 328 mal-tx-channel = <3>; 329 mal-rx-channel = <3>; 330 cell-index = <3>; | 328 local-mac-address = [000000000000]; // Filled in by zImage 329 mal-device = <&MAL0>; 330 mal-tx-channel = <3>; 331 mal-rx-channel = <3>; 332 cell-index = <3>; |
331 max-frame-size = <2328>; 332 rx-fifo-size = <1000>; 333 tx-fifo-size = <800>; | 333 max-frame-size = <9000>; 334 rx-fifo-size = <4096>; 335 tx-fifo-size = <2048>; |
334 phy-mode = "rgmii"; | 336 phy-mode = "rgmii"; |
335 phy-map = <00000003>; | 337 phy-map = <0x00000003>; |
336 rgmii-device = <&RGMII0>; 337 rgmii-channel = <1>; 338 zmii-device = <&ZMII0>; 339 zmii-channel = <3>; 340 tah-device = <&TAH1>; 341 tah-channel = <0>; 342 }; 343 344 345 GPT0: gpt@40000a00 { 346 /* FIXME */ | 338 rgmii-device = <&RGMII0>; 339 rgmii-channel = <1>; 340 zmii-device = <&ZMII0>; 341 zmii-channel = <3>; 342 tah-device = <&TAH1>; 343 tah-channel = <0>; 344 }; 345 346 347 GPT0: gpt@40000a00 { 348 /* FIXME */ |
347 reg = <40000a00 d4>; | 349 reg = <0x40000a00 0x000000d4>; |
348 interrupt-parent = <&UIC0>; | 350 interrupt-parent = <&UIC0>; |
349 interrupts = <12 4 13 4 14 4 15 4 16 4>; | 351 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; |
350 }; 351 352 }; 353 354 PCIX0: pci@20ec00000 { 355 device_type = "pci"; 356 #interrupt-cells = <1>; 357 #size-cells = <2>; 358 #address-cells = <3>; 359 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 360 primary; 361 large-inbound-windows; 362 enable-msi-hole; | 352 }; 353 354 }; 355 356 PCIX0: pci@20ec00000 { 357 device_type = "pci"; 358 #interrupt-cells = <1>; 359 #size-cells = <2>; 360 #address-cells = <3>; 361 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 362 primary; 363 large-inbound-windows; 364 enable-msi-hole; |
363 reg = <2 0ec00000 8 /* Config space access */ 364 0 0 0 /* no IACK cycles */ 365 2 0ed00000 4 /* Special cycles */ 366 2 0ec80000 100 /* Internal registers */ 367 2 0ec80100 fc>; /* Internal messaging registers */ | 365 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ 366 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 367 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ 368 0x00000002 0x0ec80000 0x00000100 /* Internal registers */ 369 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ |
368 369 /* Outbound ranges, one memory and one IO, 370 * later cannot be changed 371 */ | 370 371 /* Outbound ranges, one memory and one IO, 372 * later cannot be changed 373 */ |
372 ranges = <02000000 0 80000000 00000003 80000000 0 80000000 373 01000000 0 00000000 00000002 08000000 0 00010000>; | 374 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 375 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; |
374 375 /* Inbound 2GB range starting at 0 */ | 376 377 /* Inbound 2GB range starting at 0 */ |
376 dma-ranges = <42000000 0 0 0 0 0 80000000>; | 378 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
377 | 379 |
378 interrupt-map-mask = <f800 0 0 7>; | 380 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; |
379 interrupt-map = < 380 /* IDSEL 1 */ | 381 interrupt-map = < 382 /* IDSEL 1 */ |
381 0800 0 0 1 &UIC0 17 8 382 0800 0 0 2 &UIC0 18 8 383 0800 0 0 3 &UIC0 19 8 384 0800 0 0 4 &UIC0 1a 8 | 383 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8 384 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8 385 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8 386 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8 |
385 386 /* IDSEL 2 */ | 387 388 /* IDSEL 2 */ |
387 1000 0 0 1 &UIC0 18 8 388 1000 0 0 2 &UIC0 19 8 389 1000 0 0 3 &UIC0 1a 8 390 1000 0 0 4 &UIC0 17 8 | 389 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8 390 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8 391 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8 392 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8 |
391 >; 392 }; 393 }; 394 395 chosen { 396 linux,stdout-path = "/plb/opb/serial@40000300"; 397 }; 398}; | 393 >; 394 }; 395 }; 396 397 chosen { 398 linux,stdout-path = "/plb/opb/serial@40000300"; 399 }; 400}; |