1/* 2 * Device Tree Source for IBM/AMCC Taishan 3 * 4 * Copyright 2007 IBM Corp. 5 * Hugh Blemings <hugh@au.ibm.com> based off code by 6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without 10 * any warranty of any kind, whether express or implied. 11 */ 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <1>; 16 model = "amcc,taishan"; 17 compatible = "amcc,taishan"; 18 dcr-parent = <&/cpus/cpu@0>; 19 20 aliases { 21 ethernet0 = &EMAC2; 22 ethernet1 = &EMAC3; 23 serial0 = &UART0; 24 serial1 = &UART1; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu@0 { 32 device_type = "cpu"; 33 model = "PowerPC,440GX"; 34 reg = <0>; 35 clock-frequency = <2FAF0800>; // 800MHz 36 timebase-frequency = <0>; // Filled in by zImage 37 i-cache-line-size = <32>; 38 d-cache-line-size = <32>; 39 i-cache-size = <8000>; /* 32 kB */ 40 d-cache-size = <8000>; /* 32 kB */ 41 dcr-controller; 42 dcr-access-method = "native"; 43 }; 44 }; 45 46 memory { 47 device_type = "memory"; 48 reg = <0 0 0>; // Filled in by zImage 49 }; 50 51 52 UICB0: interrupt-controller-base { 53 compatible = "ibm,uic-440gx", "ibm,uic"; 54 interrupt-controller; 55 cell-index = <3>; 56 dcr-reg = <200 009>; 57 #address-cells = <0>; 58 #size-cells = <0>; 59 #interrupt-cells = <2>; 60 }; 61 62 63 UIC0: interrupt-controller0 { 64 compatible = "ibm,uic-440gx", "ibm,uic"; 65 interrupt-controller; 66 cell-index = <0>; 67 dcr-reg = <0c0 009>; 68 #address-cells = <0>; 69 #size-cells = <0>; 70 #interrupt-cells = <2>; 71 interrupts = <01 4 00 4>; /* cascade - first non-critical */ 72 interrupt-parent = <&UICB0>; 73 74 }; 75 76 UIC1: interrupt-controller1 { 77 compatible = "ibm,uic-440gx", "ibm,uic"; 78 interrupt-controller; 79 cell-index = <1>; 80 dcr-reg = <0d0 009>; 81 #address-cells = <0>; 82 #size-cells = <0>; 83 #interrupt-cells = <2>; 84 interrupts = <03 4 02 4>; /* cascade */ 85 interrupt-parent = <&UICB0>; 86 }; 87 88 UIC2: interrupt-controller2 { 89 compatible = "ibm,uic-440gx", "ibm,uic"; 90 interrupt-controller; 91 cell-index = <2>; /* was 1 */ 92 dcr-reg = <210 009>; 93 #address-cells = <0>; 94 #size-cells = <0>; 95 #interrupt-cells = <2>; 96 interrupts = <05 4 04 4>; /* cascade */ 97 interrupt-parent = <&UICB0>; 98 }; 99 100 101 CPC0: cpc { 102 compatible = "ibm,cpc-440gp"; 103 dcr-reg = <0b0 003 0e0 010>; 104 // FIXME: anything else? 105 }; 106 107 L2C0: l2c { 108 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; 109 dcr-reg = <20 8 /* Internal SRAM DCR's */ 110 30 8>; /* L2 cache DCR's */ 111 cache-line-size = <20>; /* 32 bytes */ 112 cache-size = <40000>; /* L2, 256K */ 113 interrupt-parent = <&UIC2>; 114 interrupts = <17 1>; 115 }; 116 117 plb { 118 compatible = "ibm,plb-440gx", "ibm,plb4"; 119 #address-cells = <2>; 120 #size-cells = <1>; 121 ranges; 122 clock-frequency = <9896800>; // 160MHz 123 124 SDRAM0: memory-controller { 125 compatible = "ibm,sdram-440gp"; 126 dcr-reg = <010 2>; 127 // FIXME: anything else? 128 }; 129 130 SRAM0: sram { 131 compatible = "ibm,sram-440gp"; 132 dcr-reg = <020 8 00a 1>; 133 }; 134 135 DMA0: dma { 136 // FIXME: ??? 137 compatible = "ibm,dma-440gp"; 138 dcr-reg = <100 027>; 139 }; 140 141 MAL0: mcmal { 142 compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; 143 dcr-reg = <180 62>; 144 num-tx-chans = <4>; 145 num-rx-chans = <4>; 146 interrupt-parent = <&MAL0>; 147 interrupts = <0 1 2 3 4>; 148 #interrupt-cells = <1>; 149 #address-cells = <0>; 150 #size-cells = <0>; 151 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 152 /*RXEOB*/ 1 &UIC0 b 4 153 /*SERR*/ 2 &UIC1 0 4 154 /*TXDE*/ 3 &UIC1 1 4 155 /*RXDE*/ 4 &UIC1 2 4>; 156 interrupt-map-mask = <ffffffff>; 157 }; 158 159 POB0: opb { 160 compatible = "ibm,opb-440gx", "ibm,opb"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 /* Wish there was a nicer way of specifying a full 32-bit 164 range */ 165 ranges = <00000000 1 00000000 80000000 166 80000000 1 80000000 80000000>; 167 dcr-reg = <090 00b>; 168 interrupt-parent = <&UIC1>; 169 interrupts = <7 4>; 170 clock-frequency = <4C4B400>; // 80MHz 171 172 173 EBC0: ebc { 174 compatible = "ibm,ebc-440gx", "ibm,ebc"; 175 dcr-reg = <012 2>; 176 #address-cells = <2>; 177 #size-cells = <1>; 178 clock-frequency = <4C4B400>; // 80MHz 179 180 /* ranges property is supplied by zImage 181 * based on firmware's configuration of the 182 * EBC bridge */ 183 184 interrupts = <5 4>; 185 interrupt-parent = <&UIC1>; 186 187 /* TODO: Add other EBC devices */ 188 }; 189 190 191 192 UART0: serial@40000200 { 193 device_type = "serial"; 194 compatible = "ns16550"; 195 reg = <40000200 8>; 196 virtual-reg = <e0000200>; 197 clock-frequency = <A8C000>; 198 current-speed = <1C200>; /* 115200 */ 199 interrupt-parent = <&UIC0>; 200 interrupts = <0 4>; 201 }; 202 203 UART1: serial@40000300 { 204 device_type = "serial"; 205 compatible = "ns16550"; 206 reg = <40000300 8>; 207 virtual-reg = <e0000300>; 208 clock-frequency = <A8C000>; 209 current-speed = <1C200>; /* 115200 */ 210 interrupt-parent = <&UIC0>; 211 interrupts = <1 4>; 212 }; 213 214 IIC0: i2c@40000400 { 215 /* FIXME */ 216 compatible = "ibm,iic-440gp", "ibm,iic"; 217 reg = <40000400 14>; 218 interrupt-parent = <&UIC0>; 219 interrupts = <2 4>; 220 }; 221 IIC1: i2c@40000500 { 222 /* FIXME */ 223 compatible = "ibm,iic-440gp", "ibm,iic"; 224 reg = <40000500 14>; 225 interrupt-parent = <&UIC0>; 226 interrupts = <3 4>; 227 }; 228 229 GPIO0: gpio@40000700 { 230 /* FIXME */ 231 compatible = "ibm,gpio-440gp"; 232 reg = <40000700 20>; 233 }; 234 235 ZMII0: emac-zmii@40000780 { 236 compatible = "ibm,zmii-440gx", "ibm,zmii"; 237 reg = <40000780 c>; 238 }; 239 240 RGMII0: emac-rgmii@40000790 { 241 compatible = "ibm,rgmii"; 242 reg = <40000790 8>; 243 }; 244 245 TAH0: emac-tah@40000b50 { 246 compatible = "ibm,tah-440gx", "ibm,tah"; 247 reg = <40000b50 30>; 248 }; 249 250 TAH1: emac-tah@40000d50 { 251 compatible = "ibm,tah-440gx", "ibm,tah"; 252 reg = <40000d50 30>; 253 }; 254 255 EMAC0: ethernet@40000800 { 256 unused = <1>; 257 device_type = "network"; 258 compatible = "ibm,emac-440gx", "ibm,emac4"; 259 interrupt-parent = <&UIC1>; 260 interrupts = <1c 4 1d 4>; 261 reg = <40000800 70>; 262 local-mac-address = [000000000000]; // Filled in by zImage 263 mal-device = <&MAL0>; 264 mal-tx-channel = <0>; 265 mal-rx-channel = <0>; 266 cell-index = <0>; 267 max-frame-size = <5dc>; 268 rx-fifo-size = <1000>; 269 tx-fifo-size = <800>; 270 phy-mode = "rmii"; 271 phy-map = <00000001>; 272 zmii-device = <&ZMII0>; 273 zmii-channel = <0>; 274 }; 275 EMAC1: ethernet@40000900 { 276 unused = <1>; 277 device_type = "network"; 278 compatible = "ibm,emac-440gx", "ibm,emac4"; 279 interrupt-parent = <&UIC1>; 280 interrupts = <1e 4 1f 4>; 281 reg = <40000900 70>; 282 local-mac-address = [000000000000]; // Filled in by zImage 283 mal-device = <&MAL0>; 284 mal-tx-channel = <1>; 285 mal-rx-channel = <1>; 286 cell-index = <1>; 287 max-frame-size = <5dc>; 288 rx-fifo-size = <1000>; 289 tx-fifo-size = <800>; 290 phy-mode = "rmii"; 291 phy-map = <00000001>; 292 zmii-device = <&ZMII0>; 293 zmii-channel = <1>; 294 }; 295 296 EMAC2: ethernet@40000c00 { 297 device_type = "network"; 298 compatible = "ibm,emac-440gx", "ibm,emac4"; 299 interrupt-parent = <&UIC2>; 300 interrupts = <0 4 1 4>; 301 reg = <40000c00 70>; 302 local-mac-address = [000000000000]; // Filled in by zImage 303 mal-device = <&MAL0>; 304 mal-tx-channel = <2>; 305 mal-rx-channel = <2>; 306 cell-index = <2>; 307 max-frame-size = <2328>; 308 rx-fifo-size = <1000>; 309 tx-fifo-size = <800>; 310 phy-mode = "rgmii"; 311 phy-map = <00000001>; 312 rgmii-device = <&RGMII0>; 313 rgmii-channel = <0>; 314 zmii-device = <&ZMII0>; 315 zmii-channel = <2>; 316 tah-device = <&TAH0>; 317 tah-channel = <0>; 318 }; 319 320 EMAC3: ethernet@40000e00 { 321 device_type = "network"; 322 compatible = "ibm,emac-440gx", "ibm,emac4"; 323 interrupt-parent = <&UIC2>; 324 interrupts = <2 4 3 4>; 325 reg = <40000e00 70>; 326 local-mac-address = [000000000000]; // Filled in by zImage 327 mal-device = <&MAL0>; 328 mal-tx-channel = <3>; 329 mal-rx-channel = <3>; 330 cell-index = <3>; 331 max-frame-size = <2328>; 332 rx-fifo-size = <1000>; 333 tx-fifo-size = <800>; 334 phy-mode = "rgmii"; 335 phy-map = <00000003>; 336 rgmii-device = <&RGMII0>; 337 rgmii-channel = <1>; 338 zmii-device = <&ZMII0>; 339 zmii-channel = <3>; 340 tah-device = <&TAH1>; 341 tah-channel = <0>; 342 }; 343 344 345 GPT0: gpt@40000a00 { 346 /* FIXME */ 347 reg = <40000a00 d4>; 348 interrupt-parent = <&UIC0>; 349 interrupts = <12 4 13 4 14 4 15 4 16 4>; 350 }; 351 352 }; 353 354 PCIX0: pci@20ec00000 { 355 device_type = "pci"; 356 #interrupt-cells = <1>; 357 #size-cells = <2>; 358 #address-cells = <3>; 359 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 360 primary; 361 large-inbound-windows; 362 enable-msi-hole; 363 reg = <2 0ec00000 8 /* Config space access */ 364 0 0 0 /* no IACK cycles */ 365 2 0ed00000 4 /* Special cycles */ 366 2 0ec80000 100 /* Internal registers */ 367 2 0ec80100 fc>; /* Internal messaging registers */ 368 369 /* Outbound ranges, one memory and one IO, 370 * later cannot be changed 371 */ 372 ranges = <02000000 0 80000000 00000003 80000000 0 80000000 373 01000000 0 00000000 00000002 08000000 0 00010000>; 374 375 /* Inbound 2GB range starting at 0 */ 376 dma-ranges = <42000000 0 0 0 0 0 80000000>; 377 378 interrupt-map-mask = <f800 0 0 7>; 379 interrupt-map = < 380 /* IDSEL 1 */ 381 0800 0 0 1 &UIC0 17 8 382 0800 0 0 2 &UIC0 18 8 383 0800 0 0 3 &UIC0 19 8 384 0800 0 0 4 &UIC0 1a 8 385 386 /* IDSEL 2 */ 387 1000 0 0 1 &UIC0 18 8 388 1000 0 0 2 &UIC0 19 8 389 1000 0 0 3 &UIC0 1a 8 390 1000 0 0 4 &UIC0 17 8 391 >; 392 }; 393 }; 394 395 chosen { 396 linux,stdout-path = "/plb/opb/serial@40000300"; 397 }; 398}; 399