time.c (8e6d08e0a15e7d4d4b608b56597350d4cdd77710) time.c (4553474d977d1ee8a81067cfbc588f1df84ce3e9)
1/*
2 * OpenRISC time.c
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:

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22
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/irq.h>
26#include <linux/io.h>
27
28#include <asm/cpuinfo.h>
29
1/*
2 * OpenRISC time.c
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:

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22
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/irq.h>
26#include <linux/io.h>
27
28#include <asm/cpuinfo.h>
29
30static int openrisc_timer_set_next_event(unsigned long delta,
31 struct clock_event_device *dev)
30/* Test the timer ticks to count, used in sync routine */
31inline void openrisc_timer_set(unsigned long count)
32{
32{
33 mtspr(SPR_TTCR, count);
34}
35
36/* Set the timer to trigger in delta cycles */
37inline void openrisc_timer_set_next(unsigned long delta)
38{
33 u32 c;
34
35 /* Read 32-bit counter value, add delta, mask off the low 28 bits.
36 * We're guaranteed delta won't be bigger than 28 bits because the
37 * generic timekeeping code ensures that for us.
38 */
39 c = mfspr(SPR_TTCR);
40 c += delta;
41 c &= SPR_TTMR_TP;
42
43 /* Set counter and enable interrupt.
44 * Keep timer in continuous mode always.
45 */
46 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
39 u32 c;
40
41 /* Read 32-bit counter value, add delta, mask off the low 28 bits.
42 * We're guaranteed delta won't be bigger than 28 bits because the
43 * generic timekeeping code ensures that for us.
44 */
45 c = mfspr(SPR_TTCR);
46 c += delta;
47 c &= SPR_TTMR_TP;
48
49 /* Set counter and enable interrupt.
50 * Keep timer in continuous mode always.
51 */
52 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
53}
47
54
55static int openrisc_timer_set_next_event(unsigned long delta,
56 struct clock_event_device *dev)
57{
58 openrisc_timer_set_next(delta);
48 return 0;
49}
50
51/* This is the clock event device based on the OR1K tick timer.
52 * As the timer is being used as a continuous clock-source (required for HR
53 * timers) we cannot enable the PERIODIC feature. The tick timer can run using
54 * one-shot events, so no problem.
55 */

--- 110 unchanged lines hidden --- 		59 return 0;
60}
61
62/* This is the clock event device based on the OR1K tick timer.
63 * As the timer is being used as a continuous clock-source (required for HR
64 * timers) we cannot enable the PERIODIC feature. The tick timer can run using
65 * one-shot events, so no problem.
66 */

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