1 /* 2 * OpenRISC time.c 3 * 4 * Linux architectural port borrowing liberally from similar works of 5 * others. All original copyrights apply as per the original source 6 * declaration. 7 * 8 * Modifications for the OpenRISC architecture: 9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/time.h> 19 #include <linux/timex.h> 20 #include <linux/interrupt.h> 21 #include <linux/ftrace.h> 22 23 #include <linux/clocksource.h> 24 #include <linux/clockchips.h> 25 #include <linux/irq.h> 26 #include <linux/io.h> 27 28 #include <asm/cpuinfo.h> 29 30 static int openrisc_timer_set_next_event(unsigned long delta, 31 struct clock_event_device *dev) 32 { 33 u32 c; 34 35 /* Read 32-bit counter value, add delta, mask off the low 28 bits. 36 * We're guaranteed delta won't be bigger than 28 bits because the 37 * generic timekeeping code ensures that for us. 38 */ 39 c = mfspr(SPR_TTCR); 40 c += delta; 41 c &= SPR_TTMR_TP; 42 43 /* Set counter and enable interrupt. 44 * Keep timer in continuous mode always. 45 */ 46 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c); 47 48 return 0; 49 } 50 51 /* This is the clock event device based on the OR1K tick timer. 52 * As the timer is being used as a continuous clock-source (required for HR 53 * timers) we cannot enable the PERIODIC feature. The tick timer can run using 54 * one-shot events, so no problem. 55 */ 56 DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer); 57 58 void openrisc_clockevent_init(void) 59 { 60 unsigned int cpu = smp_processor_id(); 61 struct clock_event_device *evt = 62 &per_cpu(clockevent_openrisc_timer, cpu); 63 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu]; 64 65 mtspr(SPR_TTMR, SPR_TTMR_CR); 66 67 #ifdef CONFIG_SMP 68 evt->broadcast = tick_broadcast; 69 #endif 70 evt->name = "openrisc_timer_clockevent", 71 evt->features = CLOCK_EVT_FEAT_ONESHOT, 72 evt->rating = 300, 73 evt->set_next_event = openrisc_timer_set_next_event, 74 75 evt->cpumask = cpumask_of(cpu); 76 77 /* We only have 28 bits */ 78 clockevents_config_and_register(evt, cpuinfo->clock_frequency, 79 100, 0x0fffffff); 80 81 } 82 83 static inline void timer_ack(void) 84 { 85 /* Clear the IP bit and disable further interrupts */ 86 /* This can be done very simply... we just need to keep the timer 87 running, so just maintain the CR bits while clearing the rest 88 of the register 89 */ 90 mtspr(SPR_TTMR, SPR_TTMR_CR); 91 } 92 93 /* 94 * The timer interrupt is mostly handled in generic code nowadays... this 95 * function just acknowledges the interrupt and fires the event handler that 96 * has been set on the clockevent device by the generic time management code. 97 * 98 * This function needs to be called by the timer exception handler and that's 99 * all the exception handler needs to do. 100 */ 101 102 irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs) 103 { 104 struct pt_regs *old_regs = set_irq_regs(regs); 105 unsigned int cpu = smp_processor_id(); 106 struct clock_event_device *evt = 107 &per_cpu(clockevent_openrisc_timer, cpu); 108 109 timer_ack(); 110 111 /* 112 * update_process_times() expects us to have called irq_enter(). 113 */ 114 irq_enter(); 115 evt->event_handler(evt); 116 irq_exit(); 117 118 set_irq_regs(old_regs); 119 120 return IRQ_HANDLED; 121 } 122 123 /** 124 * Clocksource: Based on OpenRISC timer/counter 125 * 126 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer 127 * is 32 bits wide and runs at the CPU clock frequency. 128 */ 129 static u64 openrisc_timer_read(struct clocksource *cs) 130 { 131 return (u64) mfspr(SPR_TTCR); 132 } 133 134 static struct clocksource openrisc_timer = { 135 .name = "openrisc_timer", 136 .rating = 200, 137 .read = openrisc_timer_read, 138 .mask = CLOCKSOURCE_MASK(32), 139 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 140 }; 141 142 static int __init openrisc_timer_init(void) 143 { 144 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; 145 146 if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency)) 147 panic("failed to register clocksource"); 148 149 /* Enable the incrementer: 'continuous' mode with interrupt disabled */ 150 mtspr(SPR_TTMR, SPR_TTMR_CR); 151 152 return 0; 153 } 154 155 void __init time_init(void) 156 { 157 u32 upr; 158 159 upr = mfspr(SPR_UPR); 160 if (!(upr & SPR_UPR_TTP)) 161 panic("Linux not supported on devices without tick timer"); 162 163 openrisc_timer_init(); 164 openrisc_clockevent_init(); 165 } 166