cp1emu.c (7cbe010a5ea728d7c4440b11a1a3997faca0e46d) cp1emu.c (842dfc11ea9a21f9825167c8a4f2834b205b0a79)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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579#endif
580 case cop0_op:
581 case cop1_op:
582 case cop2_op:
583 case cop1x_op:
584 if (insn.i_format.rs == bc_op) {
585 preempt_disable();
586 if (is_fpu_owner())
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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579#endif
580 case cop0_op:
581 case cop1_op:
582 case cop2_op:
583 case cop1x_op:
584 if (insn.i_format.rs == bc_op) {
585 preempt_disable();
586 if (is_fpu_owner())
587 asm volatile(
588 ".set push\n"
589 "\t.set mips1\n"
590 "\tcfc1\t%0,$31\n"
591 "\t.set pop" : "=r" (fcr31));
587 fcr31 = read_32bit_cp1_register(CP1_STATUS);
592 else
593 fcr31 = current->thread.fpu.fcr31;
594 preempt_enable();
595
596 bit = (insn.i_format.rt >> 2);
597 bit += (bit != 0);
598 bit += 23;
599 switch (insn.i_format.rt & 3) {

--- 1359 unchanged lines hidden --- 		588 else
589 fcr31 = current->thread.fpu.fcr31;
590 preempt_enable();
591
592 bit = (insn.i_format.rt >> 2);
593 bit += (bit != 0);
594 bit += 23;
595 switch (insn.i_format.rt & 3) {

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