cp1emu.c (4b820d95dc53c15e6e727da964430a3ed60e05ef) cp1emu.c (ab4a92e66741b35ca12f8497896bafbe579c28a1)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

--- 431 unchanged lines hidden (view full) ---

440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
445 case spec_op:
446 switch (insn.r_format.func) {
447 case jalr_op:
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

--- 431 unchanged lines hidden (view full) ---

440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
445 case spec_op:
446 switch (insn.r_format.func) {
447 case jalr_op:
448 regs->regs[insn.r_format.rd] =
449 regs->cp0_epc + dec_insn.pc_inc +
450 dec_insn.next_pc_inc;
448 if (insn.r_format.rd != 0) {
449 regs->regs[insn.r_format.rd] =
450 regs->cp0_epc + dec_insn.pc_inc +
451 dec_insn.next_pc_inc;
452 }
451 /* Fall through */
452 case jr_op:
453 /* For R6, JR already emulated in jalr_op */
454 if (NO_R6EMU && insn.r_format.func == jr_op)
455 break;
456 *contpc = regs->regs[insn.r_format.rs];
457 return 1;
458 }

--- 2161 unchanged lines hidden --- 		453 /* Fall through */
454 case jr_op:
455 /* For R6, JR already emulated in jalr_op */
456 if (NO_R6EMU && insn.r_format.func == jr_op)
457 break;
458 *contpc = regs->regs[insn.r_format.rs];
459 return 1;
460 }

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