traps.c (0fdc50dfab47d525b71a9f0d8310746cdc0c09c5) traps.c (ec7a93188a75b57b9f704db6862e7137f01aa80b)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson

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66#include <linux/uaccess.h>
67#include <asm/watch.h>
68#include <asm/mmu_context.h>
69#include <asm/types.h>
70#include <asm/stacktrace.h>
71#include <asm/tlbex.h>
72#include <asm/uasm.h>
73
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson

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66#include <linux/uaccess.h>
67#include <asm/watch.h>
68#include <asm/mmu_context.h>
69#include <asm/types.h>
70#include <asm/stacktrace.h>
71#include <asm/tlbex.h>
72#include <asm/uasm.h>
73
74#include <asm/mach-loongson64/cpucfg-emul.h>
75
74extern void check_wait(void);
75extern asmlinkage void rollback_handle_int(void);
76extern asmlinkage void handle_int(void);
77extern asmlinkage void handle_adel(void);
78extern asmlinkage void handle_ades(void);
79extern asmlinkage void handle_ibe(void);
80extern asmlinkage void handle_dbe(void);
81extern asmlinkage void handle_sys(void);

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688 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
689 1, regs, 0);
690 return 0;
691 }
692
693 return -1; /* Must be something else ... */
694}
695
76extern void check_wait(void);
77extern asmlinkage void rollback_handle_int(void);
78extern asmlinkage void handle_int(void);
79extern asmlinkage void handle_adel(void);
80extern asmlinkage void handle_ades(void);
81extern asmlinkage void handle_ibe(void);
82extern asmlinkage void handle_dbe(void);
83extern asmlinkage void handle_sys(void);

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690 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
691 1, regs, 0);
692 return 0;
693 }
694
695 return -1; /* Must be something else ... */
696}
697
698/*
699 * Loongson-3 CSR instructions emulation
700 */
701
702#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
703
704#define LWC2 0xc8000000
705#define RS BASE
706#define CSR_OPCODE2 0x00000118
707#define CSR_OPCODE2_MASK 0x000007ff
708#define CSR_FUNC_MASK RT
709#define CSR_FUNC_CPUCFG 0x8
710
711static int simulate_loongson3_cpucfg(struct pt_regs *regs,
712 unsigned int opcode)
713{
714 int op = opcode & OPCODE;
715 int op2 = opcode & CSR_OPCODE2_MASK;
716 int csr_func = (opcode & CSR_FUNC_MASK) >> 16;
717
718 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {
719 int rd = (opcode & RD) >> 11;
720 int rs = (opcode & RS) >> 21;
721 __u64 sel = regs->regs[rs];
722
723 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
724
725 regs->regs[rd] = loongson3_cpucfg_read_synthesized(
726 &current_cpu_data, sel);
727
728 return 0;
729 }
730
731 /* Not ours. */
732 return -1;
733}
734#endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */
735
696asmlinkage void do_ov(struct pt_regs *regs)
697{
698 enum ctx_state prev_state;
699
700 prev_state = exception_enter();
701 die_if_kernel("Integer overflow", regs);
702
703 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc);

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1161 if (status < 0)
1162 status = simulate_rdhwr_normal(regs, opcode);
1163
1164 if (status < 0)
1165 status = simulate_sync(regs, opcode);
1166
1167 if (status < 0)
1168 status = simulate_fp(regs, opcode, old_epc, old31);
736asmlinkage void do_ov(struct pt_regs *regs)
737{
738 enum ctx_state prev_state;
739
740 prev_state = exception_enter();
741 die_if_kernel("Integer overflow", regs);
742
743 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc);

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1201 if (status < 0)
1202 status = simulate_rdhwr_normal(regs, opcode);
1203
1204 if (status < 0)
1205 status = simulate_sync(regs, opcode);
1206
1207 if (status < 0)
1208 status = simulate_fp(regs, opcode, old_epc, old31);
1209
1210#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
1211 if (status < 0)
1212 status = simulate_loongson3_cpucfg(regs, opcode);
1213#endif
1169 } else if (cpu_has_mmips) {
1170 unsigned short mmop[2] = { 0 };
1171
1172 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1173 status = SIGSEGV;
1174 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1175 status = SIGSEGV;
1176 opcode = mmop[0];

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1396 * of these ISAs however use this code erroneously for COP1X
1397 * instructions. Therefore we redirect this trap to the FP
1398 * emulator too.
1399 */
1400 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1401 force_sig(SIGILL);
1402 break;
1403 }
1214 } else if (cpu_has_mmips) {
1215 unsigned short mmop[2] = { 0 };
1216
1217 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1218 status = SIGSEGV;
1219 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1220 status = SIGSEGV;
1221 opcode = mmop[0];

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1441 * of these ISAs however use this code erroneously for COP1X
1442 * instructions. Therefore we redirect this trap to the FP
1443 * emulator too.
1444 */
1445 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
1446 force_sig(SIGILL);
1447 break;
1448 }
1404 /* Fall through. */
1405
1449 fallthrough;
1406 case 1: {
1407 void __user *fault_addr;
1408 unsigned long fcr31;
1409 int err, sig;
1410
1411 err = enable_restore_fp_context(0);
1412
1413 if (raw_cpu_has_fpu && !err)

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1451 void __user *fault_addr;
1452 unsigned long fcr31;
1453 int err, sig;
1454
1455 err = enable_restore_fp_context(0);
1456
1457 if (raw_cpu_has_fpu && !err)

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