| pgtable.h (907bc6c7fc7071b00083fc11e510e47dd93df45d) | pgtable.h (a6475c132278c1be158a13872c233aeab8a00176) |
|---|---|
| 1/* 2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2008-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. --- 76 unchanged lines hidden (view full) --- 85#define VMALLOC_START (CONFIG_KERNEL_START + \ 86 max(32 * 1024 * 1024UL, memory_size)) 87#define VMALLOC_END ioremap_bot 88#define VMALLOC_VMADDR(x) ((unsigned long)(x)) 89 90#endif /* __ASSEMBLY__ */ 91 92/* | 1/* 2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2008-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. --- 76 unchanged lines hidden (view full) --- 85#define VMALLOC_START (CONFIG_KERNEL_START + \ 86 max(32 * 1024 * 1024UL, memory_size)) 87#define VMALLOC_END ioremap_bot 88#define VMALLOC_VMADDR(x) ((unsigned long)(x)) 89 90#endif /* __ASSEMBLY__ */ 91 92/* |
| 93 * Macro to mark a page protection value as "uncacheable". 94 */ 95 96#define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ 97 _PAGE_WRITETHRU) 98 99#define pgprot_noncached(prot) \ 100 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 101 _PAGE_NO_CACHE | _PAGE_GUARDED)) 102 103#define pgprot_noncached_wc(prot) \ 104 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 105 _PAGE_NO_CACHE)) 106 107/* |
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| 93 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 94 * table containing PTEs, together with a set of 16 segment registers, to 95 * define the virtual to physical address mapping. 96 * 97 * We use the hash table as an extended TLB, i.e. a cache of currently 98 * active mappings. We maintain a two-level page table tree, much 99 * like that used by the i386, for the sake of the Linux memory 100 * management code. Low-level assembler code in hashtable.S --- 492 unchanged lines hidden --- | 108 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 109 * table containing PTEs, together with a set of 16 segment registers, to 110 * define the virtual to physical address mapping. 111 * 112 * We use the hash table as an extended TLB, i.e. a cache of currently 113 * active mappings. We maintain a two-level page table tree, much 114 * like that used by the i386, for the sake of the Linux memory 115 * management code. Low-level assembler code in hashtable.S --- 492 unchanged lines hidden --- |