1 /* 2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2008-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #ifndef _ASM_MICROBLAZE_PGTABLE_H 12 #define _ASM_MICROBLAZE_PGTABLE_H 13 14 #include <asm/setup.h> 15 16 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 17 remap_pfn_range(vma, vaddr, pfn, size, prot) 18 19 #ifndef CONFIG_MMU 20 21 #define pgd_present(pgd) (1) /* pages are always present on non MMU */ 22 #define pgd_none(pgd) (0) 23 #define pgd_bad(pgd) (0) 24 #define pgd_clear(pgdp) 25 #define kern_addr_valid(addr) (1) 26 #define pmd_offset(a, b) ((void *) 0) 27 28 #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */ 29 #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */ 30 #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */ 31 #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */ 32 #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */ 33 34 #define pgprot_noncached(x) (x) 35 36 #define __swp_type(x) (0) 37 #define __swp_offset(x) (0) 38 #define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) 39 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 40 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 41 42 #ifndef __ASSEMBLY__ 43 static inline int pte_file(pte_t pte) { return 0; } 44 #endif /* __ASSEMBLY__ */ 45 46 #define ZERO_PAGE(vaddr) ({ BUG(); NULL; }) 47 48 #define swapper_pg_dir ((pgd_t *) NULL) 49 50 #define pgtable_cache_init() do {} while (0) 51 52 #define arch_enter_lazy_cpu_mode() do {} while (0) 53 54 #else /* CONFIG_MMU */ 55 56 #include <asm-generic/4level-fixup.h> 57 58 #ifdef __KERNEL__ 59 #ifndef __ASSEMBLY__ 60 61 #include <linux/sched.h> 62 #include <linux/threads.h> 63 #include <asm/processor.h> /* For TASK_SIZE */ 64 #include <asm/mmu.h> 65 #include <asm/page.h> 66 67 #define FIRST_USER_ADDRESS 0 68 69 extern unsigned long va_to_phys(unsigned long address); 70 extern pte_t *va_to_pte(unsigned long address); 71 extern unsigned long ioremap_bot, ioremap_base; 72 73 /* 74 * The following only work if pte_present() is true. 75 * Undefined behaviour if not.. 76 */ 77 78 static inline int pte_special(pte_t pte) { return 0; } 79 80 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 81 82 /* Start and end of the vmalloc area. */ 83 /* Make sure to map the vmalloc area above the pinned kernel memory area 84 of 32Mb. */ 85 #define VMALLOC_START (CONFIG_KERNEL_START + \ 86 max(32 * 1024 * 1024UL, memory_size)) 87 #define VMALLOC_END ioremap_bot 88 #define VMALLOC_VMADDR(x) ((unsigned long)(x)) 89 90 #endif /* __ASSEMBLY__ */ 91 92 /* 93 * Macro to mark a page protection value as "uncacheable". 94 */ 95 96 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \ 97 _PAGE_WRITETHRU) 98 99 #define pgprot_noncached(prot) \ 100 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 101 _PAGE_NO_CACHE | _PAGE_GUARDED)) 102 103 #define pgprot_noncached_wc(prot) \ 104 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 105 _PAGE_NO_CACHE)) 106 107 /* 108 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 109 * table containing PTEs, together with a set of 16 segment registers, to 110 * define the virtual to physical address mapping. 111 * 112 * We use the hash table as an extended TLB, i.e. a cache of currently 113 * active mappings. We maintain a two-level page table tree, much 114 * like that used by the i386, for the sake of the Linux memory 115 * management code. Low-level assembler code in hashtable.S 116 * (procedure hash_page) is responsible for extracting ptes from the 117 * tree and putting them into the hash table when necessary, and 118 * updating the accessed and modified bits in the page table tree. 119 */ 120 121 /* 122 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 123 * instruction and data sides share a unified, 64-entry, semi-associative 124 * TLB which is maintained totally under software control. In addition, the 125 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative 126 * TLB which serves as a first level to the shared TLB. These two TLBs are 127 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions). 128 */ 129 130 /* 131 * The normal case is that PTEs are 32-bits and we have a 1-page 132 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 133 * 134 */ 135 136 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */ 137 #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT) 138 #define PMD_SIZE (1UL << PMD_SHIFT) 139 #define PMD_MASK (~(PMD_SIZE-1)) 140 141 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 142 #define PGDIR_SHIFT PMD_SHIFT 143 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 144 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 145 146 /* 147 * entries per page directory level: our page-table tree is two-level, so 148 * we don't really have any PMD directory. 149 */ 150 #define PTRS_PER_PTE (1 << PTE_SHIFT) 151 #define PTRS_PER_PMD 1 152 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 153 154 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 155 #define FIRST_USER_PGD_NR 0 156 157 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) 158 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) 159 160 #define pte_ERROR(e) \ 161 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \ 162 __FILE__, __LINE__, pte_val(e)) 163 #define pmd_ERROR(e) \ 164 printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \ 165 __FILE__, __LINE__, pmd_val(e)) 166 #define pgd_ERROR(e) \ 167 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \ 168 __FILE__, __LINE__, pgd_val(e)) 169 170 /* 171 * Bits in a linux-style PTE. These match the bits in the 172 * (hardware-defined) PTE as closely as possible. 173 */ 174 175 /* There are several potential gotchas here. The hardware TLBLO 176 * field looks like this: 177 * 178 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 179 * RPN..................... 0 0 EX WR ZSEL....... W I M G 180 * 181 * Where possible we make the Linux PTE bits match up with this 182 * 183 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can 184 * support down to 1k pages), this is done in the TLBMiss exception 185 * handler. 186 * - We use only zones 0 (for kernel pages) and 1 (for user pages) 187 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB 188 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct 189 * zone. 190 * - PRESENT *must* be in the bottom two bits because swap cache 191 * entries use the top 30 bits. Because 4xx doesn't support SMP 192 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 193 * is cleared in the TLB miss handler before the TLB entry is loaded. 194 * - All other bits of the PTE are loaded into TLBLO without 195 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for 196 * software PTE bits. We actually use use bits 21, 24, 25, and 197 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and 198 * PRESENT. 199 */ 200 201 /* Definitions for MicroBlaze. */ 202 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ 203 #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ 204 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ 205 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ 206 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ 207 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ 208 #define _PAGE_RW 0x040 /* software: Writes permitted */ 209 #define _PAGE_DIRTY 0x080 /* software: dirty page */ 210 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ 211 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ 212 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ 213 #define _PMD_PRESENT PAGE_MASK 214 215 /* 216 * Some bits are unused... 217 */ 218 #ifndef _PAGE_HASHPTE 219 #define _PAGE_HASHPTE 0 220 #endif 221 #ifndef _PTE_NONE_MASK 222 #define _PTE_NONE_MASK 0 223 #endif 224 #ifndef _PAGE_SHARED 225 #define _PAGE_SHARED 0 226 #endif 227 #ifndef _PAGE_HWWRITE 228 #define _PAGE_HWWRITE 0 229 #endif 230 #ifndef _PAGE_HWEXEC 231 #define _PAGE_HWEXEC 0 232 #endif 233 #ifndef _PAGE_EXEC 234 #define _PAGE_EXEC 0 235 #endif 236 237 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 238 239 /* 240 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware 241 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need 242 * to have it in the Linux PTE, and in fact the bit could be reused for 243 * another purpose. -- paulus. 244 */ 245 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) 246 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) 247 248 #define _PAGE_KERNEL \ 249 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC) 250 251 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) 252 253 #define PAGE_NONE __pgprot(_PAGE_BASE) 254 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) 255 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 256 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 257 #define PAGE_SHARED_X \ 258 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) 259 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) 260 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 261 262 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 263 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED) 264 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO) 265 266 /* 267 * We consider execute permission the same as read. 268 * Also, write permissions imply read permissions. 269 */ 270 #define __P000 PAGE_NONE 271 #define __P001 PAGE_READONLY_X 272 #define __P010 PAGE_COPY 273 #define __P011 PAGE_COPY_X 274 #define __P100 PAGE_READONLY 275 #define __P101 PAGE_READONLY_X 276 #define __P110 PAGE_COPY 277 #define __P111 PAGE_COPY_X 278 279 #define __S000 PAGE_NONE 280 #define __S001 PAGE_READONLY_X 281 #define __S010 PAGE_SHARED 282 #define __S011 PAGE_SHARED_X 283 #define __S100 PAGE_READONLY 284 #define __S101 PAGE_READONLY_X 285 #define __S110 PAGE_SHARED 286 #define __S111 PAGE_SHARED_X 287 288 #ifndef __ASSEMBLY__ 289 /* 290 * ZERO_PAGE is a global shared page that is always zero: used 291 * for zero-mapped memory areas etc.. 292 */ 293 extern unsigned long empty_zero_page[1024]; 294 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 295 296 #endif /* __ASSEMBLY__ */ 297 298 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) 299 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) 300 #define pte_clear(mm, addr, ptep) \ 301 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) 302 303 #define pmd_none(pmd) (!pmd_val(pmd)) 304 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0) 305 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0) 306 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) 307 308 #define pte_page(x) (mem_map + (unsigned long) \ 309 ((pte_val(x) - memory_start) >> PAGE_SHIFT)) 310 #define PFN_SHIFT_OFFSET (PAGE_SHIFT) 311 312 #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) 313 314 #define pfn_pte(pfn, prot) \ 315 __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot)) 316 317 #ifndef __ASSEMBLY__ 318 /* 319 * The "pgd_xxx()" functions here are trivial for a folded two-level 320 * setup: the pgd is never bad, and a pmd always exists (as it's folded 321 * into the pgd entry) 322 */ 323 static inline int pgd_none(pgd_t pgd) { return 0; } 324 static inline int pgd_bad(pgd_t pgd) { return 0; } 325 static inline int pgd_present(pgd_t pgd) { return 1; } 326 #define pgd_clear(xp) do { } while (0) 327 #define pgd_page(pgd) \ 328 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) 329 330 /* 331 * The following only work if pte_present() is true. 332 * Undefined behaviour if not.. 333 */ 334 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } 335 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } 336 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 337 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 338 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 339 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } 340 341 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } 342 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } 343 344 static inline pte_t pte_rdprotect(pte_t pte) \ 345 { pte_val(pte) &= ~_PAGE_USER; return pte; } 346 static inline pte_t pte_wrprotect(pte_t pte) \ 347 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } 348 static inline pte_t pte_exprotect(pte_t pte) \ 349 { pte_val(pte) &= ~_PAGE_EXEC; return pte; } 350 static inline pte_t pte_mkclean(pte_t pte) \ 351 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } 352 static inline pte_t pte_mkold(pte_t pte) \ 353 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 354 355 static inline pte_t pte_mkread(pte_t pte) \ 356 { pte_val(pte) |= _PAGE_USER; return pte; } 357 static inline pte_t pte_mkexec(pte_t pte) \ 358 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; } 359 static inline pte_t pte_mkwrite(pte_t pte) \ 360 { pte_val(pte) |= _PAGE_RW; return pte; } 361 static inline pte_t pte_mkdirty(pte_t pte) \ 362 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 363 static inline pte_t pte_mkyoung(pte_t pte) \ 364 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 365 366 /* 367 * Conversion functions: convert a page and protection to a page entry, 368 * and a page entry and page directory to the page they refer to. 369 */ 370 371 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot) 372 { 373 pte_t pte; 374 pte_val(pte) = physpage | pgprot_val(pgprot); 375 return pte; 376 } 377 378 #define mk_pte(page, pgprot) \ 379 ({ \ 380 pte_t pte; \ 381 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \ 382 pgprot_val(pgprot); \ 383 pte; \ 384 }) 385 386 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 387 { 388 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); 389 return pte; 390 } 391 392 /* 393 * Atomic PTE updates. 394 * 395 * pte_update clears and sets bit atomically, and returns 396 * the old pte value. 397 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant 398 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits. 399 */ 400 static inline unsigned long pte_update(pte_t *p, unsigned long clr, 401 unsigned long set) 402 { 403 unsigned long old, tmp, msr; 404 405 __asm__ __volatile__("\ 406 msrclr %2, 0x2\n\ 407 nop\n\ 408 lw %0, %4, r0\n\ 409 andn %1, %0, %5\n\ 410 or %1, %1, %6\n\ 411 sw %1, %4, r0\n\ 412 mts rmsr, %2\n\ 413 nop" 414 : "=&r" (old), "=&r" (tmp), "=&r" (msr), "=m" (*p) 415 : "r" ((unsigned long)(p+1) - 4), "r" (clr), "r" (set), "m" (*p) 416 : "cc"); 417 418 return old; 419 } 420 421 /* 422 * set_pte stores a linux PTE into the linux page table. 423 */ 424 static inline void set_pte(struct mm_struct *mm, unsigned long addr, 425 pte_t *ptep, pte_t pte) 426 { 427 *ptep = pte; 428 } 429 430 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 431 pte_t *ptep, pte_t pte) 432 { 433 *ptep = pte; 434 } 435 436 static inline int ptep_test_and_clear_young(struct mm_struct *mm, 437 unsigned long addr, pte_t *ptep) 438 { 439 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0; 440 } 441 442 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm, 443 unsigned long addr, pte_t *ptep) 444 { 445 return (pte_update(ptep, \ 446 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0; 447 } 448 449 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 450 unsigned long addr, pte_t *ptep) 451 { 452 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 453 } 454 455 /*static inline void ptep_set_wrprotect(struct mm_struct *mm, 456 unsigned long addr, pte_t *ptep) 457 { 458 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); 459 }*/ 460 461 static inline void ptep_mkdirty(struct mm_struct *mm, 462 unsigned long addr, pte_t *ptep) 463 { 464 pte_update(ptep, 0, _PAGE_DIRTY); 465 } 466 467 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/ 468 469 /* Convert pmd entry to page */ 470 /* our pmd entry is an effective address of pte table*/ 471 /* returns effective address of the pmd entry*/ 472 #define pmd_page_kernel(pmd) ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) 473 474 /* returns struct *page of the pmd entry*/ 475 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 476 477 /* to find an entry in a kernel page-table-directory */ 478 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 479 480 /* to find an entry in a page-table-directory */ 481 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 482 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 483 484 /* Find an entry in the second-level page table.. */ 485 static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) 486 { 487 return (pmd_t *) dir; 488 } 489 490 /* Find an entry in the third-level page table.. */ 491 #define pte_index(address) \ 492 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 493 #define pte_offset_kernel(dir, addr) \ 494 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr)) 495 #define pte_offset_map(dir, addr) \ 496 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) 497 #define pte_offset_map_nested(dir, addr) \ 498 ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) 499 500 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) 501 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) 502 503 /* Encode and decode a nonlinear file mapping entry */ 504 #define PTE_FILE_MAX_BITS 29 505 #define pte_to_pgoff(pte) (pte_val(pte) >> 3) 506 #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) 507 508 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 509 510 /* 511 * When flushing the tlb entry for a page, we also need to flush the hash 512 * table entry. flush_hash_page is assembler (for speed) in hashtable.S. 513 */ 514 extern int flush_hash_page(unsigned context, unsigned long va, pte_t *ptep); 515 516 /* Add an HPTE to the hash table */ 517 extern void add_hash_page(unsigned context, unsigned long va, pte_t *ptep); 518 519 /* 520 * Encode and decode a swap entry. 521 * Note that the bits we use in a PTE for representing a swap entry 522 * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit 523 * (if used). -- paulus 524 */ 525 #define __swp_type(entry) ((entry).val & 0x3f) 526 #define __swp_offset(entry) ((entry).val >> 6) 527 #define __swp_entry(type, offset) \ 528 ((swp_entry_t) { (type) | ((offset) << 6) }) 529 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 }) 530 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 }) 531 532 533 /* CONFIG_APUS */ 534 /* For virtual address to physical address conversion */ 535 extern void cache_clear(__u32 addr, int length); 536 extern void cache_push(__u32 addr, int length); 537 extern int mm_end_of_chunk(unsigned long addr, int len); 538 extern unsigned long iopa(unsigned long addr); 539 /* extern unsigned long mm_ptov(unsigned long addr) \ 540 __attribute__ ((const)); TBD */ 541 542 /* Values for nocacheflag and cmode */ 543 /* These are not used by the APUS kernel_map, but prevents 544 * compilation errors. 545 */ 546 #define IOMAP_FULL_CACHING 0 547 #define IOMAP_NOCACHE_SER 1 548 #define IOMAP_NOCACHE_NONSER 2 549 #define IOMAP_NO_COPYBACK 3 550 551 /* 552 * Map some physical address range into the kernel address space. 553 */ 554 extern unsigned long kernel_map(unsigned long paddr, unsigned long size, 555 int nocacheflag, unsigned long *memavailp); 556 557 /* 558 * Set cache mode of (kernel space) address range. 559 */ 560 extern void kernel_set_cachemode(unsigned long address, unsigned long size, 561 unsigned int cmode); 562 563 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 564 #define kern_addr_valid(addr) (1) 565 566 #define io_remap_page_range remap_page_range 567 568 /* 569 * No page table caches to initialise 570 */ 571 #define pgtable_cache_init() do { } while (0) 572 573 void do_page_fault(struct pt_regs *regs, unsigned long address, 574 unsigned long error_code); 575 576 void __init io_block_mapping(unsigned long virt, phys_addr_t phys, 577 unsigned int size, int flags); 578 579 void __init adjust_total_lowmem(void); 580 void mapin_ram(void); 581 int map_page(unsigned long va, phys_addr_t pa, int flags); 582 583 extern int mem_init_done; 584 extern unsigned long ioremap_base; 585 extern unsigned long ioremap_bot; 586 587 asmlinkage void __init mmu_init(void); 588 589 void __init *early_get_page(void); 590 591 void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle); 592 void consistent_free(void *vaddr); 593 void consistent_sync(void *vaddr, size_t size, int direction); 594 void consistent_sync_page(struct page *page, unsigned long offset, 595 size_t size, int direction); 596 #endif /* __ASSEMBLY__ */ 597 #endif /* __KERNEL__ */ 598 599 #endif /* CONFIG_MMU */ 600 601 #ifndef __ASSEMBLY__ 602 #include <asm-generic/pgtable.h> 603 604 void setup_memory(void); 605 #endif /* __ASSEMBLY__ */ 606 607 #endif /* _ASM_MICROBLAZE_PGTABLE_H */ 608