cpufeature.c (7052e808c44638ed52187f2403df6ed941e1adfa) cpufeature.c (e5ecedcd7cc231a115c11cfed79635583ef4f882)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because

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2371{
2372 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
2373}
2374
2375#ifdef CONFIG_ARM64_POE
2376static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
2377{
2378 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because

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2371{
2372 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
2373}
2374
2375#ifdef CONFIG_ARM64_POE
2376static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
2377{
2378 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE);
2379 sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);
2379 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE);
2380}
2381#endif
2382
2383#ifdef CONFIG_ARM64_GCS
2384static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused)
2385{
2386 /* GCSPR_EL0 is always readable */
2387 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);

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2381#endif
2382
2383#ifdef CONFIG_ARM64_GCS
2384static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused)
2385{
2386 /* GCSPR_EL0 is always readable */
2387 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);

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