1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 unsigned int compat_elf_hwcap3 __read_mostly; 107 #endif 108 109 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 110 EXPORT_SYMBOL(system_cpucaps); 111 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 112 113 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 114 115 bool arm64_use_ng_mappings = false; 116 EXPORT_SYMBOL(arm64_use_ng_mappings); 117 118 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 119 120 /* 121 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 122 * support it? 123 */ 124 static bool __read_mostly allow_mismatched_32bit_el0; 125 126 /* 127 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 128 * seen at least one CPU capable of 32-bit EL0. 129 */ 130 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 131 132 /* 133 * Mask of CPUs supporting 32-bit EL0. 134 * Only valid if arm64_mismatched_32bit_el0 is enabled. 135 */ 136 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 137 138 void dump_cpu_features(void) 139 { 140 /* file-wide pr_fmt adds "CPU features: " prefix */ 141 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 142 } 143 144 #define __ARM64_MAX_POSITIVE(reg, field) \ 145 ((reg##_##field##_SIGNED ? \ 146 BIT(reg##_##field##_WIDTH - 1) : \ 147 BIT(reg##_##field##_WIDTH)) - 1) 148 149 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 150 151 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 152 .sys_reg = SYS_##reg, \ 153 .field_pos = reg##_##field##_SHIFT, \ 154 .field_width = reg##_##field##_WIDTH, \ 155 .sign = reg##_##field##_SIGNED, \ 156 .min_field_value = min_value, \ 157 .max_field_value = max_value, 158 159 /* 160 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 161 * an implicit maximum that depends on the sign-ess of the field. 162 * 163 * An unsigned field will be capped at all ones, while a signed field 164 * will be limited to the positive half only. 165 */ 166 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 167 __ARM64_CPUID_FIELDS(reg, field, \ 168 SYS_FIELD_VALUE(reg, field, min_value), \ 169 __ARM64_MAX_POSITIVE(reg, field)) 170 171 /* 172 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 173 * implicit minimal value to max_value. This should be used when 174 * matching a non-implemented property. 175 */ 176 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 177 __ARM64_CPUID_FIELDS(reg, field, \ 178 __ARM64_MIN_NEGATIVE(reg, field), \ 179 SYS_FIELD_VALUE(reg, field, max_value)) 180 181 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 182 { \ 183 .sign = SIGNED, \ 184 .visible = VISIBLE, \ 185 .strict = STRICT, \ 186 .type = TYPE, \ 187 .shift = SHIFT, \ 188 .width = WIDTH, \ 189 .safe_val = SAFE_VAL, \ 190 } 191 192 /* Define a feature with unsigned values */ 193 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 194 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 195 196 /* Define a feature with a signed value */ 197 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 198 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 199 200 #define ARM64_FTR_END \ 201 { \ 202 .width = 0, \ 203 } 204 205 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 206 207 static bool __system_matches_cap(unsigned int n); 208 209 /* 210 * NOTE: Any changes to the visibility of features should be kept in 211 * sync with the documentation of the CPU feature register ABI. 212 */ 213 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 228 ARM64_FTR_END, 229 }; 230 231 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 247 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 251 ARM64_FTR_END, 252 }; 253 254 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 262 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 272 ARM64_FTR_END, 273 }; 274 275 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 286 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 287 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 292 ARM64_FTR_END, 293 }; 294 295 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 297 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 303 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 304 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 306 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 307 ARM64_FTR_END, 308 }; 309 310 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 311 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 312 ARM64_FTR_END, 313 }; 314 315 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 336 ARM64_FTR_END, 337 }; 338 339 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 341 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 343 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 345 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 347 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 349 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 351 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 353 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 376 ARM64_FTR_END, 377 }; 378 379 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 386 ARM64_FTR_END, 387 }; 388 389 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 390 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 393 /* 394 * Page size not being supported at Stage-2 is not fatal. You 395 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 396 * your favourite nesting hypervisor. 397 * 398 * There is a small corner case where the hypervisor explicitly 399 * advertises a given granule size at Stage-2 (value 2) on some 400 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 401 * vCPUs. Although this is not forbidden by the architecture, it 402 * indicates that the hypervisor is being silly (or buggy). 403 * 404 * We make no effort to cope with this and pretend that if these 405 * fields are inconsistent across vCPUs, then it isn't worth 406 * trying to bring KVM up. 407 */ 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 411 /* 412 * We already refuse to boot CPUs that don't support our configured 413 * page size, so we can only detect mismatches for a page size other 414 * than the one we're currently using. Unfortunately, SoCs like this 415 * exist in the wild so, even though we don't like it, we'll have to go 416 * along with it and treat them as non-strict. 417 */ 418 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 419 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 421 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 423 /* Linux shouldn't care about secure memory */ 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 427 /* 428 * Differing PARange is fine as long as all peripherals and memory are mapped 429 * within the minimum PARange of all CPUs 430 */ 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 432 ARM64_FTR_END, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 450 ARM64_FTR_END, 451 }; 452 453 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 469 ARM64_FTR_END, 470 }; 471 472 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 473 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 474 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 477 ARM64_FTR_END, 478 }; 479 480 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 481 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 482 ARM64_FTR_END, 483 }; 484 485 static const struct arm64_ftr_bits ftr_ctr[] = { 486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 488 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 489 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 492 /* 493 * Linux can handle differing I-cache policies. Userspace JITs will 494 * make use of *minLine. 495 * If we have differing I-cache policies, report it as the weakest - VIPT. 496 */ 497 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 498 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 499 ARM64_FTR_END, 500 }; 501 502 static struct arm64_ftr_override __ro_after_init no_override = { }; 503 504 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 505 .name = "SYS_CTR_EL0", 506 .ftr_bits = ftr_ctr, 507 .override = &no_override, 508 }; 509 510 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 511 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 516 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 519 ARM64_FTR_END, 520 }; 521 522 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 523 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 528 /* 529 * We can instantiate multiple PMU instances with different levels 530 * of support. 531 */ 532 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 534 ARM64_FTR_END, 535 }; 536 537 static const struct arm64_ftr_bits ftr_mvfr0[] = { 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 546 ARM64_FTR_END, 547 }; 548 549 static const struct arm64_ftr_bits ftr_mvfr1[] = { 550 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 558 ARM64_FTR_END, 559 }; 560 561 static const struct arm64_ftr_bits ftr_mvfr2[] = { 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 564 ARM64_FTR_END, 565 }; 566 567 static const struct arm64_ftr_bits ftr_dczid[] = { 568 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 569 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 570 ARM64_FTR_END, 571 }; 572 573 static const struct arm64_ftr_bits ftr_gmid[] = { 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_id_isar0[] = { 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 586 ARM64_FTR_END, 587 }; 588 589 static const struct arm64_ftr_bits ftr_id_isar5[] = { 590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 607 608 /* 609 * SpecSEI = 1 indicates that the PE might generate an SError on an 610 * external abort on speculative read. It is safe to assume that an 611 * SError might be generated than it will not be. Hence it has been 612 * classified as FTR_HIGHER_SAFE. 613 */ 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 615 ARM64_FTR_END, 616 }; 617 618 static const struct arm64_ftr_bits ftr_id_isar4[] = { 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 627 ARM64_FTR_END, 628 }; 629 630 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 static const struct arm64_ftr_bits ftr_id_isar6[] = { 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 643 ARM64_FTR_END, 644 }; 645 646 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 653 ARM64_FTR_END, 654 }; 655 656 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 665 ARM64_FTR_END, 666 }; 667 668 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 675 /* [31:28] TraceFilt */ 676 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 683 ARM64_FTR_END, 684 }; 685 686 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 687 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 688 ARM64_FTR_END, 689 }; 690 691 static const struct arm64_ftr_bits ftr_mpamidr[] = { 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 696 ARM64_FTR_END, 697 }; 698 699 /* 700 * Common ftr bits for a 32bit register with all hidden, strict 701 * attributes, with 4bit feature fields and a default safe value of 702 * 0. Covers the following 32bit registers: 703 * id_isar[1-3], id_mmfr[1-3] 704 */ 705 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 714 ARM64_FTR_END, 715 }; 716 717 /* Table for a single 32bit feature value */ 718 static const struct arm64_ftr_bits ftr_single32[] = { 719 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 720 ARM64_FTR_END, 721 }; 722 723 static const struct arm64_ftr_bits ftr_raz[] = { 724 ARM64_FTR_END, 725 }; 726 727 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 728 .sys_id = id, \ 729 .reg = &(struct arm64_ftr_reg){ \ 730 .name = id_str, \ 731 .override = (ovr), \ 732 .ftr_bits = &((table)[0]), \ 733 }} 734 735 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 736 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 737 738 #define ARM64_FTR_REG(id, table) \ 739 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 740 741 struct arm64_ftr_override id_aa64mmfr0_override; 742 struct arm64_ftr_override id_aa64mmfr1_override; 743 struct arm64_ftr_override id_aa64mmfr2_override; 744 struct arm64_ftr_override id_aa64pfr0_override; 745 struct arm64_ftr_override id_aa64pfr1_override; 746 struct arm64_ftr_override id_aa64zfr0_override; 747 struct arm64_ftr_override id_aa64smfr0_override; 748 struct arm64_ftr_override id_aa64isar1_override; 749 struct arm64_ftr_override id_aa64isar2_override; 750 751 struct arm64_ftr_override arm64_sw_feature_override; 752 753 static const struct __ftr_reg_entry { 754 u32 sys_id; 755 struct arm64_ftr_reg *reg; 756 } arm64_ftr_regs[] = { 757 758 /* Op1 = 0, CRn = 0, CRm = 1 */ 759 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 760 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 761 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 762 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 763 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 764 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 765 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 766 767 /* Op1 = 0, CRn = 0, CRm = 2 */ 768 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 769 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 770 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 771 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 772 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 773 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 774 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 775 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 776 777 /* Op1 = 0, CRn = 0, CRm = 3 */ 778 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 779 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 780 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 781 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 782 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 783 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 784 785 /* Op1 = 0, CRn = 0, CRm = 4 */ 786 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 787 &id_aa64pfr0_override), 788 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 789 &id_aa64pfr1_override), 790 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 791 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 792 &id_aa64zfr0_override), 793 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 794 &id_aa64smfr0_override), 795 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 796 797 /* Op1 = 0, CRn = 0, CRm = 5 */ 798 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 799 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 800 801 /* Op1 = 0, CRn = 0, CRm = 6 */ 802 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 803 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 804 &id_aa64isar1_override), 805 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 806 &id_aa64isar2_override), 807 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 808 809 /* Op1 = 0, CRn = 0, CRm = 7 */ 810 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 811 &id_aa64mmfr0_override), 812 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 813 &id_aa64mmfr1_override), 814 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 815 &id_aa64mmfr2_override), 816 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 817 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 818 819 /* Op1 = 0, CRn = 10, CRm = 4 */ 820 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 821 822 /* Op1 = 1, CRn = 0, CRm = 0 */ 823 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 824 825 /* Op1 = 3, CRn = 0, CRm = 0 */ 826 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 827 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 828 829 /* Op1 = 3, CRn = 14, CRm = 0 */ 830 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 831 }; 832 833 static int search_cmp_ftr_reg(const void *id, const void *regp) 834 { 835 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 836 } 837 838 /* 839 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 840 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 841 * ascending order of sys_id, we use binary search to find a matching 842 * entry. 843 * 844 * returns - Upon success, matching ftr_reg entry for id. 845 * - NULL on failure. It is upto the caller to decide 846 * the impact of a failure. 847 */ 848 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 849 { 850 const struct __ftr_reg_entry *ret; 851 852 ret = bsearch((const void *)(unsigned long)sys_id, 853 arm64_ftr_regs, 854 ARRAY_SIZE(arm64_ftr_regs), 855 sizeof(arm64_ftr_regs[0]), 856 search_cmp_ftr_reg); 857 if (ret) 858 return ret->reg; 859 return NULL; 860 } 861 862 /* 863 * get_arm64_ftr_reg - Looks up a feature register entry using 864 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 865 * 866 * returns - Upon success, matching ftr_reg entry for id. 867 * - NULL on failure but with an WARN_ON(). 868 */ 869 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 870 { 871 struct arm64_ftr_reg *reg; 872 873 reg = get_arm64_ftr_reg_nowarn(sys_id); 874 875 /* 876 * Requesting a non-existent register search is an error. Warn 877 * and let the caller handle it. 878 */ 879 WARN_ON(!reg); 880 return reg; 881 } 882 883 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 884 s64 ftr_val) 885 { 886 u64 mask = arm64_ftr_mask(ftrp); 887 888 reg &= ~mask; 889 reg |= (ftr_val << ftrp->shift) & mask; 890 return reg; 891 } 892 893 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 894 s64 cur) 895 { 896 s64 ret = 0; 897 898 switch (ftrp->type) { 899 case FTR_EXACT: 900 ret = ftrp->safe_val; 901 break; 902 case FTR_LOWER_SAFE: 903 ret = min(new, cur); 904 break; 905 case FTR_HIGHER_OR_ZERO_SAFE: 906 if (!cur || !new) 907 break; 908 fallthrough; 909 case FTR_HIGHER_SAFE: 910 ret = max(new, cur); 911 break; 912 default: 913 BUG(); 914 } 915 916 return ret; 917 } 918 919 static void __init sort_ftr_regs(void) 920 { 921 unsigned int i; 922 923 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 924 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 925 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 926 unsigned int j = 0; 927 928 /* 929 * Features here must be sorted in descending order with respect 930 * to their shift values and should not overlap with each other. 931 */ 932 for (; ftr_bits->width != 0; ftr_bits++, j++) { 933 unsigned int width = ftr_reg->ftr_bits[j].width; 934 unsigned int shift = ftr_reg->ftr_bits[j].shift; 935 unsigned int prev_shift; 936 937 WARN((shift + width) > 64, 938 "%s has invalid feature at shift %d\n", 939 ftr_reg->name, shift); 940 941 /* 942 * Skip the first feature. There is nothing to 943 * compare against for now. 944 */ 945 if (j == 0) 946 continue; 947 948 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 949 WARN((shift + width) > prev_shift, 950 "%s has feature overlap at shift %d\n", 951 ftr_reg->name, shift); 952 } 953 954 /* 955 * Skip the first register. There is nothing to 956 * compare against for now. 957 */ 958 if (i == 0) 959 continue; 960 /* 961 * Registers here must be sorted in ascending order with respect 962 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 963 * to work correctly. 964 */ 965 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 966 } 967 } 968 969 /* 970 * Initialise the CPU feature register from Boot CPU values. 971 * Also initiliases the strict_mask for the register. 972 * Any bits that are not covered by an arm64_ftr_bits entry are considered 973 * RES0 for the system-wide value, and must strictly match. 974 */ 975 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 976 { 977 u64 val = 0; 978 u64 strict_mask = ~0x0ULL; 979 u64 user_mask = 0; 980 u64 valid_mask = 0; 981 982 const struct arm64_ftr_bits *ftrp; 983 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 984 985 if (!reg) 986 return; 987 988 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 989 u64 ftr_mask = arm64_ftr_mask(ftrp); 990 s64 ftr_new = arm64_ftr_value(ftrp, new); 991 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 992 993 if ((ftr_mask & reg->override->mask) == ftr_mask) { 994 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 995 char *str = NULL; 996 997 if (ftr_ovr != tmp) { 998 /* Unsafe, remove the override */ 999 reg->override->mask &= ~ftr_mask; 1000 reg->override->val &= ~ftr_mask; 1001 tmp = ftr_ovr; 1002 str = "ignoring override"; 1003 } else if (ftr_new != tmp) { 1004 /* Override was valid */ 1005 ftr_new = tmp; 1006 str = "forced"; 1007 } else { 1008 /* Override was the safe value */ 1009 str = "already set"; 1010 } 1011 1012 pr_warn("%s[%d:%d]: %s to %llx\n", 1013 reg->name, 1014 ftrp->shift + ftrp->width - 1, 1015 ftrp->shift, str, 1016 tmp & (BIT(ftrp->width) - 1)); 1017 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1018 reg->override->val &= ~ftr_mask; 1019 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1020 reg->name, 1021 ftrp->shift + ftrp->width - 1, 1022 ftrp->shift); 1023 } 1024 1025 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1026 1027 valid_mask |= ftr_mask; 1028 if (!ftrp->strict) 1029 strict_mask &= ~ftr_mask; 1030 if (ftrp->visible) 1031 user_mask |= ftr_mask; 1032 else 1033 reg->user_val = arm64_ftr_set_value(ftrp, 1034 reg->user_val, 1035 ftrp->safe_val); 1036 } 1037 1038 val &= valid_mask; 1039 1040 reg->sys_val = val; 1041 reg->strict_mask = strict_mask; 1042 reg->user_mask = user_mask; 1043 } 1044 1045 extern const struct arm64_cpu_capabilities arm64_errata[]; 1046 static const struct arm64_cpu_capabilities arm64_features[]; 1047 1048 static void __init 1049 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1050 { 1051 for (; caps->matches; caps++) { 1052 if (WARN(caps->capability >= ARM64_NCAPS, 1053 "Invalid capability %d\n", caps->capability)) 1054 continue; 1055 if (WARN(cpucap_ptrs[caps->capability], 1056 "Duplicate entry for capability %d\n", 1057 caps->capability)) 1058 continue; 1059 cpucap_ptrs[caps->capability] = caps; 1060 } 1061 } 1062 1063 static void __init init_cpucap_indirect_list(void) 1064 { 1065 init_cpucap_indirect_list_from_array(arm64_features); 1066 init_cpucap_indirect_list_from_array(arm64_errata); 1067 } 1068 1069 static void __init setup_boot_cpu_capabilities(void); 1070 1071 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1072 { 1073 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1074 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1075 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1076 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1077 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1078 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1079 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1080 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1081 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1082 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1083 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1084 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1085 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1086 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1087 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1088 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1089 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1090 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1091 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1092 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1093 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1094 } 1095 1096 #ifdef CONFIG_ARM64_PSEUDO_NMI 1097 static bool enable_pseudo_nmi; 1098 1099 static int __init early_enable_pseudo_nmi(char *p) 1100 { 1101 return kstrtobool(p, &enable_pseudo_nmi); 1102 } 1103 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1104 1105 static __init void detect_system_supports_pseudo_nmi(void) 1106 { 1107 struct device_node *np; 1108 1109 if (!enable_pseudo_nmi) 1110 return; 1111 1112 /* 1113 * Detect broken MediaTek firmware that doesn't properly save and 1114 * restore GIC priorities. 1115 */ 1116 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1117 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1118 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1119 enable_pseudo_nmi = false; 1120 } 1121 of_node_put(np); 1122 } 1123 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1124 static inline void detect_system_supports_pseudo_nmi(void) { } 1125 #endif 1126 1127 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1128 { 1129 /* Before we start using the tables, make sure it is sorted */ 1130 sort_ftr_regs(); 1131 1132 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1133 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1134 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1135 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1136 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1137 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1138 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1139 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1140 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1141 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1142 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1143 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1144 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1145 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1146 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1147 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1148 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1149 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1150 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1151 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1152 1153 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1154 init_32bit_cpu_features(&info->aarch32); 1155 1156 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1157 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1158 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1159 1160 vec_init_vq_map(ARM64_VEC_SVE); 1161 1162 cpacr_restore(cpacr); 1163 } 1164 1165 if (IS_ENABLED(CONFIG_ARM64_SME) && 1166 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1167 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1168 1169 /* 1170 * We mask out SMPS since even if the hardware 1171 * supports priorities the kernel does not at present 1172 * and we block access to them. 1173 */ 1174 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1175 vec_init_vq_map(ARM64_VEC_SME); 1176 1177 cpacr_restore(cpacr); 1178 } 1179 1180 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) 1181 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1182 1183 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1184 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1185 } 1186 1187 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1188 { 1189 const struct arm64_ftr_bits *ftrp; 1190 1191 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1192 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1193 s64 ftr_new = arm64_ftr_value(ftrp, new); 1194 1195 if (ftr_cur == ftr_new) 1196 continue; 1197 /* Find a safe value */ 1198 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1199 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1200 } 1201 1202 } 1203 1204 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1205 { 1206 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1207 1208 if (!regp) 1209 return 0; 1210 1211 update_cpu_ftr_reg(regp, val); 1212 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1213 return 0; 1214 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1215 regp->name, boot, cpu, val); 1216 return 1; 1217 } 1218 1219 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1220 { 1221 const struct arm64_ftr_bits *ftrp; 1222 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1223 1224 if (!regp) 1225 return; 1226 1227 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1228 if (ftrp->shift == field) { 1229 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1230 break; 1231 } 1232 } 1233 1234 /* Bogus field? */ 1235 WARN_ON(!ftrp->width); 1236 } 1237 1238 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1239 struct cpuinfo_arm64 *boot) 1240 { 1241 static bool boot_cpu_32bit_regs_overridden = false; 1242 1243 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1244 return; 1245 1246 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1247 return; 1248 1249 boot->aarch32 = info->aarch32; 1250 init_32bit_cpu_features(&boot->aarch32); 1251 boot_cpu_32bit_regs_overridden = true; 1252 } 1253 1254 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1255 struct cpuinfo_32bit *boot) 1256 { 1257 int taint = 0; 1258 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1259 1260 /* 1261 * If we don't have AArch32 at EL1, then relax the strictness of 1262 * EL1-dependent register fields to avoid spurious sanity check fails. 1263 */ 1264 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1265 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1266 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1267 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1268 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1269 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1270 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1271 } 1272 1273 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1274 info->reg_id_dfr0, boot->reg_id_dfr0); 1275 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1276 info->reg_id_dfr1, boot->reg_id_dfr1); 1277 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1278 info->reg_id_isar0, boot->reg_id_isar0); 1279 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1280 info->reg_id_isar1, boot->reg_id_isar1); 1281 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1282 info->reg_id_isar2, boot->reg_id_isar2); 1283 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1284 info->reg_id_isar3, boot->reg_id_isar3); 1285 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1286 info->reg_id_isar4, boot->reg_id_isar4); 1287 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1288 info->reg_id_isar5, boot->reg_id_isar5); 1289 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1290 info->reg_id_isar6, boot->reg_id_isar6); 1291 1292 /* 1293 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1294 * ACTLR formats could differ across CPUs and therefore would have to 1295 * be trapped for virtualization anyway. 1296 */ 1297 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1298 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1299 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1300 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1301 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1302 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1303 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1304 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1305 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1306 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1307 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1308 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1309 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1310 info->reg_id_pfr0, boot->reg_id_pfr0); 1311 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1312 info->reg_id_pfr1, boot->reg_id_pfr1); 1313 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1314 info->reg_id_pfr2, boot->reg_id_pfr2); 1315 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1316 info->reg_mvfr0, boot->reg_mvfr0); 1317 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1318 info->reg_mvfr1, boot->reg_mvfr1); 1319 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1320 info->reg_mvfr2, boot->reg_mvfr2); 1321 1322 return taint; 1323 } 1324 1325 /* 1326 * Update system wide CPU feature registers with the values from a 1327 * non-boot CPU. Also performs SANITY checks to make sure that there 1328 * aren't any insane variations from that of the boot CPU. 1329 */ 1330 void update_cpu_features(int cpu, 1331 struct cpuinfo_arm64 *info, 1332 struct cpuinfo_arm64 *boot) 1333 { 1334 int taint = 0; 1335 1336 /* 1337 * The kernel can handle differing I-cache policies, but otherwise 1338 * caches should look identical. Userspace JITs will make use of 1339 * *minLine. 1340 */ 1341 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1342 info->reg_ctr, boot->reg_ctr); 1343 1344 /* 1345 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1346 * could result in too much or too little memory being zeroed if a 1347 * process is preempted and migrated between CPUs. 1348 */ 1349 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1350 info->reg_dczid, boot->reg_dczid); 1351 1352 /* If different, timekeeping will be broken (especially with KVM) */ 1353 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1354 info->reg_cntfrq, boot->reg_cntfrq); 1355 1356 /* 1357 * The kernel uses self-hosted debug features and expects CPUs to 1358 * support identical debug features. We presently need CTX_CMPs, WRPs, 1359 * and BRPs to be identical. 1360 * ID_AA64DFR1 is currently RES0. 1361 */ 1362 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1363 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1364 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1365 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1366 /* 1367 * Even in big.LITTLE, processors should be identical instruction-set 1368 * wise. 1369 */ 1370 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1371 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1372 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1373 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1374 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1375 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1376 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1377 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1378 1379 /* 1380 * Differing PARange support is fine as long as all peripherals and 1381 * memory are mapped within the minimum PARange of all CPUs. 1382 * Linux should not care about secure memory. 1383 */ 1384 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1385 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1386 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1387 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1388 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1389 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1390 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1391 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1392 1393 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1394 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1395 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1396 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1397 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1398 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1399 1400 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1401 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1402 1403 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1404 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1405 1406 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1407 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1408 1409 /* Probe vector lengths */ 1410 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1411 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1412 if (!system_capabilities_finalized()) { 1413 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1414 1415 vec_update_vq_map(ARM64_VEC_SVE); 1416 1417 cpacr_restore(cpacr); 1418 } 1419 } 1420 1421 if (IS_ENABLED(CONFIG_ARM64_SME) && 1422 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1423 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1424 1425 /* 1426 * We mask out SMPS since even if the hardware 1427 * supports priorities the kernel does not at present 1428 * and we block access to them. 1429 */ 1430 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1431 1432 /* Probe vector lengths */ 1433 if (!system_capabilities_finalized()) 1434 vec_update_vq_map(ARM64_VEC_SME); 1435 1436 cpacr_restore(cpacr); 1437 } 1438 1439 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { 1440 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1441 info->reg_mpamidr, boot->reg_mpamidr); 1442 } 1443 1444 /* 1445 * The kernel uses the LDGM/STGM instructions and the number of tags 1446 * they read/write depends on the GMID_EL1.BS field. Check that the 1447 * value is the same on all CPUs. 1448 */ 1449 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1450 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1451 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1452 info->reg_gmid, boot->reg_gmid); 1453 } 1454 1455 /* 1456 * If we don't have AArch32 at all then skip the checks entirely 1457 * as the register values may be UNKNOWN and we're not going to be 1458 * using them for anything. 1459 * 1460 * This relies on a sanitised view of the AArch64 ID registers 1461 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1462 */ 1463 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1464 lazy_init_32bit_cpu_features(info, boot); 1465 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1466 &boot->aarch32); 1467 } 1468 1469 /* 1470 * Mismatched CPU features are a recipe for disaster. Don't even 1471 * pretend to support them. 1472 */ 1473 if (taint) { 1474 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1475 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1476 } 1477 } 1478 1479 u64 read_sanitised_ftr_reg(u32 id) 1480 { 1481 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1482 1483 if (!regp) 1484 return 0; 1485 return regp->sys_val; 1486 } 1487 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1488 1489 #define read_sysreg_case(r) \ 1490 case r: val = read_sysreg_s(r); break; 1491 1492 /* 1493 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1494 * Read the system register on the current CPU 1495 */ 1496 u64 __read_sysreg_by_encoding(u32 sys_id) 1497 { 1498 struct arm64_ftr_reg *regp; 1499 u64 val; 1500 1501 switch (sys_id) { 1502 read_sysreg_case(SYS_ID_PFR0_EL1); 1503 read_sysreg_case(SYS_ID_PFR1_EL1); 1504 read_sysreg_case(SYS_ID_PFR2_EL1); 1505 read_sysreg_case(SYS_ID_DFR0_EL1); 1506 read_sysreg_case(SYS_ID_DFR1_EL1); 1507 read_sysreg_case(SYS_ID_MMFR0_EL1); 1508 read_sysreg_case(SYS_ID_MMFR1_EL1); 1509 read_sysreg_case(SYS_ID_MMFR2_EL1); 1510 read_sysreg_case(SYS_ID_MMFR3_EL1); 1511 read_sysreg_case(SYS_ID_MMFR4_EL1); 1512 read_sysreg_case(SYS_ID_MMFR5_EL1); 1513 read_sysreg_case(SYS_ID_ISAR0_EL1); 1514 read_sysreg_case(SYS_ID_ISAR1_EL1); 1515 read_sysreg_case(SYS_ID_ISAR2_EL1); 1516 read_sysreg_case(SYS_ID_ISAR3_EL1); 1517 read_sysreg_case(SYS_ID_ISAR4_EL1); 1518 read_sysreg_case(SYS_ID_ISAR5_EL1); 1519 read_sysreg_case(SYS_ID_ISAR6_EL1); 1520 read_sysreg_case(SYS_MVFR0_EL1); 1521 read_sysreg_case(SYS_MVFR1_EL1); 1522 read_sysreg_case(SYS_MVFR2_EL1); 1523 1524 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1525 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1526 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1527 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1528 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1529 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1530 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1531 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1532 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1533 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1534 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1535 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1536 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1537 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1538 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1539 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1540 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1541 1542 read_sysreg_case(SYS_CNTFRQ_EL0); 1543 read_sysreg_case(SYS_CTR_EL0); 1544 read_sysreg_case(SYS_DCZID_EL0); 1545 1546 default: 1547 BUG(); 1548 return 0; 1549 } 1550 1551 regp = get_arm64_ftr_reg(sys_id); 1552 if (regp) { 1553 val &= ~regp->override->mask; 1554 val |= (regp->override->val & regp->override->mask); 1555 } 1556 1557 return val; 1558 } 1559 1560 #include <linux/irqchip/arm-gic-v3.h> 1561 1562 static bool 1563 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1564 { 1565 return true; 1566 } 1567 1568 static bool 1569 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1570 { 1571 int val, min, max; 1572 u64 tmp; 1573 1574 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1575 entry->field_width, 1576 entry->sign); 1577 1578 tmp = entry->min_field_value; 1579 tmp <<= entry->field_pos; 1580 1581 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1582 entry->field_width, 1583 entry->sign); 1584 1585 tmp = entry->max_field_value; 1586 tmp <<= entry->field_pos; 1587 1588 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1589 entry->field_width, 1590 entry->sign); 1591 1592 return val >= min && val <= max; 1593 } 1594 1595 static u64 1596 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1597 { 1598 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1599 if (scope == SCOPE_SYSTEM) 1600 return read_sanitised_ftr_reg(entry->sys_reg); 1601 else 1602 return __read_sysreg_by_encoding(entry->sys_reg); 1603 } 1604 1605 static bool 1606 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1607 { 1608 int mask; 1609 struct arm64_ftr_reg *regp; 1610 u64 val = read_scoped_sysreg(entry, scope); 1611 1612 regp = get_arm64_ftr_reg(entry->sys_reg); 1613 if (!regp) 1614 return false; 1615 1616 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1617 entry->field_pos, 1618 entry->field_width); 1619 if (!mask) 1620 return false; 1621 1622 return feature_matches(val, entry); 1623 } 1624 1625 static bool 1626 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1627 { 1628 u64 val = read_scoped_sysreg(entry, scope); 1629 return feature_matches(val, entry); 1630 } 1631 1632 const struct cpumask *system_32bit_el0_cpumask(void) 1633 { 1634 if (!system_supports_32bit_el0()) 1635 return cpu_none_mask; 1636 1637 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1638 return cpu_32bit_el0_mask; 1639 1640 return cpu_possible_mask; 1641 } 1642 1643 static int __init parse_32bit_el0_param(char *str) 1644 { 1645 allow_mismatched_32bit_el0 = true; 1646 return 0; 1647 } 1648 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1649 1650 static ssize_t aarch32_el0_show(struct device *dev, 1651 struct device_attribute *attr, char *buf) 1652 { 1653 const struct cpumask *mask = system_32bit_el0_cpumask(); 1654 1655 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1656 } 1657 static const DEVICE_ATTR_RO(aarch32_el0); 1658 1659 static int __init aarch32_el0_sysfs_init(void) 1660 { 1661 struct device *dev_root; 1662 int ret = 0; 1663 1664 if (!allow_mismatched_32bit_el0) 1665 return 0; 1666 1667 dev_root = bus_get_dev_root(&cpu_subsys); 1668 if (dev_root) { 1669 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1670 put_device(dev_root); 1671 } 1672 return ret; 1673 } 1674 device_initcall(aarch32_el0_sysfs_init); 1675 1676 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1677 { 1678 if (!has_cpuid_feature(entry, scope)) 1679 return allow_mismatched_32bit_el0; 1680 1681 if (scope == SCOPE_SYSTEM) 1682 pr_info("detected: 32-bit EL0 Support\n"); 1683 1684 return true; 1685 } 1686 1687 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1688 { 1689 bool has_sre; 1690 1691 if (!has_cpuid_feature(entry, scope)) 1692 return false; 1693 1694 has_sre = gic_enable_sre(); 1695 if (!has_sre) 1696 pr_warn_once("%s present but disabled by higher exception level\n", 1697 entry->desc); 1698 1699 return has_sre; 1700 } 1701 1702 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1703 int scope) 1704 { 1705 u64 ctr; 1706 1707 if (scope == SCOPE_SYSTEM) 1708 ctr = arm64_ftr_reg_ctrel0.sys_val; 1709 else 1710 ctr = read_cpuid_effective_cachetype(); 1711 1712 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1713 } 1714 1715 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1716 { 1717 /* 1718 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1719 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1720 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1721 * value. 1722 */ 1723 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1724 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1725 } 1726 1727 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1728 int scope) 1729 { 1730 u64 ctr; 1731 1732 if (scope == SCOPE_SYSTEM) 1733 ctr = arm64_ftr_reg_ctrel0.sys_val; 1734 else 1735 ctr = read_cpuid_cachetype(); 1736 1737 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1738 } 1739 1740 static bool __maybe_unused 1741 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1742 { 1743 /* 1744 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1745 * may share TLB entries with a CPU stuck in the crashed 1746 * kernel. 1747 */ 1748 if (is_kdump_kernel()) 1749 return false; 1750 1751 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1752 return false; 1753 1754 return has_cpuid_feature(entry, scope); 1755 } 1756 1757 static bool __meltdown_safe = true; 1758 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1759 1760 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1761 int scope) 1762 { 1763 /* List of CPUs that are not vulnerable and don't need KPTI */ 1764 static const struct midr_range kpti_safe_list[] = { 1765 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1766 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1767 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1768 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1769 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1770 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1771 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1772 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1773 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1774 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1775 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1776 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1777 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1778 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1779 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1780 { /* sentinel */ } 1781 }; 1782 char const *str = "kpti command line option"; 1783 bool meltdown_safe; 1784 1785 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1786 1787 /* Defer to CPU feature registers */ 1788 if (has_cpuid_feature(entry, scope)) 1789 meltdown_safe = true; 1790 1791 if (!meltdown_safe) 1792 __meltdown_safe = false; 1793 1794 /* 1795 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1796 * ThunderX leads to apparent I-cache corruption of kernel text, which 1797 * ends as well as you might imagine. Don't even try. We cannot rely 1798 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1799 * because cpucap detection order may change. However, since we know 1800 * affected CPUs are always in a homogeneous configuration, it is 1801 * safe to rely on this_cpu_has_cap() here. 1802 */ 1803 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1804 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1805 __kpti_forced = -1; 1806 } 1807 1808 /* Useful for KASLR robustness */ 1809 if (kaslr_enabled() && kaslr_requires_kpti()) { 1810 if (!__kpti_forced) { 1811 str = "KASLR"; 1812 __kpti_forced = 1; 1813 } 1814 } 1815 1816 if (cpu_mitigations_off() && !__kpti_forced) { 1817 str = "mitigations=off"; 1818 __kpti_forced = -1; 1819 } 1820 1821 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1822 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1823 return false; 1824 } 1825 1826 /* Forced? */ 1827 if (__kpti_forced) { 1828 pr_info_once("kernel page table isolation forced %s by %s\n", 1829 __kpti_forced > 0 ? "ON" : "OFF", str); 1830 return __kpti_forced > 0; 1831 } 1832 1833 return !meltdown_safe; 1834 } 1835 1836 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1837 { 1838 /* 1839 * Although the Apple M2 family appears to support NV1, the 1840 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1841 * that it doesn't support NV1 at all. 1842 */ 1843 static const struct midr_range nv1_ni_list[] = { 1844 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1845 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1846 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1847 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1848 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1849 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1850 {} 1851 }; 1852 1853 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1854 !(has_cpuid_feature(entry, scope) || 1855 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list))); 1856 } 1857 1858 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1859 static bool has_lpa2_at_stage1(u64 mmfr0) 1860 { 1861 unsigned int tgran; 1862 1863 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1864 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1865 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1866 } 1867 1868 static bool has_lpa2_at_stage2(u64 mmfr0) 1869 { 1870 unsigned int tgran; 1871 1872 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1873 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1874 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1875 } 1876 1877 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1878 { 1879 u64 mmfr0; 1880 1881 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1882 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1883 } 1884 #else 1885 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1886 { 1887 return false; 1888 } 1889 #endif 1890 1891 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1892 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1893 1894 extern 1895 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1896 phys_addr_t size, pgprot_t prot, 1897 phys_addr_t (*pgtable_alloc)(int), int flags); 1898 1899 static phys_addr_t __initdata kpti_ng_temp_alloc; 1900 1901 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1902 { 1903 kpti_ng_temp_alloc -= PAGE_SIZE; 1904 return kpti_ng_temp_alloc; 1905 } 1906 1907 static int __init __kpti_install_ng_mappings(void *__unused) 1908 { 1909 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1910 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1911 kpti_remap_fn *remap_fn; 1912 1913 int cpu = smp_processor_id(); 1914 int levels = CONFIG_PGTABLE_LEVELS; 1915 int order = order_base_2(levels); 1916 u64 kpti_ng_temp_pgd_pa = 0; 1917 pgd_t *kpti_ng_temp_pgd; 1918 u64 alloc = 0; 1919 1920 if (levels == 5 && !pgtable_l5_enabled()) 1921 levels = 4; 1922 else if (levels == 4 && !pgtable_l4_enabled()) 1923 levels = 3; 1924 1925 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1926 1927 if (!cpu) { 1928 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1929 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1930 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1931 1932 // 1933 // Create a minimal page table hierarchy that permits us to map 1934 // the swapper page tables temporarily as we traverse them. 1935 // 1936 // The physical pages are laid out as follows: 1937 // 1938 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1939 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1940 // +--------+-\-------+-\------ +-\------ +-///--------+ 1941 // ^ 1942 // The first page is mapped into this hierarchy at a PMD_SHIFT 1943 // aligned virtual address, so that we can manipulate the PTE 1944 // level entries while the mapping is active. The first entry 1945 // covers the PTE[] page itself, the remaining entries are free 1946 // to be used as a ad-hoc fixmap. 1947 // 1948 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1949 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1950 kpti_ng_pgd_alloc, 0); 1951 } 1952 1953 cpu_install_idmap(); 1954 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1955 cpu_uninstall_idmap(); 1956 1957 if (!cpu) { 1958 free_pages(alloc, order); 1959 arm64_use_ng_mappings = true; 1960 } 1961 1962 return 0; 1963 } 1964 1965 static void __init kpti_install_ng_mappings(void) 1966 { 1967 /* Check whether KPTI is going to be used */ 1968 if (!arm64_kernel_unmapped_at_el0()) 1969 return; 1970 1971 /* 1972 * We don't need to rewrite the page-tables if either we've done 1973 * it already or we have KASLR enabled and therefore have not 1974 * created any global mappings at all. 1975 */ 1976 if (arm64_use_ng_mappings) 1977 return; 1978 1979 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1980 } 1981 1982 #else 1983 static inline void kpti_install_ng_mappings(void) 1984 { 1985 } 1986 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1987 1988 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1989 { 1990 if (__this_cpu_read(this_cpu_vector) == vectors) { 1991 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1992 1993 __this_cpu_write(this_cpu_vector, v); 1994 } 1995 1996 } 1997 1998 static int __init parse_kpti(char *str) 1999 { 2000 bool enabled; 2001 int ret = kstrtobool(str, &enabled); 2002 2003 if (ret) 2004 return ret; 2005 2006 __kpti_forced = enabled ? 1 : -1; 2007 return 0; 2008 } 2009 early_param("kpti", parse_kpti); 2010 2011 #ifdef CONFIG_ARM64_HW_AFDBM 2012 static struct cpumask dbm_cpus __read_mostly; 2013 2014 static inline void __cpu_enable_hw_dbm(void) 2015 { 2016 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2017 2018 write_sysreg(tcr, tcr_el1); 2019 isb(); 2020 local_flush_tlb_all(); 2021 } 2022 2023 static bool cpu_has_broken_dbm(void) 2024 { 2025 /* List of CPUs which have broken DBM support. */ 2026 static const struct midr_range cpus[] = { 2027 #ifdef CONFIG_ARM64_ERRATUM_1024718 2028 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2029 /* Kryo4xx Silver (rdpe => r1p0) */ 2030 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2031 #endif 2032 #ifdef CONFIG_ARM64_ERRATUM_2051678 2033 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2034 #endif 2035 {}, 2036 }; 2037 2038 return is_midr_in_range_list(read_cpuid_id(), cpus); 2039 } 2040 2041 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2042 { 2043 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2044 !cpu_has_broken_dbm(); 2045 } 2046 2047 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2048 { 2049 if (cpu_can_use_dbm(cap)) { 2050 __cpu_enable_hw_dbm(); 2051 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2052 } 2053 } 2054 2055 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2056 int __unused) 2057 { 2058 /* 2059 * DBM is a non-conflicting feature. i.e, the kernel can safely 2060 * run a mix of CPUs with and without the feature. So, we 2061 * unconditionally enable the capability to allow any late CPU 2062 * to use the feature. We only enable the control bits on the 2063 * CPU, if it is supported. 2064 */ 2065 2066 return true; 2067 } 2068 2069 #endif 2070 2071 #ifdef CONFIG_ARM64_AMU_EXTN 2072 2073 /* 2074 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2075 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2076 * information regarding all the events that it supports. When a CPU bit is 2077 * set in the cpumask, the user of this feature can only rely on the presence 2078 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2079 * counters are enabled or access to these counters is enabled by code 2080 * executed at higher exception levels (firmware). 2081 */ 2082 static struct cpumask amu_cpus __read_mostly; 2083 2084 bool cpu_has_amu_feat(int cpu) 2085 { 2086 return cpumask_test_cpu(cpu, &amu_cpus); 2087 } 2088 2089 int get_cpu_with_amu_feat(void) 2090 { 2091 return cpumask_any(&amu_cpus); 2092 } 2093 2094 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2095 { 2096 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2097 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2098 2099 /* 0 reference values signal broken/disabled counters */ 2100 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2101 update_freq_counters_refs(); 2102 } 2103 } 2104 2105 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2106 int __unused) 2107 { 2108 /* 2109 * The AMU extension is a non-conflicting feature: the kernel can 2110 * safely run a mix of CPUs with and without support for the 2111 * activity monitors extension. Therefore, unconditionally enable 2112 * the capability to allow any late CPU to use the feature. 2113 * 2114 * With this feature unconditionally enabled, the cpu_enable 2115 * function will be called for all CPUs that match the criteria, 2116 * including secondary and hotplugged, marking this feature as 2117 * present on that respective CPU. The enable function will also 2118 * print a detection message. 2119 */ 2120 2121 return true; 2122 } 2123 #else 2124 int get_cpu_with_amu_feat(void) 2125 { 2126 return nr_cpu_ids; 2127 } 2128 #endif 2129 2130 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2131 { 2132 return is_kernel_in_hyp_mode(); 2133 } 2134 2135 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2136 { 2137 /* 2138 * Copy register values that aren't redirected by hardware. 2139 * 2140 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2141 * this value to tpidr_el2 before we patch the code. Once we've done 2142 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2143 * do anything here. 2144 */ 2145 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2146 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2147 } 2148 2149 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2150 int scope) 2151 { 2152 if (kvm_get_mode() != KVM_MODE_NV) 2153 return false; 2154 2155 if (!has_cpuid_feature(cap, scope)) { 2156 pr_warn("unavailable: %s\n", cap->desc); 2157 return false; 2158 } 2159 2160 return true; 2161 } 2162 2163 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2164 int __unused) 2165 { 2166 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2167 } 2168 2169 #ifdef CONFIG_ARM64_PAN 2170 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2171 { 2172 /* 2173 * We modify PSTATE. This won't work from irq context as the PSTATE 2174 * is discarded once we return from the exception. 2175 */ 2176 WARN_ON_ONCE(in_interrupt()); 2177 2178 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2179 set_pstate_pan(1); 2180 } 2181 #endif /* CONFIG_ARM64_PAN */ 2182 2183 #ifdef CONFIG_ARM64_RAS_EXTN 2184 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2185 { 2186 /* Firmware may have left a deferred SError in this register. */ 2187 write_sysreg_s(0, SYS_DISR_EL1); 2188 } 2189 #endif /* CONFIG_ARM64_RAS_EXTN */ 2190 2191 #ifdef CONFIG_ARM64_PTR_AUTH 2192 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2193 { 2194 int boot_val, sec_val; 2195 2196 /* We don't expect to be called with SCOPE_SYSTEM */ 2197 WARN_ON(scope == SCOPE_SYSTEM); 2198 /* 2199 * The ptr-auth feature levels are not intercompatible with lower 2200 * levels. Hence we must match ptr-auth feature level of the secondary 2201 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2202 * from the sanitised register whereas direct register read is done for 2203 * the secondary CPUs. 2204 * The sanitised feature state is guaranteed to match that of the 2205 * boot CPU as a mismatched secondary CPU is parked before it gets 2206 * a chance to update the state, with the capability. 2207 */ 2208 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2209 entry->field_pos, entry->sign); 2210 if (scope & SCOPE_BOOT_CPU) 2211 return boot_val >= entry->min_field_value; 2212 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2213 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2214 entry->field_pos, entry->sign); 2215 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2216 } 2217 2218 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2219 int scope) 2220 { 2221 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2222 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2223 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2224 2225 return apa || apa3 || api; 2226 } 2227 2228 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2229 int __unused) 2230 { 2231 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2232 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2233 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2234 2235 return gpa || gpa3 || gpi; 2236 } 2237 #endif /* CONFIG_ARM64_PTR_AUTH */ 2238 2239 #ifdef CONFIG_ARM64_E0PD 2240 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2241 { 2242 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2243 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2244 } 2245 #endif /* CONFIG_ARM64_E0PD */ 2246 2247 #ifdef CONFIG_ARM64_PSEUDO_NMI 2248 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2249 int scope) 2250 { 2251 /* 2252 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2253 * feature, so will be detected earlier. 2254 */ 2255 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2256 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2257 return false; 2258 2259 return enable_pseudo_nmi; 2260 } 2261 2262 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2263 int scope) 2264 { 2265 /* 2266 * If we're not using priority masking then we won't be poking PMR_EL1, 2267 * and there's no need to relax synchronization of writes to it, and 2268 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2269 * that. 2270 * 2271 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2272 * feature, so will be detected earlier. 2273 */ 2274 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2275 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2276 return false; 2277 2278 /* 2279 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2280 * hint for interrupt distribution, a DSB is not necessary when 2281 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2282 * 2283 * Linux itself doesn't use 1:N distribution, so has no need to 2284 * set PMHE. The only reason to have it set is if EL3 requires it 2285 * (and we can't change it). 2286 */ 2287 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2288 } 2289 #endif 2290 2291 #ifdef CONFIG_ARM64_BTI 2292 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2293 { 2294 /* 2295 * Use of X16/X17 for tail-calls and trampolines that jump to 2296 * function entry points using BR is a requirement for 2297 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2298 * So, be strict and forbid other BRs using other registers to 2299 * jump onto a PACIxSP instruction: 2300 */ 2301 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2302 isb(); 2303 } 2304 #endif /* CONFIG_ARM64_BTI */ 2305 2306 #ifdef CONFIG_ARM64_MTE 2307 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2308 { 2309 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2310 2311 mte_cpu_setup(); 2312 2313 /* 2314 * Clear the tags in the zero page. This needs to be done via the 2315 * linear map which has the Tagged attribute. 2316 */ 2317 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2318 mte_clear_page_tags(lm_alias(empty_zero_page)); 2319 set_page_mte_tagged(ZERO_PAGE(0)); 2320 } 2321 2322 kasan_init_hw_tags_cpu(); 2323 } 2324 #endif /* CONFIG_ARM64_MTE */ 2325 2326 static void user_feature_fixup(void) 2327 { 2328 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2329 struct arm64_ftr_reg *regp; 2330 2331 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2332 if (regp) 2333 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2334 } 2335 2336 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2337 struct arm64_ftr_reg *regp; 2338 2339 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2340 if (regp) 2341 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2342 } 2343 } 2344 2345 static void elf_hwcap_fixup(void) 2346 { 2347 #ifdef CONFIG_COMPAT 2348 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2349 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2350 #endif /* CONFIG_COMPAT */ 2351 } 2352 2353 #ifdef CONFIG_KVM 2354 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2355 { 2356 return kvm_get_mode() == KVM_MODE_PROTECTED; 2357 } 2358 #endif /* CONFIG_KVM */ 2359 2360 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2361 { 2362 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2363 } 2364 2365 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2366 { 2367 set_pstate_dit(1); 2368 } 2369 2370 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2371 { 2372 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2373 } 2374 2375 #ifdef CONFIG_ARM64_POE 2376 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2377 { 2378 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2379 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2380 } 2381 #endif 2382 2383 #ifdef CONFIG_ARM64_GCS 2384 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2385 { 2386 /* GCSPR_EL0 is always readable */ 2387 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2388 } 2389 #endif 2390 2391 /* Internal helper functions to match cpu capability type */ 2392 static bool 2393 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2394 { 2395 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2396 } 2397 2398 static bool 2399 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2400 { 2401 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2402 } 2403 2404 static bool 2405 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2406 { 2407 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2408 } 2409 2410 static bool 2411 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2412 { 2413 if (!has_cpuid_feature(entry, scope)) 2414 return false; 2415 2416 /* Check firmware actually enabled MPAM on this cpu. */ 2417 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2418 } 2419 2420 static void 2421 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2422 { 2423 /* 2424 * Access by the kernel (at EL1) should use the reserved PARTID 2425 * which is configured unrestricted. This avoids priority-inversion 2426 * where latency sensitive tasks have to wait for a task that has 2427 * been throttled to release the lock. 2428 */ 2429 write_sysreg_s(0, SYS_MPAM1_EL1); 2430 } 2431 2432 static bool 2433 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2434 { 2435 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2436 2437 return idr & MPAMIDR_EL1_HAS_HCR; 2438 } 2439 2440 static const struct arm64_cpu_capabilities arm64_features[] = { 2441 { 2442 .capability = ARM64_ALWAYS_BOOT, 2443 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2444 .matches = has_always, 2445 }, 2446 { 2447 .capability = ARM64_ALWAYS_SYSTEM, 2448 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2449 .matches = has_always, 2450 }, 2451 { 2452 .desc = "GIC system register CPU interface", 2453 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2454 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2455 .matches = has_useable_gicv3_cpuif, 2456 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2457 }, 2458 { 2459 .desc = "Enhanced Counter Virtualization", 2460 .capability = ARM64_HAS_ECV, 2461 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2462 .matches = has_cpuid_feature, 2463 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2464 }, 2465 { 2466 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2467 .capability = ARM64_HAS_ECV_CNTPOFF, 2468 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2469 .matches = has_cpuid_feature, 2470 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2471 }, 2472 #ifdef CONFIG_ARM64_PAN 2473 { 2474 .desc = "Privileged Access Never", 2475 .capability = ARM64_HAS_PAN, 2476 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2477 .matches = has_cpuid_feature, 2478 .cpu_enable = cpu_enable_pan, 2479 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2480 }, 2481 #endif /* CONFIG_ARM64_PAN */ 2482 #ifdef CONFIG_ARM64_EPAN 2483 { 2484 .desc = "Enhanced Privileged Access Never", 2485 .capability = ARM64_HAS_EPAN, 2486 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2487 .matches = has_cpuid_feature, 2488 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2489 }, 2490 #endif /* CONFIG_ARM64_EPAN */ 2491 #ifdef CONFIG_ARM64_LSE_ATOMICS 2492 { 2493 .desc = "LSE atomic instructions", 2494 .capability = ARM64_HAS_LSE_ATOMICS, 2495 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2496 .matches = has_cpuid_feature, 2497 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2498 }, 2499 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2500 { 2501 .desc = "Virtualization Host Extensions", 2502 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2503 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2504 .matches = runs_at_el2, 2505 .cpu_enable = cpu_copy_el2regs, 2506 }, 2507 { 2508 .desc = "Nested Virtualization Support", 2509 .capability = ARM64_HAS_NESTED_VIRT, 2510 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2511 .matches = has_nested_virt_support, 2512 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2513 }, 2514 { 2515 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2516 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2517 .matches = has_32bit_el0, 2518 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2519 }, 2520 #ifdef CONFIG_KVM 2521 { 2522 .desc = "32-bit EL1 Support", 2523 .capability = ARM64_HAS_32BIT_EL1, 2524 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2525 .matches = has_cpuid_feature, 2526 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2527 }, 2528 { 2529 .desc = "Protected KVM", 2530 .capability = ARM64_KVM_PROTECTED_MODE, 2531 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2532 .matches = is_kvm_protected_mode, 2533 }, 2534 { 2535 .desc = "HCRX_EL2 register", 2536 .capability = ARM64_HAS_HCX, 2537 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2538 .matches = has_cpuid_feature, 2539 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2540 }, 2541 #endif 2542 { 2543 .desc = "Kernel page table isolation (KPTI)", 2544 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2545 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2546 .cpu_enable = cpu_enable_kpti, 2547 .matches = unmap_kernel_at_el0, 2548 /* 2549 * The ID feature fields below are used to indicate that 2550 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2551 * more details. 2552 */ 2553 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2554 }, 2555 { 2556 .capability = ARM64_HAS_FPSIMD, 2557 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2558 .matches = has_cpuid_feature, 2559 .cpu_enable = cpu_enable_fpsimd, 2560 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2561 }, 2562 #ifdef CONFIG_ARM64_PMEM 2563 { 2564 .desc = "Data cache clean to Point of Persistence", 2565 .capability = ARM64_HAS_DCPOP, 2566 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2567 .matches = has_cpuid_feature, 2568 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2569 }, 2570 { 2571 .desc = "Data cache clean to Point of Deep Persistence", 2572 .capability = ARM64_HAS_DCPODP, 2573 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2574 .matches = has_cpuid_feature, 2575 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2576 }, 2577 #endif 2578 #ifdef CONFIG_ARM64_SVE 2579 { 2580 .desc = "Scalable Vector Extension", 2581 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2582 .capability = ARM64_SVE, 2583 .cpu_enable = cpu_enable_sve, 2584 .matches = has_cpuid_feature, 2585 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2586 }, 2587 #endif /* CONFIG_ARM64_SVE */ 2588 #ifdef CONFIG_ARM64_RAS_EXTN 2589 { 2590 .desc = "RAS Extension Support", 2591 .capability = ARM64_HAS_RAS_EXTN, 2592 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2593 .matches = has_cpuid_feature, 2594 .cpu_enable = cpu_clear_disr, 2595 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2596 }, 2597 #endif /* CONFIG_ARM64_RAS_EXTN */ 2598 #ifdef CONFIG_ARM64_AMU_EXTN 2599 { 2600 .desc = "Activity Monitors Unit (AMU)", 2601 .capability = ARM64_HAS_AMU_EXTN, 2602 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2603 .matches = has_amu, 2604 .cpu_enable = cpu_amu_enable, 2605 .cpus = &amu_cpus, 2606 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2607 }, 2608 #endif /* CONFIG_ARM64_AMU_EXTN */ 2609 { 2610 .desc = "Data cache clean to the PoU not required for I/D coherence", 2611 .capability = ARM64_HAS_CACHE_IDC, 2612 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2613 .matches = has_cache_idc, 2614 .cpu_enable = cpu_emulate_effective_ctr, 2615 }, 2616 { 2617 .desc = "Instruction cache invalidation not required for I/D coherence", 2618 .capability = ARM64_HAS_CACHE_DIC, 2619 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2620 .matches = has_cache_dic, 2621 }, 2622 { 2623 .desc = "Stage-2 Force Write-Back", 2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2625 .capability = ARM64_HAS_STAGE2_FWB, 2626 .matches = has_cpuid_feature, 2627 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2628 }, 2629 { 2630 .desc = "ARMv8.4 Translation Table Level", 2631 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2632 .capability = ARM64_HAS_ARMv8_4_TTL, 2633 .matches = has_cpuid_feature, 2634 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2635 }, 2636 { 2637 .desc = "TLB range maintenance instructions", 2638 .capability = ARM64_HAS_TLB_RANGE, 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .matches = has_cpuid_feature, 2641 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2642 }, 2643 #ifdef CONFIG_ARM64_HW_AFDBM 2644 { 2645 .desc = "Hardware dirty bit management", 2646 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2647 .capability = ARM64_HW_DBM, 2648 .matches = has_hw_dbm, 2649 .cpu_enable = cpu_enable_hw_dbm, 2650 .cpus = &dbm_cpus, 2651 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2652 }, 2653 #endif 2654 #ifdef CONFIG_ARM64_HAFT 2655 { 2656 .desc = "Hardware managed Access Flag for Table Descriptors", 2657 /* 2658 * Contrary to the page/block access flag, the table access flag 2659 * cannot be emulated in software (no access fault will occur). 2660 * Therefore this should be used only if it's supported system 2661 * wide. 2662 */ 2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2664 .capability = ARM64_HAFT, 2665 .matches = has_cpuid_feature, 2666 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2667 }, 2668 #endif 2669 { 2670 .desc = "CRC32 instructions", 2671 .capability = ARM64_HAS_CRC32, 2672 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2673 .matches = has_cpuid_feature, 2674 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2675 }, 2676 { 2677 .desc = "Speculative Store Bypassing Safe (SSBS)", 2678 .capability = ARM64_SSBS, 2679 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2680 .matches = has_cpuid_feature, 2681 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2682 }, 2683 #ifdef CONFIG_ARM64_CNP 2684 { 2685 .desc = "Common not Private translations", 2686 .capability = ARM64_HAS_CNP, 2687 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2688 .matches = has_useable_cnp, 2689 .cpu_enable = cpu_enable_cnp, 2690 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2691 }, 2692 #endif 2693 { 2694 .desc = "Speculation barrier (SB)", 2695 .capability = ARM64_HAS_SB, 2696 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2697 .matches = has_cpuid_feature, 2698 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2699 }, 2700 #ifdef CONFIG_ARM64_PTR_AUTH 2701 { 2702 .desc = "Address authentication (architected QARMA5 algorithm)", 2703 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2704 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2705 .matches = has_address_auth_cpucap, 2706 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2707 }, 2708 { 2709 .desc = "Address authentication (architected QARMA3 algorithm)", 2710 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2711 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2712 .matches = has_address_auth_cpucap, 2713 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2714 }, 2715 { 2716 .desc = "Address authentication (IMP DEF algorithm)", 2717 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2718 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2719 .matches = has_address_auth_cpucap, 2720 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2721 }, 2722 { 2723 .capability = ARM64_HAS_ADDRESS_AUTH, 2724 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2725 .matches = has_address_auth_metacap, 2726 }, 2727 { 2728 .desc = "Generic authentication (architected QARMA5 algorithm)", 2729 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2730 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2731 .matches = has_cpuid_feature, 2732 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2733 }, 2734 { 2735 .desc = "Generic authentication (architected QARMA3 algorithm)", 2736 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2737 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2738 .matches = has_cpuid_feature, 2739 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2740 }, 2741 { 2742 .desc = "Generic authentication (IMP DEF algorithm)", 2743 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2744 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2745 .matches = has_cpuid_feature, 2746 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2747 }, 2748 { 2749 .capability = ARM64_HAS_GENERIC_AUTH, 2750 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2751 .matches = has_generic_auth, 2752 }, 2753 #endif /* CONFIG_ARM64_PTR_AUTH */ 2754 #ifdef CONFIG_ARM64_PSEUDO_NMI 2755 { 2756 /* 2757 * Depends on having GICv3 2758 */ 2759 .desc = "IRQ priority masking", 2760 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2761 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2762 .matches = can_use_gic_priorities, 2763 }, 2764 { 2765 /* 2766 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2767 */ 2768 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2769 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2770 .matches = has_gic_prio_relaxed_sync, 2771 }, 2772 #endif 2773 #ifdef CONFIG_ARM64_E0PD 2774 { 2775 .desc = "E0PD", 2776 .capability = ARM64_HAS_E0PD, 2777 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2778 .cpu_enable = cpu_enable_e0pd, 2779 .matches = has_cpuid_feature, 2780 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2781 }, 2782 #endif 2783 { 2784 .desc = "Random Number Generator", 2785 .capability = ARM64_HAS_RNG, 2786 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2787 .matches = has_cpuid_feature, 2788 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2789 }, 2790 #ifdef CONFIG_ARM64_BTI 2791 { 2792 .desc = "Branch Target Identification", 2793 .capability = ARM64_BTI, 2794 #ifdef CONFIG_ARM64_BTI_KERNEL 2795 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2796 #else 2797 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2798 #endif 2799 .matches = has_cpuid_feature, 2800 .cpu_enable = bti_enable, 2801 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2802 }, 2803 #endif 2804 #ifdef CONFIG_ARM64_MTE 2805 { 2806 .desc = "Memory Tagging Extension", 2807 .capability = ARM64_MTE, 2808 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2809 .matches = has_cpuid_feature, 2810 .cpu_enable = cpu_enable_mte, 2811 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2812 }, 2813 { 2814 .desc = "Asymmetric MTE Tag Check Fault", 2815 .capability = ARM64_MTE_ASYMM, 2816 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2817 .matches = has_cpuid_feature, 2818 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2819 }, 2820 #endif /* CONFIG_ARM64_MTE */ 2821 { 2822 .desc = "RCpc load-acquire (LDAPR)", 2823 .capability = ARM64_HAS_LDAPR, 2824 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2825 .matches = has_cpuid_feature, 2826 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2827 }, 2828 { 2829 .desc = "Fine Grained Traps", 2830 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2831 .capability = ARM64_HAS_FGT, 2832 .matches = has_cpuid_feature, 2833 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2834 }, 2835 #ifdef CONFIG_ARM64_SME 2836 { 2837 .desc = "Scalable Matrix Extension", 2838 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2839 .capability = ARM64_SME, 2840 .matches = has_cpuid_feature, 2841 .cpu_enable = cpu_enable_sme, 2842 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2843 }, 2844 /* FA64 should be sorted after the base SME capability */ 2845 { 2846 .desc = "FA64", 2847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2848 .capability = ARM64_SME_FA64, 2849 .matches = has_cpuid_feature, 2850 .cpu_enable = cpu_enable_fa64, 2851 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2852 }, 2853 { 2854 .desc = "SME2", 2855 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2856 .capability = ARM64_SME2, 2857 .matches = has_cpuid_feature, 2858 .cpu_enable = cpu_enable_sme2, 2859 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2860 }, 2861 #endif /* CONFIG_ARM64_SME */ 2862 { 2863 .desc = "WFx with timeout", 2864 .capability = ARM64_HAS_WFXT, 2865 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2866 .matches = has_cpuid_feature, 2867 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2868 }, 2869 { 2870 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2871 .capability = ARM64_HAS_TIDCP1, 2872 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2873 .matches = has_cpuid_feature, 2874 .cpu_enable = cpu_trap_el0_impdef, 2875 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2876 }, 2877 { 2878 .desc = "Data independent timing control (DIT)", 2879 .capability = ARM64_HAS_DIT, 2880 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2881 .matches = has_cpuid_feature, 2882 .cpu_enable = cpu_enable_dit, 2883 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2884 }, 2885 { 2886 .desc = "Memory Copy and Memory Set instructions", 2887 .capability = ARM64_HAS_MOPS, 2888 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2889 .matches = has_cpuid_feature, 2890 .cpu_enable = cpu_enable_mops, 2891 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2892 }, 2893 { 2894 .capability = ARM64_HAS_TCR2, 2895 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2896 .matches = has_cpuid_feature, 2897 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2898 }, 2899 { 2900 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2901 .capability = ARM64_HAS_S1PIE, 2902 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2903 .matches = has_cpuid_feature, 2904 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2905 }, 2906 { 2907 .desc = "VHE for hypervisor only", 2908 .capability = ARM64_KVM_HVHE, 2909 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2910 .matches = hvhe_possible, 2911 }, 2912 { 2913 .desc = "Enhanced Virtualization Traps", 2914 .capability = ARM64_HAS_EVT, 2915 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2916 .matches = has_cpuid_feature, 2917 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2918 }, 2919 { 2920 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2921 .capability = ARM64_HAS_LPA2, 2922 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2923 .matches = has_lpa2, 2924 }, 2925 { 2926 .desc = "FPMR", 2927 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2928 .capability = ARM64_HAS_FPMR, 2929 .matches = has_cpuid_feature, 2930 .cpu_enable = cpu_enable_fpmr, 2931 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2932 }, 2933 #ifdef CONFIG_ARM64_VA_BITS_52 2934 { 2935 .capability = ARM64_HAS_VA52, 2936 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2937 .matches = has_cpuid_feature, 2938 #ifdef CONFIG_ARM64_64K_PAGES 2939 .desc = "52-bit Virtual Addressing (LVA)", 2940 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2941 #else 2942 .desc = "52-bit Virtual Addressing (LPA2)", 2943 #ifdef CONFIG_ARM64_4K_PAGES 2944 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2945 #else 2946 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2947 #endif 2948 #endif 2949 }, 2950 #endif 2951 { 2952 .desc = "Memory Partitioning And Monitoring", 2953 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2954 .capability = ARM64_MPAM, 2955 .matches = test_has_mpam, 2956 .cpu_enable = cpu_enable_mpam, 2957 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 2958 }, 2959 { 2960 .desc = "Memory Partitioning And Monitoring Virtualisation", 2961 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2962 .capability = ARM64_MPAM_HCR, 2963 .matches = test_has_mpam_hcr, 2964 }, 2965 { 2966 .desc = "NV1", 2967 .capability = ARM64_HAS_HCR_NV1, 2968 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2969 .matches = has_nv1, 2970 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 2971 }, 2972 #ifdef CONFIG_ARM64_POE 2973 { 2974 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 2975 .capability = ARM64_HAS_S1POE, 2976 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2977 .matches = has_cpuid_feature, 2978 .cpu_enable = cpu_enable_poe, 2979 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 2980 }, 2981 #endif 2982 #ifdef CONFIG_ARM64_GCS 2983 { 2984 .desc = "Guarded Control Stack (GCS)", 2985 .capability = ARM64_HAS_GCS, 2986 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2987 .cpu_enable = cpu_enable_gcs, 2988 .matches = has_cpuid_feature, 2989 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 2990 }, 2991 #endif 2992 {}, 2993 }; 2994 2995 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2996 .matches = has_user_cpuid_feature, \ 2997 ARM64_CPUID_FIELDS(reg, field, min_value) 2998 2999 #define __HWCAP_CAP(name, cap_type, cap) \ 3000 .desc = name, \ 3001 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3002 .hwcap_type = cap_type, \ 3003 .hwcap = cap, \ 3004 3005 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3006 { \ 3007 __HWCAP_CAP(#cap, cap_type, cap) \ 3008 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3009 } 3010 3011 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3012 { \ 3013 __HWCAP_CAP(#cap, cap_type, cap) \ 3014 .matches = cpucap_multi_entry_cap_matches, \ 3015 .match_list = list, \ 3016 } 3017 3018 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3019 { \ 3020 __HWCAP_CAP(#cap, cap_type, cap) \ 3021 .matches = match, \ 3022 } 3023 3024 #ifdef CONFIG_ARM64_PTR_AUTH 3025 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3026 { 3027 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3028 }, 3029 { 3030 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3031 }, 3032 { 3033 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3034 }, 3035 {}, 3036 }; 3037 3038 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3039 { 3040 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3041 }, 3042 { 3043 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3044 }, 3045 { 3046 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3047 }, 3048 {}, 3049 }; 3050 #endif 3051 3052 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3053 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3054 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3055 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3056 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3057 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3058 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3059 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3060 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3061 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3062 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3063 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3064 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3065 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3066 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3067 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3068 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3069 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3070 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3071 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3072 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3073 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3074 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3075 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3076 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3077 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3078 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3079 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3080 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3081 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3082 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3083 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3084 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3085 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3086 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3087 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3088 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3089 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3090 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3091 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3092 #ifdef CONFIG_ARM64_SVE 3093 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3094 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3095 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3096 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3097 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3098 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3099 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3100 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3101 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3102 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3103 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3104 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3105 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3106 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3107 #endif 3108 #ifdef CONFIG_ARM64_GCS 3109 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3110 #endif 3111 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3112 #ifdef CONFIG_ARM64_BTI 3113 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3114 #endif 3115 #ifdef CONFIG_ARM64_PTR_AUTH 3116 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3117 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3118 #endif 3119 #ifdef CONFIG_ARM64_MTE 3120 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3121 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3122 #endif /* CONFIG_ARM64_MTE */ 3123 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3124 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3125 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3126 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3127 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3128 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3129 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3130 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3131 #ifdef CONFIG_ARM64_SME 3132 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3133 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3134 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3135 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3136 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3137 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3138 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3139 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3140 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3141 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3142 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3143 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3144 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3145 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3146 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3147 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3148 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3149 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3150 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3151 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3152 #endif /* CONFIG_ARM64_SME */ 3153 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3154 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3155 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3156 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3157 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3158 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3159 #ifdef CONFIG_ARM64_POE 3160 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3161 #endif 3162 {}, 3163 }; 3164 3165 #ifdef CONFIG_COMPAT 3166 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3167 { 3168 /* 3169 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3170 * in line with that of arm32 as in vfp_init(). We make sure that the 3171 * check is future proof, by making sure value is non-zero. 3172 */ 3173 u32 mvfr1; 3174 3175 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3176 if (scope == SCOPE_SYSTEM) 3177 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3178 else 3179 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3180 3181 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3182 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3183 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3184 } 3185 #endif 3186 3187 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3188 #ifdef CONFIG_COMPAT 3189 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3190 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3191 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3192 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3193 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3194 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3195 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3196 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3197 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3198 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3199 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3200 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3201 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3202 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3203 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3204 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3205 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3206 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3207 #endif 3208 {}, 3209 }; 3210 3211 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3212 { 3213 switch (cap->hwcap_type) { 3214 case CAP_HWCAP: 3215 cpu_set_feature(cap->hwcap); 3216 break; 3217 #ifdef CONFIG_COMPAT 3218 case CAP_COMPAT_HWCAP: 3219 compat_elf_hwcap |= (u32)cap->hwcap; 3220 break; 3221 case CAP_COMPAT_HWCAP2: 3222 compat_elf_hwcap2 |= (u32)cap->hwcap; 3223 break; 3224 #endif 3225 default: 3226 WARN_ON(1); 3227 break; 3228 } 3229 } 3230 3231 /* Check if we have a particular HWCAP enabled */ 3232 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3233 { 3234 bool rc; 3235 3236 switch (cap->hwcap_type) { 3237 case CAP_HWCAP: 3238 rc = cpu_have_feature(cap->hwcap); 3239 break; 3240 #ifdef CONFIG_COMPAT 3241 case CAP_COMPAT_HWCAP: 3242 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3243 break; 3244 case CAP_COMPAT_HWCAP2: 3245 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3246 break; 3247 #endif 3248 default: 3249 WARN_ON(1); 3250 rc = false; 3251 } 3252 3253 return rc; 3254 } 3255 3256 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3257 { 3258 /* We support emulation of accesses to CPU ID feature registers */ 3259 cpu_set_named_feature(CPUID); 3260 for (; hwcaps->matches; hwcaps++) 3261 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3262 cap_set_elf_hwcap(hwcaps); 3263 } 3264 3265 static void update_cpu_capabilities(u16 scope_mask) 3266 { 3267 int i; 3268 const struct arm64_cpu_capabilities *caps; 3269 3270 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3271 for (i = 0; i < ARM64_NCAPS; i++) { 3272 caps = cpucap_ptrs[i]; 3273 if (!caps || !(caps->type & scope_mask) || 3274 cpus_have_cap(caps->capability) || 3275 !caps->matches(caps, cpucap_default_scope(caps))) 3276 continue; 3277 3278 if (caps->desc && !caps->cpus) 3279 pr_info("detected: %s\n", caps->desc); 3280 3281 __set_bit(caps->capability, system_cpucaps); 3282 3283 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3284 set_bit(caps->capability, boot_cpucaps); 3285 } 3286 } 3287 3288 /* 3289 * Enable all the available capabilities on this CPU. The capabilities 3290 * with BOOT_CPU scope are handled separately and hence skipped here. 3291 */ 3292 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3293 { 3294 int i; 3295 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3296 3297 for_each_available_cap(i) { 3298 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3299 3300 if (WARN_ON(!cap)) 3301 continue; 3302 3303 if (!(cap->type & non_boot_scope)) 3304 continue; 3305 3306 if (cap->cpu_enable) 3307 cap->cpu_enable(cap); 3308 } 3309 return 0; 3310 } 3311 3312 /* 3313 * Run through the enabled capabilities and enable() it on all active 3314 * CPUs 3315 */ 3316 static void __init enable_cpu_capabilities(u16 scope_mask) 3317 { 3318 int i; 3319 const struct arm64_cpu_capabilities *caps; 3320 bool boot_scope; 3321 3322 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3323 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3324 3325 for (i = 0; i < ARM64_NCAPS; i++) { 3326 caps = cpucap_ptrs[i]; 3327 if (!caps || !(caps->type & scope_mask) || 3328 !cpus_have_cap(caps->capability)) 3329 continue; 3330 3331 if (boot_scope && caps->cpu_enable) 3332 /* 3333 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3334 * before any secondary CPU boots. Thus, each secondary 3335 * will enable the capability as appropriate via 3336 * check_local_cpu_capabilities(). The only exception is 3337 * the boot CPU, for which the capability must be 3338 * enabled here. This approach avoids costly 3339 * stop_machine() calls for this case. 3340 */ 3341 caps->cpu_enable(caps); 3342 } 3343 3344 /* 3345 * For all non-boot scope capabilities, use stop_machine() 3346 * as it schedules the work allowing us to modify PSTATE, 3347 * instead of on_each_cpu() which uses an IPI, giving us a 3348 * PSTATE that disappears when we return. 3349 */ 3350 if (!boot_scope) 3351 stop_machine(cpu_enable_non_boot_scope_capabilities, 3352 NULL, cpu_online_mask); 3353 } 3354 3355 /* 3356 * Run through the list of capabilities to check for conflicts. 3357 * If the system has already detected a capability, take necessary 3358 * action on this CPU. 3359 */ 3360 static void verify_local_cpu_caps(u16 scope_mask) 3361 { 3362 int i; 3363 bool cpu_has_cap, system_has_cap; 3364 const struct arm64_cpu_capabilities *caps; 3365 3366 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3367 3368 for (i = 0; i < ARM64_NCAPS; i++) { 3369 caps = cpucap_ptrs[i]; 3370 if (!caps || !(caps->type & scope_mask)) 3371 continue; 3372 3373 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3374 system_has_cap = cpus_have_cap(caps->capability); 3375 3376 if (system_has_cap) { 3377 /* 3378 * Check if the new CPU misses an advertised feature, 3379 * which is not safe to miss. 3380 */ 3381 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3382 break; 3383 /* 3384 * We have to issue cpu_enable() irrespective of 3385 * whether the CPU has it or not, as it is enabeld 3386 * system wide. It is upto the call back to take 3387 * appropriate action on this CPU. 3388 */ 3389 if (caps->cpu_enable) 3390 caps->cpu_enable(caps); 3391 } else { 3392 /* 3393 * Check if the CPU has this capability if it isn't 3394 * safe to have when the system doesn't. 3395 */ 3396 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3397 break; 3398 } 3399 } 3400 3401 if (i < ARM64_NCAPS) { 3402 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3403 smp_processor_id(), caps->capability, 3404 caps->desc, system_has_cap, cpu_has_cap); 3405 3406 if (cpucap_panic_on_conflict(caps)) 3407 cpu_panic_kernel(); 3408 else 3409 cpu_die_early(); 3410 } 3411 } 3412 3413 /* 3414 * Check for CPU features that are used in early boot 3415 * based on the Boot CPU value. 3416 */ 3417 static void check_early_cpu_features(void) 3418 { 3419 verify_cpu_asid_bits(); 3420 3421 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3422 } 3423 3424 static void 3425 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3426 { 3427 3428 for (; caps->matches; caps++) 3429 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3430 pr_crit("CPU%d: missing HWCAP: %s\n", 3431 smp_processor_id(), caps->desc); 3432 cpu_die_early(); 3433 } 3434 } 3435 3436 static void verify_local_elf_hwcaps(void) 3437 { 3438 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3439 3440 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3441 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3442 } 3443 3444 static void verify_sve_features(void) 3445 { 3446 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3447 3448 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3449 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3450 smp_processor_id()); 3451 cpu_die_early(); 3452 } 3453 3454 cpacr_restore(cpacr); 3455 } 3456 3457 static void verify_sme_features(void) 3458 { 3459 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3460 3461 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3462 pr_crit("CPU%d: SME: vector length support mismatch\n", 3463 smp_processor_id()); 3464 cpu_die_early(); 3465 } 3466 3467 cpacr_restore(cpacr); 3468 } 3469 3470 static void verify_hyp_capabilities(void) 3471 { 3472 u64 safe_mmfr1, mmfr0, mmfr1; 3473 int parange, ipa_max; 3474 unsigned int safe_vmid_bits, vmid_bits; 3475 3476 if (!IS_ENABLED(CONFIG_KVM)) 3477 return; 3478 3479 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3480 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3481 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3482 3483 /* Verify VMID bits */ 3484 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3485 vmid_bits = get_vmid_bits(mmfr1); 3486 if (vmid_bits < safe_vmid_bits) { 3487 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3488 cpu_die_early(); 3489 } 3490 3491 /* Verify IPA range */ 3492 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3493 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3494 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3495 if (ipa_max < get_kvm_ipa_limit()) { 3496 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3497 cpu_die_early(); 3498 } 3499 } 3500 3501 static void verify_mpam_capabilities(void) 3502 { 3503 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3504 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3505 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3506 3507 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3508 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3509 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3510 cpu_die_early(); 3511 } 3512 3513 cpu_idr = read_cpuid(MPAMIDR_EL1); 3514 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3515 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3516 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3517 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3518 cpu_die_early(); 3519 } 3520 3521 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3522 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3523 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3524 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3525 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3526 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3527 cpu_die_early(); 3528 } 3529 } 3530 3531 /* 3532 * Run through the enabled system capabilities and enable() it on this CPU. 3533 * The capabilities were decided based on the available CPUs at the boot time. 3534 * Any new CPU should match the system wide status of the capability. If the 3535 * new CPU doesn't have a capability which the system now has enabled, we 3536 * cannot do anything to fix it up and could cause unexpected failures. So 3537 * we park the CPU. 3538 */ 3539 static void verify_local_cpu_capabilities(void) 3540 { 3541 /* 3542 * The capabilities with SCOPE_BOOT_CPU are checked from 3543 * check_early_cpu_features(), as they need to be verified 3544 * on all secondary CPUs. 3545 */ 3546 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3547 verify_local_elf_hwcaps(); 3548 3549 if (system_supports_sve()) 3550 verify_sve_features(); 3551 3552 if (system_supports_sme()) 3553 verify_sme_features(); 3554 3555 if (is_hyp_mode_available()) 3556 verify_hyp_capabilities(); 3557 3558 if (system_supports_mpam()) 3559 verify_mpam_capabilities(); 3560 } 3561 3562 void check_local_cpu_capabilities(void) 3563 { 3564 /* 3565 * All secondary CPUs should conform to the early CPU features 3566 * in use by the kernel based on boot CPU. 3567 */ 3568 check_early_cpu_features(); 3569 3570 /* 3571 * If we haven't finalised the system capabilities, this CPU gets 3572 * a chance to update the errata work arounds and local features. 3573 * Otherwise, this CPU should verify that it has all the system 3574 * advertised capabilities. 3575 */ 3576 if (!system_capabilities_finalized()) 3577 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3578 else 3579 verify_local_cpu_capabilities(); 3580 } 3581 3582 bool this_cpu_has_cap(unsigned int n) 3583 { 3584 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3585 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3586 3587 if (cap) 3588 return cap->matches(cap, SCOPE_LOCAL_CPU); 3589 } 3590 3591 return false; 3592 } 3593 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3594 3595 /* 3596 * This helper function is used in a narrow window when, 3597 * - The system wide safe registers are set with all the SMP CPUs and, 3598 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3599 */ 3600 static bool __maybe_unused __system_matches_cap(unsigned int n) 3601 { 3602 if (n < ARM64_NCAPS) { 3603 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3604 3605 if (cap) 3606 return cap->matches(cap, SCOPE_SYSTEM); 3607 } 3608 return false; 3609 } 3610 3611 void cpu_set_feature(unsigned int num) 3612 { 3613 set_bit(num, elf_hwcap); 3614 } 3615 3616 bool cpu_have_feature(unsigned int num) 3617 { 3618 return test_bit(num, elf_hwcap); 3619 } 3620 EXPORT_SYMBOL_GPL(cpu_have_feature); 3621 3622 unsigned long cpu_get_elf_hwcap(void) 3623 { 3624 /* 3625 * We currently only populate the first 32 bits of AT_HWCAP. Please 3626 * note that for userspace compatibility we guarantee that bits 62 3627 * and 63 will always be returned as 0. 3628 */ 3629 return elf_hwcap[0]; 3630 } 3631 3632 unsigned long cpu_get_elf_hwcap2(void) 3633 { 3634 return elf_hwcap[1]; 3635 } 3636 3637 unsigned long cpu_get_elf_hwcap3(void) 3638 { 3639 return elf_hwcap[2]; 3640 } 3641 3642 static void __init setup_boot_cpu_capabilities(void) 3643 { 3644 /* 3645 * The boot CPU's feature register values have been recorded. Detect 3646 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3647 * patch alternatives for the available boot cpucaps. 3648 */ 3649 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3650 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3651 apply_boot_alternatives(); 3652 } 3653 3654 void __init setup_boot_cpu_features(void) 3655 { 3656 /* 3657 * Initialize the indirect array of CPU capabilities pointers before we 3658 * handle the boot CPU. 3659 */ 3660 init_cpucap_indirect_list(); 3661 3662 /* 3663 * Detect broken pseudo-NMI. Must be called _before_ the call to 3664 * setup_boot_cpu_capabilities() since it interacts with 3665 * can_use_gic_priorities(). 3666 */ 3667 detect_system_supports_pseudo_nmi(); 3668 3669 setup_boot_cpu_capabilities(); 3670 } 3671 3672 static void __init setup_system_capabilities(void) 3673 { 3674 /* 3675 * The system-wide safe feature register values have been finalized. 3676 * Detect, enable, and patch alternatives for the available system 3677 * cpucaps. 3678 */ 3679 update_cpu_capabilities(SCOPE_SYSTEM); 3680 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3681 apply_alternatives_all(); 3682 3683 /* 3684 * Log any cpucaps with a cpumask as these aren't logged by 3685 * update_cpu_capabilities(). 3686 */ 3687 for (int i = 0; i < ARM64_NCAPS; i++) { 3688 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3689 3690 if (caps && caps->cpus && caps->desc && 3691 cpumask_any(caps->cpus) < nr_cpu_ids) 3692 pr_info("detected: %s on CPU%*pbl\n", 3693 caps->desc, cpumask_pr_args(caps->cpus)); 3694 } 3695 3696 /* 3697 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3698 */ 3699 if (system_uses_ttbr0_pan()) 3700 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3701 } 3702 3703 void __init setup_system_features(void) 3704 { 3705 setup_system_capabilities(); 3706 3707 kpti_install_ng_mappings(); 3708 3709 sve_setup(); 3710 sme_setup(); 3711 3712 /* 3713 * Check for sane CTR_EL0.CWG value. 3714 */ 3715 if (!cache_type_cwg()) 3716 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3717 ARCH_DMA_MINALIGN); 3718 } 3719 3720 void __init setup_user_features(void) 3721 { 3722 user_feature_fixup(); 3723 3724 setup_elf_hwcaps(arm64_elf_hwcaps); 3725 3726 if (system_supports_32bit_el0()) { 3727 setup_elf_hwcaps(compat_elf_hwcaps); 3728 elf_hwcap_fixup(); 3729 } 3730 3731 minsigstksz_setup(); 3732 } 3733 3734 static int enable_mismatched_32bit_el0(unsigned int cpu) 3735 { 3736 /* 3737 * The first 32-bit-capable CPU we detected and so can no longer 3738 * be offlined by userspace. -1 indicates we haven't yet onlined 3739 * a 32-bit-capable CPU. 3740 */ 3741 static int lucky_winner = -1; 3742 3743 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3744 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3745 3746 if (cpu_32bit) { 3747 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3748 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3749 } 3750 3751 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3752 return 0; 3753 3754 if (lucky_winner >= 0) 3755 return 0; 3756 3757 /* 3758 * We've detected a mismatch. We need to keep one of our CPUs with 3759 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3760 * every CPU in the system for a 32-bit task. 3761 */ 3762 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3763 cpu_active_mask); 3764 get_cpu_device(lucky_winner)->offline_disabled = true; 3765 setup_elf_hwcaps(compat_elf_hwcaps); 3766 elf_hwcap_fixup(); 3767 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3768 cpu, lucky_winner); 3769 return 0; 3770 } 3771 3772 static int __init init_32bit_el0_mask(void) 3773 { 3774 if (!allow_mismatched_32bit_el0) 3775 return 0; 3776 3777 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3778 return -ENOMEM; 3779 3780 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3781 "arm64/mismatched_32bit_el0:online", 3782 enable_mismatched_32bit_el0, NULL); 3783 } 3784 subsys_initcall_sync(init_32bit_el0_mask); 3785 3786 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3787 { 3788 cpu_enable_swapper_cnp(); 3789 } 3790 3791 /* 3792 * We emulate only the following system register space. 3793 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3794 * See Table C5-6 System instruction encodings for System register accesses, 3795 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3796 */ 3797 static inline bool __attribute_const__ is_emulated(u32 id) 3798 { 3799 return (sys_reg_Op0(id) == 0x3 && 3800 sys_reg_CRn(id) == 0x0 && 3801 sys_reg_Op1(id) == 0x0 && 3802 (sys_reg_CRm(id) == 0 || 3803 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3804 } 3805 3806 /* 3807 * With CRm == 0, reg should be one of : 3808 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3809 */ 3810 static inline int emulate_id_reg(u32 id, u64 *valp) 3811 { 3812 switch (id) { 3813 case SYS_MIDR_EL1: 3814 *valp = read_cpuid_id(); 3815 break; 3816 case SYS_MPIDR_EL1: 3817 *valp = SYS_MPIDR_SAFE_VAL; 3818 break; 3819 case SYS_REVIDR_EL1: 3820 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3821 *valp = 0; 3822 break; 3823 default: 3824 return -EINVAL; 3825 } 3826 3827 return 0; 3828 } 3829 3830 static int emulate_sys_reg(u32 id, u64 *valp) 3831 { 3832 struct arm64_ftr_reg *regp; 3833 3834 if (!is_emulated(id)) 3835 return -EINVAL; 3836 3837 if (sys_reg_CRm(id) == 0) 3838 return emulate_id_reg(id, valp); 3839 3840 regp = get_arm64_ftr_reg_nowarn(id); 3841 if (regp) 3842 *valp = arm64_ftr_reg_user_value(regp); 3843 else 3844 /* 3845 * The untracked registers are either IMPLEMENTATION DEFINED 3846 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3847 */ 3848 *valp = 0; 3849 return 0; 3850 } 3851 3852 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3853 { 3854 int rc; 3855 u64 val; 3856 3857 rc = emulate_sys_reg(sys_reg, &val); 3858 if (!rc) { 3859 pt_regs_write_reg(regs, rt, val); 3860 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3861 } 3862 return rc; 3863 } 3864 3865 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3866 { 3867 u32 sys_reg, rt; 3868 3869 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3870 return false; 3871 3872 /* 3873 * sys_reg values are defined as used in mrs/msr instruction. 3874 * shift the imm value to get the encoding. 3875 */ 3876 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3877 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3878 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3879 } 3880 3881 enum mitigation_state arm64_get_meltdown_state(void) 3882 { 3883 if (__meltdown_safe) 3884 return SPECTRE_UNAFFECTED; 3885 3886 if (arm64_kernel_unmapped_at_el0()) 3887 return SPECTRE_MITIGATED; 3888 3889 return SPECTRE_VULNERABLE; 3890 } 3891 3892 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3893 char *buf) 3894 { 3895 switch (arm64_get_meltdown_state()) { 3896 case SPECTRE_UNAFFECTED: 3897 return sprintf(buf, "Not affected\n"); 3898 3899 case SPECTRE_MITIGATED: 3900 return sprintf(buf, "Mitigation: PTI\n"); 3901 3902 default: 3903 return sprintf(buf, "Vulnerable\n"); 3904 } 3905 } 3906