r9a07g043u.dtsi (48ab6eddd8bbcf7e9c8ae27bf42d0b52a777aaba) r9a07g043u.dtsi (85169df721078bf90fb0fc3bf15e4743fea45b2d)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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44 compatible = "arm,armv8-timer";
45 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
46 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
47 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
48 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
49 };
50};
51
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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44 compatible = "arm,armv8-timer";
45 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
46 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
47 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
48 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
49 };
50};
51
52&pinctrl {
53 interrupt-parent = <&irqc>;
54};
55
52&soc {
53 interrupt-parent = <&gic>;
54
55 irqc: interrupt-controller@110a0000 {
56 compatible = "renesas,r9a07g043u-irqc",
57 "renesas,rzg2l-irqc";
58 reg = <0 0x110a0000 0 0x10000>;
59 #interrupt-cells = <2>;

--- 82 unchanged lines hidden --- 		56&soc {
57 interrupt-parent = <&gic>;
58
59 irqc: interrupt-controller@110a0000 {
60 compatible = "renesas,r9a07g043u-irqc",
61 "renesas,rzg2l-irqc";
62 reg = <0 0x110a0000 0 0x10000>;
63 #interrupt-cells = <2>;

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