r9a07g043.dtsi (cecdd52a3dd312564f81a39df08378b7b39a2654) r9a07g043.dtsi (05d11e2f4460752fa5f7ce7657e1b040056c1736)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>

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75 ranges;
76
77 ssi0: ssi@10049c00 {
78 compatible = "renesas,r9a07g043-ssi",
79 "renesas,rz-ssi";
80 reg = <0 0x10049c00 0 0x400>;
81 interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
82 <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>

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75 ranges;
76
77 ssi0: ssi@10049c00 {
78 compatible = "renesas,r9a07g043-ssi",
79 "renesas,rz-ssi";
80 reg = <0 0x10049c00 0 0x400>;
81 interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
82 <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
83 <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
84 <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
85 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
83 <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>;
84 interrupt-names = "int_req", "dma_rx", "dma_tx";
86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
88 <&audio_clk1>, <&audio_clk2>;
89 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
91 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
92 dma-names = "tx", "rx";
93 power-domains = <&cpg>;
94 #sound-dai-cells = <0>;
95 status = "disabled";
96 };
97
98 ssi1: ssi@1004a000 {
99 compatible = "renesas,r9a07g043-ssi",
100 "renesas,rz-ssi";
101 reg = <0 0x1004a000 0 0x400>;
102 interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
103 <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
85 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
86 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
87 <&audio_clk1>, <&audio_clk2>;
88 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
89 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
90 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
91 dma-names = "tx", "rx";
92 power-domains = <&cpg>;
93 #sound-dai-cells = <0>;
94 status = "disabled";
95 };
96
97 ssi1: ssi@1004a000 {
98 compatible = "renesas,r9a07g043-ssi",
99 "renesas,rz-ssi";
100 reg = <0 0x1004a000 0 0x400>;
101 interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
102 <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
104 <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
105 <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
103 <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>;
104 interrupt-names = "int_req", "dma_rx", "dma_tx";
107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
109 <&audio_clk1>, <&audio_clk2>;
110 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
112 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
113 dma-names = "tx", "rx";
114 power-domains = <&cpg>;
115 #sound-dai-cells = <0>;
116 status = "disabled";
117 };
118
119 ssi2: ssi@1004a400 {
120 compatible = "renesas,r9a07g043-ssi",
121 "renesas,rz-ssi";
122 reg = <0 0x1004a400 0 0x400>;
123 interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
105 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
106 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
107 <&audio_clk1>, <&audio_clk2>;
108 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
109 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
110 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
111 dma-names = "tx", "rx";
112 power-domains = <&cpg>;
113 #sound-dai-cells = <0>;
114 status = "disabled";
115 };
116
117 ssi2: ssi@1004a400 {
118 compatible = "renesas,r9a07g043-ssi",
119 "renesas,rz-ssi";
120 reg = <0 0x1004a400 0 0x400>;
121 interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
124 <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
125 <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
126 <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
122 <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
127 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
123 interrupt-names = "int_req", "dma_rt";
128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
130 <&audio_clk1>, <&audio_clk2>;
131 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
133 dmas = <&dmac 0x265f>;
134 dma-names = "rt";
135 power-domains = <&cpg>;
136 #sound-dai-cells = <0>;
137 status = "disabled";
138 };
139
140 ssi3: ssi@1004a800 {
141 compatible = "renesas,r9a07g043-ssi",
142 "renesas,rz-ssi";
143 reg = <0 0x1004a800 0 0x400>;
144 interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
145 <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
124 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
125 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
126 <&audio_clk1>, <&audio_clk2>;
127 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
128 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
129 dmas = <&dmac 0x265f>;
130 dma-names = "rt";
131 power-domains = <&cpg>;
132 #sound-dai-cells = <0>;
133 status = "disabled";
134 };
135
136 ssi3: ssi@1004a800 {
137 compatible = "renesas,r9a07g043-ssi",
138 "renesas,rz-ssi";
139 reg = <0 0x1004a800 0 0x400>;
140 interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
141 <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
146 <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
147 <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
148 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
142 <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>;
143 interrupt-names = "int_req", "dma_rx", "dma_tx";
149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
151 <&audio_clk1>, <&audio_clk2>;
152 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
154 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
155 dma-names = "tx", "rx";
156 power-domains = <&cpg>;

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564 <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
565 interrupt-names = "error",
566 "ch0", "ch1", "ch2", "ch3",
567 "ch4", "ch5", "ch6", "ch7",
568 "ch8", "ch9", "ch10", "ch11",
569 "ch12", "ch13", "ch14", "ch15";
570 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
571 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
144 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
145 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
146 <&audio_clk1>, <&audio_clk2>;
147 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
148 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
149 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
150 dma-names = "tx", "rx";
151 power-domains = <&cpg>;

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559 <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
560 interrupt-names = "error",
561 "ch0", "ch1", "ch2", "ch3",
562 "ch4", "ch5", "ch6", "ch7",
563 "ch8", "ch9", "ch10", "ch11",
564 "ch12", "ch13", "ch14", "ch15";
565 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
566 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
567 clock-names = "main", "register";
572 power-domains = <&cpg>;
573 resets = <&cpg R9A07G043_DMAC_ARESETN>,
574 <&cpg R9A07G043_DMAC_RST_ASYNC>;
568 power-domains = <&cpg>;
569 resets = <&cpg R9A07G043_DMAC_ARESETN>,
570 <&cpg R9A07G043_DMAC_RST_ASYNC>;
571 reset-names = "arst", "rst_async";
575 #dma-cells = <1>;
576 dma-channels = <16>;
577 };
578
579 sdhi0: mmc@11c00000 {
580 compatible = "renesas,sdhi-r9a07g043",
581 "renesas,rcar-gen3-sdhi";
582 reg = <0x0 0x11c00000 0 0x10000>;

--- 262 unchanged lines hidden --- 		572 #dma-cells = <1>;
573 dma-channels = <16>;
574 };
575
576 sdhi0: mmc@11c00000 {
577 compatible = "renesas,sdhi-r9a07g043",
578 "renesas,rcar-gen3-sdhi";
579 reg = <0x0 0x11c00000 0 0x10000>;

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