1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r9a07g043-cpg.h> 9 10/ { 11 compatible = "renesas,r9a07g043"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 audio_clk1: audio1-clk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 /* This value must be overridden by boards that provide it */ 19 clock-frequency = <0>; 20 }; 21 22 audio_clk2: audio2-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 /* This value must be overridden by boards that provide it */ 26 clock-frequency = <0>; 27 }; 28 29 /* External CAN clock - to be overridden by boards that provide it */ 30 can_clk: can-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 37 extal_clk: extal-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 /* This value must be overridden by the board */ 41 clock-frequency = <0>; 42 }; 43 44 cluster0_opp: opp-table-0 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-125000000 { 49 opp-hz = /bits/ 64 <125000000>; 50 opp-microvolt = <1100000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-250000000 { 54 opp-hz = /bits/ 64 <250000000>; 55 opp-microvolt = <1100000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-500000000 { 59 opp-hz = /bits/ 64 <500000000>; 60 opp-microvolt = <1100000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1000000000 { 64 opp-hz = /bits/ 64 <1000000000>; 65 opp-microvolt = <1100000>; 66 clock-latency-ns = <300000>; 67 opp-suspend; 68 }; 69 }; 70 71 soc: soc { 72 compatible = "simple-bus"; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 ssi0: ssi@10049c00 { 78 compatible = "renesas,r9a07g043-ssi", 79 "renesas,rz-ssi"; 80 reg = <0 0x10049c00 0 0x400>; 81 interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>, 82 <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>, 83 <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>, 84 <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>; 85 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 88 <&audio_clk1>, <&audio_clk2>; 89 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 91 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 92 dma-names = "tx", "rx"; 93 power-domains = <&cpg>; 94 #sound-dai-cells = <0>; 95 status = "disabled"; 96 }; 97 98 ssi1: ssi@1004a000 { 99 compatible = "renesas,r9a07g043-ssi", 100 "renesas,rz-ssi"; 101 reg = <0 0x1004a000 0 0x400>; 102 interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>, 103 <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>, 104 <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>, 105 <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>; 106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 109 <&audio_clk1>, <&audio_clk2>; 110 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 112 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 113 dma-names = "tx", "rx"; 114 power-domains = <&cpg>; 115 #sound-dai-cells = <0>; 116 status = "disabled"; 117 }; 118 119 ssi2: ssi@1004a400 { 120 compatible = "renesas,r9a07g043-ssi", 121 "renesas,rz-ssi"; 122 reg = <0 0x1004a400 0 0x400>; 123 interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>, 124 <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>, 125 <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>, 126 <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>; 127 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 130 <&audio_clk1>, <&audio_clk2>; 131 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 133 dmas = <&dmac 0x265f>; 134 dma-names = "rt"; 135 power-domains = <&cpg>; 136 #sound-dai-cells = <0>; 137 status = "disabled"; 138 }; 139 140 ssi3: ssi@1004a800 { 141 compatible = "renesas,r9a07g043-ssi", 142 "renesas,rz-ssi"; 143 reg = <0 0x1004a800 0 0x400>; 144 interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>, 145 <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>, 146 <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>, 147 <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>; 148 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 151 <&audio_clk1>, <&audio_clk2>; 152 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 154 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 155 dma-names = "tx", "rx"; 156 power-domains = <&cpg>; 157 #sound-dai-cells = <0>; 158 status = "disabled"; 159 }; 160 161 spi0: spi@1004ac00 { 162 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 163 reg = <0 0x1004ac00 0 0x400>; 164 interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>, 165 <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>, 166 <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-names = "error", "rx", "tx"; 168 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 169 resets = <&cpg R9A07G043_RSPI0_RST>; 170 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 171 dma-names = "tx", "rx"; 172 power-domains = <&cpg>; 173 num-cs = <1>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 status = "disabled"; 177 }; 178 179 spi1: spi@1004b000 { 180 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 181 reg = <0 0x1004b000 0 0x400>; 182 interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>, 183 <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>, 184 <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "error", "rx", "tx"; 186 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 187 resets = <&cpg R9A07G043_RSPI1_RST>; 188 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 189 dma-names = "tx", "rx"; 190 power-domains = <&cpg>; 191 num-cs = <1>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 status = "disabled"; 195 }; 196 197 spi2: spi@1004b400 { 198 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 199 reg = <0 0x1004b400 0 0x400>; 200 interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>, 201 <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>, 202 <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>; 203 interrupt-names = "error", "rx", "tx"; 204 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 205 resets = <&cpg R9A07G043_RSPI2_RST>; 206 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 207 dma-names = "tx", "rx"; 208 power-domains = <&cpg>; 209 num-cs = <1>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 status = "disabled"; 213 }; 214 215 scif0: serial@1004b800 { 216 compatible = "renesas,scif-r9a07g043", 217 "renesas,scif-r9a07g044"; 218 reg = <0 0x1004b800 0 0x400>; 219 interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>, 220 <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>, 221 <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>, 222 <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>, 223 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>, 224 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>; 225 interrupt-names = "eri", "rxi", "txi", 226 "bri", "dri", "tei"; 227 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 228 clock-names = "fck"; 229 power-domains = <&cpg>; 230 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 231 status = "disabled"; 232 }; 233 234 scif1: serial@1004bc00 { 235 compatible = "renesas,scif-r9a07g043", 236 "renesas,scif-r9a07g044"; 237 reg = <0 0x1004bc00 0 0x400>; 238 interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>, 239 <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>, 240 <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>, 241 <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>, 242 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>, 243 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>; 244 interrupt-names = "eri", "rxi", "txi", 245 "bri", "dri", "tei"; 246 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 247 clock-names = "fck"; 248 power-domains = <&cpg>; 249 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 250 status = "disabled"; 251 }; 252 253 scif2: serial@1004c000 { 254 compatible = "renesas,scif-r9a07g043", 255 "renesas,scif-r9a07g044"; 256 reg = <0 0x1004c000 0 0x400>; 257 interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>, 258 <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>, 259 <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>, 260 <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>, 261 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>, 262 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>; 263 interrupt-names = "eri", "rxi", "txi", 264 "bri", "dri", "tei"; 265 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 266 clock-names = "fck"; 267 power-domains = <&cpg>; 268 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 269 status = "disabled"; 270 }; 271 272 scif3: serial@1004c400 { 273 compatible = "renesas,scif-r9a07g043", 274 "renesas,scif-r9a07g044"; 275 reg = <0 0x1004c400 0 0x400>; 276 interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>, 277 <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>, 278 <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>, 279 <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>, 280 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>, 281 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-names = "eri", "rxi", "txi", 283 "bri", "dri", "tei"; 284 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 285 clock-names = "fck"; 286 power-domains = <&cpg>; 287 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 288 status = "disabled"; 289 }; 290 291 scif4: serial@1004c800 { 292 compatible = "renesas,scif-r9a07g043", 293 "renesas,scif-r9a07g044"; 294 reg = <0 0x1004c800 0 0x400>; 295 interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>, 296 <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>, 297 <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>, 298 <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>, 299 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>, 300 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-names = "eri", "rxi", "txi", 302 "bri", "dri", "tei"; 303 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 304 clock-names = "fck"; 305 power-domains = <&cpg>; 306 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 307 status = "disabled"; 308 }; 309 310 sci0: serial@1004d000 { 311 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 312 reg = <0 0x1004d000 0 0x400>; 313 interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>, 314 <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>, 315 <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>, 316 <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>; 317 interrupt-names = "eri", "rxi", "txi", "tei"; 318 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 319 clock-names = "fck"; 320 power-domains = <&cpg>; 321 resets = <&cpg R9A07G043_SCI0_RST>; 322 status = "disabled"; 323 }; 324 325 sci1: serial@1004d400 { 326 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 327 reg = <0 0x1004d400 0 0x400>; 328 interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>, 329 <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>, 330 <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>, 331 <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>; 332 interrupt-names = "eri", "rxi", "txi", "tei"; 333 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 334 clock-names = "fck"; 335 power-domains = <&cpg>; 336 resets = <&cpg R9A07G043_SCI1_RST>; 337 status = "disabled"; 338 }; 339 340 canfd: can@10050000 { 341 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 342 reg = <0 0x10050000 0 0x8000>; 343 interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>, 344 <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>, 345 <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>, 346 <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>, 347 <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>, 348 <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>, 349 <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>, 350 <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-names = "g_err", "g_recc", 352 "ch0_err", "ch0_rec", "ch0_trx", 353 "ch1_err", "ch1_rec", "ch1_trx"; 354 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 355 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 356 <&can_clk>; 357 clock-names = "fck", "canfd", "can_clk"; 358 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 359 assigned-clock-rates = <50000000>; 360 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 361 <&cpg R9A07G043_CANFD_RSTC_N>; 362 reset-names = "rstp_n", "rstc_n"; 363 power-domains = <&cpg>; 364 status = "disabled"; 365 366 channel0 { 367 status = "disabled"; 368 }; 369 channel1 { 370 status = "disabled"; 371 }; 372 }; 373 374 i2c0: i2c@10058000 { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 378 reg = <0 0x10058000 0 0x400>; 379 interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>, 380 <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>, 381 <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>, 382 <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>, 383 <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>, 384 <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>, 385 <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>, 386 <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>; 387 interrupt-names = "tei", "ri", "ti", "spi", "sti", 388 "naki", "ali", "tmoi"; 389 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 390 clock-frequency = <100000>; 391 resets = <&cpg R9A07G043_I2C0_MRST>; 392 power-domains = <&cpg>; 393 status = "disabled"; 394 }; 395 396 i2c1: i2c@10058400 { 397 #address-cells = <1>; 398 #size-cells = <0>; 399 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 400 reg = <0 0x10058400 0 0x400>; 401 interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>, 402 <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>, 403 <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>, 404 <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>, 405 <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>, 406 <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>, 407 <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>, 408 <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>; 409 interrupt-names = "tei", "ri", "ti", "spi", "sti", 410 "naki", "ali", "tmoi"; 411 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 412 clock-frequency = <100000>; 413 resets = <&cpg R9A07G043_I2C1_MRST>; 414 power-domains = <&cpg>; 415 status = "disabled"; 416 }; 417 418 i2c2: i2c@10058800 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 422 reg = <0 0x10058800 0 0x400>; 423 interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>, 424 <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>, 425 <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>, 426 <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>, 427 <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>, 428 <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>, 429 <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>, 430 <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>; 431 interrupt-names = "tei", "ri", "ti", "spi", "sti", 432 "naki", "ali", "tmoi"; 433 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 434 clock-frequency = <100000>; 435 resets = <&cpg R9A07G043_I2C2_MRST>; 436 power-domains = <&cpg>; 437 status = "disabled"; 438 }; 439 440 i2c3: i2c@10058c00 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 444 reg = <0 0x10058c00 0 0x400>; 445 interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>, 446 <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>, 447 <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>, 448 <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>, 449 <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>, 450 <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>, 451 <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>, 452 <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>; 453 interrupt-names = "tei", "ri", "ti", "spi", "sti", 454 "naki", "ali", "tmoi"; 455 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 456 clock-frequency = <100000>; 457 resets = <&cpg R9A07G043_I2C3_MRST>; 458 power-domains = <&cpg>; 459 status = "disabled"; 460 }; 461 462 adc: adc@10059000 { 463 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; 464 reg = <0 0x10059000 0 0x400>; 465 interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>; 466 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, 467 <&cpg CPG_MOD R9A07G043_ADC_PCLK>; 468 clock-names = "adclk", "pclk"; 469 resets = <&cpg R9A07G043_ADC_PRESETN>, 470 <&cpg R9A07G043_ADC_ADRST_N>; 471 reset-names = "presetn", "adrst-n"; 472 power-domains = <&cpg>; 473 status = "disabled"; 474 475 #address-cells = <1>; 476 #size-cells = <0>; 477 478 channel@0 { 479 reg = <0>; 480 }; 481 channel@1 { 482 reg = <1>; 483 }; 484 }; 485 486 tsu: thermal@10059400 { 487 compatible = "renesas,r9a07g043-tsu", 488 "renesas,rzg2l-tsu"; 489 reg = <0 0x10059400 0 0x400>; 490 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; 491 resets = <&cpg R9A07G043_TSU_PRESETN>; 492 power-domains = <&cpg>; 493 #thermal-sensor-cells = <1>; 494 }; 495 496 sbc: spi@10060000 { 497 compatible = "renesas,r9a07g043-rpc-if", 498 "renesas,rzg2l-rpc-if"; 499 reg = <0 0x10060000 0 0x10000>, 500 <0 0x20000000 0 0x10000000>, 501 <0 0x10070000 0 0x10000>; 502 reg-names = "regs", "dirmap", "wbuf"; 503 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, 504 <&cpg CPG_MOD R9A07G043_SPI_CLK>; 505 resets = <&cpg R9A07G043_SPI_RST>; 506 power-domains = <&cpg>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 cpg: clock-controller@11010000 { 513 compatible = "renesas,r9a07g043-cpg"; 514 reg = <0 0x11010000 0 0x10000>; 515 clocks = <&extal_clk>; 516 clock-names = "extal"; 517 #clock-cells = <2>; 518 #reset-cells = <1>; 519 #power-domain-cells = <0>; 520 }; 521 522 sysc: system-controller@11020000 { 523 compatible = "renesas,r9a07g043-sysc"; 524 reg = <0 0x11020000 0 0x10000>; 525 status = "disabled"; 526 }; 527 528 pinctrl: pinctrl@11030000 { 529 compatible = "renesas,r9a07g043-pinctrl"; 530 reg = <0 0x11030000 0 0x10000>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 gpio-ranges = <&pinctrl 0 0 152>; 534 #interrupt-cells = <2>; 535 interrupt-controller; 536 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 537 power-domains = <&cpg>; 538 resets = <&cpg R9A07G043_GPIO_RSTN>, 539 <&cpg R9A07G043_GPIO_PORT_RESETN>, 540 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 541 }; 542 543 dmac: dma-controller@11820000 { 544 compatible = "renesas,r9a07g043-dmac", 545 "renesas,rz-dmac"; 546 reg = <0 0x11820000 0 0x10000>, 547 <0 0x11830000 0 0x10000>; 548 interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>, 549 <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>, 550 <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>, 551 <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>, 552 <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>, 553 <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>, 554 <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>, 555 <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>, 556 <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>, 557 <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>, 558 <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>, 559 <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>, 560 <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>, 561 <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>, 562 <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>, 563 <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>, 564 <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>; 565 interrupt-names = "error", 566 "ch0", "ch1", "ch2", "ch3", 567 "ch4", "ch5", "ch6", "ch7", 568 "ch8", "ch9", "ch10", "ch11", 569 "ch12", "ch13", "ch14", "ch15"; 570 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 571 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 572 power-domains = <&cpg>; 573 resets = <&cpg R9A07G043_DMAC_ARESETN>, 574 <&cpg R9A07G043_DMAC_RST_ASYNC>; 575 #dma-cells = <1>; 576 dma-channels = <16>; 577 }; 578 579 sdhi0: mmc@11c00000 { 580 compatible = "renesas,sdhi-r9a07g043", 581 "renesas,rcar-gen3-sdhi"; 582 reg = <0x0 0x11c00000 0 0x10000>; 583 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>, 584 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 586 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 587 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 588 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 589 clock-names = "core", "clkh", "cd", "aclk"; 590 resets = <&cpg R9A07G043_SDHI0_IXRST>; 591 power-domains = <&cpg>; 592 status = "disabled"; 593 }; 594 595 sdhi1: mmc@11c10000 { 596 compatible = "renesas,sdhi-r9a07g043", 597 "renesas,rcar-gen3-sdhi"; 598 reg = <0x0 0x11c10000 0 0x10000>; 599 interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>, 600 <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 602 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 603 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 604 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 605 clock-names = "core", "clkh", "cd", "aclk"; 606 resets = <&cpg R9A07G043_SDHI1_IXRST>; 607 power-domains = <&cpg>; 608 status = "disabled"; 609 }; 610 611 eth0: ethernet@11c20000 { 612 compatible = "renesas,r9a07g043-gbeth", 613 "renesas,rzg2l-gbeth"; 614 reg = <0 0x11c20000 0 0x10000>; 615 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>, 616 <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>, 617 <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "mux", "fil", "arp_ns"; 619 phy-mode = "rgmii"; 620 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 621 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 622 <&cpg CPG_CORE R9A07G043_CLK_HP>; 623 clock-names = "axi", "chi", "refclk"; 624 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 625 power-domains = <&cpg>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 eth1: ethernet@11c30000 { 632 compatible = "renesas,r9a07g043-gbeth", 633 "renesas,rzg2l-gbeth"; 634 reg = <0 0x11c30000 0 0x10000>; 635 interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>, 636 <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>, 637 <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>; 638 interrupt-names = "mux", "fil", "arp_ns"; 639 phy-mode = "rgmii"; 640 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 641 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 642 <&cpg CPG_CORE R9A07G043_CLK_HP>; 643 clock-names = "axi", "chi", "refclk"; 644 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 645 power-domains = <&cpg>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 phyrst: usbphy-ctrl@11c40000 { 652 compatible = "renesas,r9a07g043-usbphy-ctrl", 653 "renesas,rzg2l-usbphy-ctrl"; 654 reg = <0 0x11c40000 0 0x10000>; 655 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 656 resets = <&cpg R9A07G043_USB_PRESETN>; 657 power-domains = <&cpg>; 658 #reset-cells = <1>; 659 status = "disabled"; 660 }; 661 662 ohci0: usb@11c50000 { 663 compatible = "generic-ohci"; 664 reg = <0 0x11c50000 0 0x100>; 665 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 667 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 668 resets = <&phyrst 0>, 669 <&cpg R9A07G043_USB_U2H0_HRESETN>; 670 phys = <&usb2_phy0 1>; 671 phy-names = "usb"; 672 power-domains = <&cpg>; 673 status = "disabled"; 674 }; 675 676 ohci1: usb@11c70000 { 677 compatible = "generic-ohci"; 678 reg = <0 0x11c70000 0 0x100>; 679 interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 681 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 682 resets = <&phyrst 1>, 683 <&cpg R9A07G043_USB_U2H1_HRESETN>; 684 phys = <&usb2_phy1 1>; 685 phy-names = "usb"; 686 power-domains = <&cpg>; 687 status = "disabled"; 688 }; 689 690 ehci0: usb@11c50100 { 691 compatible = "generic-ehci"; 692 reg = <0 0x11c50100 0 0x100>; 693 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 695 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 696 resets = <&phyrst 0>, 697 <&cpg R9A07G043_USB_U2H0_HRESETN>; 698 phys = <&usb2_phy0 2>; 699 phy-names = "usb"; 700 companion = <&ohci0>; 701 power-domains = <&cpg>; 702 status = "disabled"; 703 }; 704 705 ehci1: usb@11c70100 { 706 compatible = "generic-ehci"; 707 reg = <0 0x11c70100 0 0x100>; 708 interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 710 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 711 resets = <&phyrst 1>, 712 <&cpg R9A07G043_USB_U2H1_HRESETN>; 713 phys = <&usb2_phy1 2>; 714 phy-names = "usb"; 715 companion = <&ohci1>; 716 power-domains = <&cpg>; 717 status = "disabled"; 718 }; 719 720 usb2_phy0: usb-phy@11c50200 { 721 compatible = "renesas,usb2-phy-r9a07g043", 722 "renesas,rzg2l-usb2-phy"; 723 reg = <0 0x11c50200 0 0x700>; 724 interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 726 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 727 resets = <&phyrst 0>; 728 #phy-cells = <1>; 729 power-domains = <&cpg>; 730 status = "disabled"; 731 }; 732 733 usb2_phy1: usb-phy@11c70200 { 734 compatible = "renesas,usb2-phy-r9a07g043", 735 "renesas,rzg2l-usb2-phy"; 736 reg = <0 0x11c70200 0 0x700>; 737 interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 739 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 740 resets = <&phyrst 1>; 741 #phy-cells = <1>; 742 power-domains = <&cpg>; 743 status = "disabled"; 744 }; 745 746 hsusb: usb@11c60000 { 747 compatible = "renesas,usbhs-r9a07g043", 748 "renesas,rza2-usbhs"; 749 reg = <0 0x11c60000 0 0x10000>; 750 interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>, 751 <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>, 752 <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>, 753 <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 755 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 756 resets = <&phyrst 0>, 757 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 758 renesas,buswait = <7>; 759 phys = <&usb2_phy0 3>; 760 phy-names = "usb"; 761 power-domains = <&cpg>; 762 status = "disabled"; 763 }; 764 765 wdt0: watchdog@12800800 { 766 compatible = "renesas,r9a07g043-wdt", 767 "renesas,rzg2l-wdt"; 768 reg = <0 0x12800800 0 0x400>; 769 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 770 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 771 clock-names = "pclk", "oscclk"; 772 interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>, 773 <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-names = "wdt", "perrout"; 775 resets = <&cpg R9A07G043_WDT0_PRESETN>; 776 power-domains = <&cpg>; 777 status = "disabled"; 778 }; 779 780 ostm0: timer@12801000 { 781 compatible = "renesas,r9a07g043-ostm", 782 "renesas,ostm"; 783 reg = <0x0 0x12801000 0x0 0x400>; 784 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>; 785 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 786 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 787 power-domains = <&cpg>; 788 status = "disabled"; 789 }; 790 791 ostm1: timer@12801400 { 792 compatible = "renesas,r9a07g043-ostm", 793 "renesas,ostm"; 794 reg = <0x0 0x12801400 0x0 0x400>; 795 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>; 796 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 797 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 798 power-domains = <&cpg>; 799 status = "disabled"; 800 }; 801 802 ostm2: timer@12801800 { 803 compatible = "renesas,r9a07g043-ostm", 804 "renesas,ostm"; 805 reg = <0x0 0x12801800 0x0 0x400>; 806 interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>; 807 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 808 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 809 power-domains = <&cpg>; 810 status = "disabled"; 811 }; 812 }; 813 814 thermal-zones { 815 cpu-thermal { 816 polling-delay-passive = <250>; 817 polling-delay = <1000>; 818 thermal-sensors = <&tsu 0>; 819 sustainable-power = <717>; 820 821 cooling-maps { 822 map0 { 823 trip = <&target>; 824 cooling-device = <&cpu0 0 2>; 825 contribution = <1024>; 826 }; 827 }; 828 829 trips { 830 sensor_crit: sensor-crit { 831 temperature = <125000>; 832 hysteresis = <1000>; 833 type = "critical"; 834 }; 835 836 target: trip-point { 837 temperature = <100000>; 838 hysteresis = <1000>; 839 type = "passive"; 840 }; 841 }; 842 }; 843 }; 844}; 845