r9a07g043.dtsi (70a89009f723ff72ab923ae6f7581ad9e95618c3) r9a07g043.dtsi (22ec868997108e514fe380171c45578da630a0ec)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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70 soc: soc {
71 compatible = "simple-bus";
72 interrupt-parent = <&gic>;
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 ssi0: ssi@10049c00 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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70 soc: soc {
71 compatible = "simple-bus";
72 interrupt-parent = <&gic>;
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 ssi0: ssi@10049c00 {
78 compatible = "renesas,r9a07g043-ssi",
79 "renesas,rz-ssi";
78 reg = <0 0x10049c00 0 0x400>;
80 reg = <0 0x10049c00 0 0x400>;
81 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
83 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
84 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
85 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
88 <&audio_clk1>, <&audio_clk2>;
89 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
91 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
92 dma-names = "tx", "rx";
93 power-domains = <&cpg>;
79 #sound-dai-cells = <0>;
94 #sound-dai-cells = <0>;
80 /* place holder */
95 status = "disabled";
81 };
82
96 };
97
98 ssi1: ssi@1004a000 {
99 compatible = "renesas,r9a07g043-ssi",
100 "renesas,rz-ssi";
101 reg = <0 0x1004a000 0 0x400>;
102 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
104 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
105 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
109 <&audio_clk1>, <&audio_clk2>;
110 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
112 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
113 dma-names = "tx", "rx";
114 power-domains = <&cpg>;
115 #sound-dai-cells = <0>;
116 status = "disabled";
117 };
118
119 ssi2: ssi@1004a400 {
120 compatible = "renesas,r9a07g043-ssi",
121 "renesas,rz-ssi";
122 reg = <0 0x1004a400 0 0x400>;
123 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
125 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
126 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
127 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
130 <&audio_clk1>, <&audio_clk2>;
131 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
133 dmas = <&dmac 0x265f>;
134 dma-names = "rt";
135 power-domains = <&cpg>;
136 #sound-dai-cells = <0>;
137 status = "disabled";
138 };
139
140 ssi3: ssi@1004a800 {
141 compatible = "renesas,r9a07g043-ssi",
142 "renesas,rz-ssi";
143 reg = <0 0x1004a800 0 0x400>;
144 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
146 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
147 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
148 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
151 <&audio_clk1>, <&audio_clk2>;
152 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
154 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
155 dma-names = "tx", "rx";
156 power-domains = <&cpg>;
157 #sound-dai-cells = <0>;
158 status = "disabled";
159 };
160
161 spi0: spi@1004ac00 {
162 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
163 reg = <0 0x1004ac00 0 0x400>;
164 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-names = "error", "rx", "tx";
168 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
169 resets = <&cpg R9A07G043_RSPI0_RST>;
170 power-domains = <&cpg>;
171 num-cs = <1>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 status = "disabled";
175 };
176
83 spi1: spi@1004b000 {
177 spi1: spi@1004b000 {
178 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
84 reg = <0 0x1004b000 0 0x400>;
179 reg = <0 0x1004b000 0 0x400>;
180 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
183 interrupt-names = "error", "rx", "tx";
184 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
185 resets = <&cpg R9A07G043_RSPI1_RST>;
186 power-domains = <&cpg>;
187 num-cs = <1>;
85 #address-cells = <1>;
86 #size-cells = <0>;
188 #address-cells = <1>;
189 #size-cells = <0>;
87 /* place holder */
190 status = "disabled";
88 };
89
191 };
192
193 spi2: spi@1004b400 {
194 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
195 reg = <0 0x1004b400 0 0x400>;
196 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
199 interrupt-names = "error", "rx", "tx";
200 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
201 resets = <&cpg R9A07G043_RSPI2_RST>;
202 power-domains = <&cpg>;
203 num-cs = <1>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 status = "disabled";
207 };
208
90 scif0: serial@1004b800 {
91 compatible = "renesas,scif-r9a07g043",
92 "renesas,scif-r9a07g044";
93 reg = <0 0x1004b800 0 0x400>;
94 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,

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208 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
209 clock-names = "fck";
210 power-domains = <&cpg>;
211 resets = <&cpg R9A07G043_SCI1_RST>;
212 status = "disabled";
213 };
214
215 canfd: can@10050000 {
209 scif0: serial@1004b800 {
210 compatible = "renesas,scif-r9a07g043",
211 "renesas,scif-r9a07g044";
212 reg = <0 0x1004b800 0 0x400>;
213 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,

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327 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
328 clock-names = "fck";
329 power-domains = <&cpg>;
330 resets = <&cpg R9A07G043_SCI1_RST>;
331 status = "disabled";
332 };
333
334 canfd: can@10050000 {
335 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
216 reg = <0 0x10050000 0 0x8000>;
336 reg = <0 0x10050000 0 0x8000>;
217 /* place holder */
337 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-names = "g_err", "g_recc",
346 "ch0_err", "ch0_rec", "ch0_trx",
347 "ch1_err", "ch1_rec", "ch1_trx";
348 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
349 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
350 <&can_clk>;
351 clock-names = "fck", "canfd", "can_clk";
352 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
353 assigned-clock-rates = <50000000>;
354 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
355 <&cpg R9A07G043_CANFD_RSTC_N>;
356 reset-names = "rstp_n", "rstc_n";
357 power-domains = <&cpg>;
358 status = "disabled";
359
360 channel0 {
361 status = "disabled";
362 };
363 channel1 {
364 status = "disabled";
365 };
218 };
219
220 i2c0: i2c@10058000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
366 };
367
368 i2c0: i2c@10058000 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
223 reg = <0 0x10058000 0 0x400>;
372 reg = <0 0x10058000 0 0x400>;
224 /* place holder */
373 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
375 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
376 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
381 interrupt-names = "tei", "ri", "ti", "spi", "sti",
382 "naki", "ali", "tmoi";
383 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
384 clock-frequency = <100000>;
385 resets = <&cpg R9A07G043_I2C0_MRST>;
386 power-domains = <&cpg>;
387 status = "disabled";
225 };
226
227 i2c1: i2c@10058400 {
228 #address-cells = <1>;
229 #size-cells = <0>;
388 };
389
390 i2c1: i2c@10058400 {
391 #address-cells = <1>;
392 #size-cells = <0>;
393 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
230 reg = <0 0x10058400 0 0x400>;
394 reg = <0 0x10058400 0 0x400>;
231 /* place holder */
395 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
397 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
398 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
403 interrupt-names = "tei", "ri", "ti", "spi", "sti",
404 "naki", "ali", "tmoi";
405 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
406 clock-frequency = <100000>;
407 resets = <&cpg R9A07G043_I2C1_MRST>;
408 power-domains = <&cpg>;
409 status = "disabled";
232 };
233
410 };
411
412 i2c2: i2c@10058800 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
416 reg = <0 0x10058800 0 0x400>;
417 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
419 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
420 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "tei", "ri", "ti", "spi", "sti",
426 "naki", "ali", "tmoi";
427 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
428 clock-frequency = <100000>;
429 resets = <&cpg R9A07G043_I2C2_MRST>;
430 power-domains = <&cpg>;
431 status = "disabled";
432 };
433
234 i2c3: i2c@10058c00 {
235 #address-cells = <1>;
236 #size-cells = <0>;
434 i2c3: i2c@10058c00 {
435 #address-cells = <1>;
436 #size-cells = <0>;
437 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
237 reg = <0 0x10058c00 0 0x400>;
438 reg = <0 0x10058c00 0 0x400>;
238 /* place holder */
439 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
441 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
442 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "tei", "ri", "ti", "spi", "sti",
448 "naki", "ali", "tmoi";
449 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
450 clock-frequency = <100000>;
451 resets = <&cpg R9A07G043_I2C3_MRST>;
452 power-domains = <&cpg>;
453 status = "disabled";
239 };
240
241 adc: adc@10059000 {
242 reg = <0 0x10059000 0 0x400>;
243 /* place holder */
244 };
245
246 sbc: spi@10060000 {

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401 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
402 power-domains = <&cpg>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 };
407
408 phyrst: usbphy-ctrl@11c40000 {
454 };
455
456 adc: adc@10059000 {
457 reg = <0 0x10059000 0 0x400>;
458 /* place holder */
459 };
460
461 sbc: spi@10060000 {

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616 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
617 power-domains = <&cpg>;
618 #address-cells = <1>;
619 #size-cells = <0>;
620 status = "disabled";
621 };
622
623 phyrst: usbphy-ctrl@11c40000 {
624 compatible = "renesas,r9a07g043-usbphy-ctrl",
625 "renesas,rzg2l-usbphy-ctrl";
409 reg = <0 0x11c40000 0 0x10000>;
626 reg = <0 0x11c40000 0 0x10000>;
410 /* place holder */
627 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
628 resets = <&cpg R9A07G043_USB_PRESETN>;
629 power-domains = <&cpg>;
630 #reset-cells = <1>;
631 status = "disabled";
411 };
412
413 ohci0: usb@11c50000 {
632 };
633
634 ohci0: usb@11c50000 {
635 compatible = "generic-ohci";
414 reg = <0 0x11c50000 0 0x100>;
636 reg = <0 0x11c50000 0 0x100>;
415 /* place holder */
637 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
639 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
640 resets = <&phyrst 0>,
641 <&cpg R9A07G043_USB_U2H0_HRESETN>;
642 phys = <&usb2_phy0 1>;
643 phy-names = "usb";
644 power-domains = <&cpg>;
645 status = "disabled";
416 };
417
418 ohci1: usb@11c70000 {
646 };
647
648 ohci1: usb@11c70000 {
649 compatible = "generic-ohci";
419 reg = <0 0x11c70000 0 0x100>;
650 reg = <0 0x11c70000 0 0x100>;
420 /* place holder */
651 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
653 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
654 resets = <&phyrst 1>,
655 <&cpg R9A07G043_USB_U2H1_HRESETN>;
656 phys = <&usb2_phy1 1>;
657 phy-names = "usb";
658 power-domains = <&cpg>;
659 status = "disabled";
421 };
422
423 ehci0: usb@11c50100 {
660 };
661
662 ehci0: usb@11c50100 {
663 compatible = "generic-ehci";
424 reg = <0 0x11c50100 0 0x100>;
664 reg = <0 0x11c50100 0 0x100>;
425 /* place holder */
665 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
667 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
668 resets = <&phyrst 0>,
669 <&cpg R9A07G043_USB_U2H0_HRESETN>;
670 phys = <&usb2_phy0 2>;
671 phy-names = "usb";
672 companion = <&ohci0>;
673 power-domains = <&cpg>;
674 status = "disabled";
426 };
427
428 ehci1: usb@11c70100 {
675 };
676
677 ehci1: usb@11c70100 {
678 compatible = "generic-ehci";
429 reg = <0 0x11c70100 0 0x100>;
679 reg = <0 0x11c70100 0 0x100>;
430 /* place holder */
680 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
682 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
683 resets = <&phyrst 1>,
684 <&cpg R9A07G043_USB_U2H1_HRESETN>;
685 phys = <&usb2_phy1 2>;
686 phy-names = "usb";
687 companion = <&ohci1>;
688 power-domains = <&cpg>;
689 status = "disabled";
431 };
432
433 usb2_phy0: usb-phy@11c50200 {
690 };
691
692 usb2_phy0: usb-phy@11c50200 {
693 compatible = "renesas,usb2-phy-r9a07g043",
694 "renesas,rzg2l-usb2-phy";
434 reg = <0 0x11c50200 0 0x700>;
695 reg = <0 0x11c50200 0 0x700>;
435 /* place holder */
696 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
698 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
699 resets = <&phyrst 0>;
700 #phy-cells = <1>;
701 power-domains = <&cpg>;
702 status = "disabled";
436 };
437
438 usb2_phy1: usb-phy@11c70200 {
703 };
704
705 usb2_phy1: usb-phy@11c70200 {
706 compatible = "renesas,usb2-phy-r9a07g043",
707 "renesas,rzg2l-usb2-phy";
439 reg = <0 0x11c70200 0 0x700>;
708 reg = <0 0x11c70200 0 0x700>;
440 /* place holder */
709 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
711 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
712 resets = <&phyrst 1>;
713 #phy-cells = <1>;
714 power-domains = <&cpg>;
715 status = "disabled";
441 };
442
443 hsusb: usb@11c60000 {
716 };
717
718 hsusb: usb@11c60000 {
719 compatible = "renesas,usbhs-r9a07g043",
720 "renesas,rza2-usbhs";
444 reg = <0 0x11c60000 0 0x10000>;
721 reg = <0 0x11c60000 0 0x10000>;
445 /* place holder */
722 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
723 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
727 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
728 resets = <&phyrst 0>,
729 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
730 renesas,buswait = <7>;
731 phys = <&usb2_phy0 3>;
732 phy-names = "usb";
733 power-domains = <&cpg>;
734 status = "disabled";
446 };
447
448 wdt0: watchdog@12800800 {
735 };
736
737 wdt0: watchdog@12800800 {
738 compatible = "renesas,r9a07g043-wdt",
739 "renesas,rzg2l-wdt";
449 reg = <0 0x12800800 0 0x400>;
740 reg = <0 0x12800800 0 0x400>;
450 /* place holder */
741 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
742 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
743 clock-names = "pclk", "oscclk";
744 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
746 interrupt-names = "wdt", "perrout";
747 resets = <&cpg R9A07G043_WDT0_PRESETN>;
748 power-domains = <&cpg>;
749 status = "disabled";
451 };
452
453 wdt2: watchdog@12800400 {
750 };
751
752 wdt2: watchdog@12800400 {
753 compatible = "renesas,r9a07g043-wdt",
754 "renesas,rzg2l-wdt";
454 reg = <0 0x12800400 0 0x400>;
755 reg = <0 0x12800400 0 0x400>;
455 /* place holder */
756 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
757 <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
758 clock-names = "pclk", "oscclk";
759 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
761 interrupt-names = "wdt", "perrout";
762 resets = <&cpg R9A07G043_WDT2_PRESETN>;
763 power-domains = <&cpg>;
764 status = "disabled";
456 };
457
458 ostm0: timer@12801000 {
765 };
766
767 ostm0: timer@12801000 {
768 compatible = "renesas,r9a07g043-ostm",
769 "renesas,ostm";
459 reg = <0x0 0x12801000 0x0 0x400>;
770 reg = <0x0 0x12801000 0x0 0x400>;
460 /* place holder */
771 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
772 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
773 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
774 power-domains = <&cpg>;
775 status = "disabled";
461 };
462
463 ostm1: timer@12801400 {
776 };
777
778 ostm1: timer@12801400 {
779 compatible = "renesas,r9a07g043-ostm",
780 "renesas,ostm";
464 reg = <0x0 0x12801400 0x0 0x400>;
781 reg = <0x0 0x12801400 0x0 0x400>;
465 /* place holder */
782 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
783 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
784 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
785 power-domains = <&cpg>;
786 status = "disabled";
466 };
467
468 ostm2: timer@12801800 {
787 };
788
789 ostm2: timer@12801800 {
790 compatible = "renesas,r9a07g043-ostm",
791 "renesas,ostm";
469 reg = <0x0 0x12801800 0x0 0x400>;
792 reg = <0x0 0x12801800 0x0 0x400>;
470 /* place holder */
793 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
794 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
795 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
796 power-domains = <&cpg>;
797 status = "disabled";
471 };
472 };
473
474 timer {
475 compatible = "arm,armv8-timer";
476 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
477 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
478 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
479 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
480 };
481};
798 };
799 };
800
801 timer {
802 compatible = "arm,armv8-timer";
803 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
804 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
805 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
806 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
807 };
808};