1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio-clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio-clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a55"; 51 reg = <0>; 52 device_type = "cpu"; 53 next-level-cache = <&L3_CA55>; 54 enable-method = "psci"; 55 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 56 }; 57 58 L3_CA55: cache-controller-0 { 59 compatible = "cache"; 60 cache-unified; 61 cache-size = <0x40000>; 62 }; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0", "arm,psci-0.2"; 67 method = "smc"; 68 }; 69 70 soc: soc { 71 compatible = "simple-bus"; 72 interrupt-parent = <&gic>; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 ssi0: ssi@10049c00 { 78 compatible = "renesas,r9a07g043-ssi", 79 "renesas,rz-ssi"; 80 reg = <0 0x10049c00 0 0x400>; 81 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 83 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 84 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 85 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 88 <&audio_clk1>, <&audio_clk2>; 89 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 91 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 92 dma-names = "tx", "rx"; 93 power-domains = <&cpg>; 94 #sound-dai-cells = <0>; 95 status = "disabled"; 96 }; 97 98 ssi1: ssi@1004a000 { 99 compatible = "renesas,r9a07g043-ssi", 100 "renesas,rz-ssi"; 101 reg = <0 0x1004a000 0 0x400>; 102 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 104 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 105 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 106 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 109 <&audio_clk1>, <&audio_clk2>; 110 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 112 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 113 dma-names = "tx", "rx"; 114 power-domains = <&cpg>; 115 #sound-dai-cells = <0>; 116 status = "disabled"; 117 }; 118 119 ssi2: ssi@1004a400 { 120 compatible = "renesas,r9a07g043-ssi", 121 "renesas,rz-ssi"; 122 reg = <0 0x1004a400 0 0x400>; 123 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 125 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 126 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 127 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 130 <&audio_clk1>, <&audio_clk2>; 131 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 133 dmas = <&dmac 0x265f>; 134 dma-names = "rt"; 135 power-domains = <&cpg>; 136 #sound-dai-cells = <0>; 137 status = "disabled"; 138 }; 139 140 ssi3: ssi@1004a800 { 141 compatible = "renesas,r9a07g043-ssi", 142 "renesas,rz-ssi"; 143 reg = <0 0x1004a800 0 0x400>; 144 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 146 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 147 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 148 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 151 <&audio_clk1>, <&audio_clk2>; 152 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 154 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 155 dma-names = "tx", "rx"; 156 power-domains = <&cpg>; 157 #sound-dai-cells = <0>; 158 status = "disabled"; 159 }; 160 161 spi0: spi@1004ac00 { 162 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 163 reg = <0 0x1004ac00 0 0x400>; 164 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-names = "error", "rx", "tx"; 168 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 169 resets = <&cpg R9A07G043_RSPI0_RST>; 170 power-domains = <&cpg>; 171 num-cs = <1>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 status = "disabled"; 175 }; 176 177 spi1: spi@1004b000 { 178 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 179 reg = <0 0x1004b000 0 0x400>; 180 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 183 interrupt-names = "error", "rx", "tx"; 184 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 185 resets = <&cpg R9A07G043_RSPI1_RST>; 186 power-domains = <&cpg>; 187 num-cs = <1>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 status = "disabled"; 191 }; 192 193 spi2: spi@1004b400 { 194 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 195 reg = <0 0x1004b400 0 0x400>; 196 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 199 interrupt-names = "error", "rx", "tx"; 200 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 201 resets = <&cpg R9A07G043_RSPI2_RST>; 202 power-domains = <&cpg>; 203 num-cs = <1>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 status = "disabled"; 207 }; 208 209 scif0: serial@1004b800 { 210 compatible = "renesas,scif-r9a07g043", 211 "renesas,scif-r9a07g044"; 212 reg = <0 0x1004b800 0 0x400>; 213 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-names = "eri", "rxi", "txi", 220 "bri", "dri", "tei"; 221 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 222 clock-names = "fck"; 223 power-domains = <&cpg>; 224 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 225 status = "disabled"; 226 }; 227 228 scif1: serial@1004bc00 { 229 compatible = "renesas,scif-r9a07g043", 230 "renesas,scif-r9a07g044"; 231 reg = <0 0x1004bc00 0 0x400>; 232 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-names = "eri", "rxi", "txi", 239 "bri", "dri", "tei"; 240 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 241 clock-names = "fck"; 242 power-domains = <&cpg>; 243 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 244 status = "disabled"; 245 }; 246 247 scif2: serial@1004c000 { 248 compatible = "renesas,scif-r9a07g043", 249 "renesas,scif-r9a07g044"; 250 reg = <0 0x1004c000 0 0x400>; 251 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-names = "eri", "rxi", "txi", 258 "bri", "dri", "tei"; 259 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 260 clock-names = "fck"; 261 power-domains = <&cpg>; 262 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 263 status = "disabled"; 264 }; 265 266 scif3: serial@1004c400 { 267 compatible = "renesas,scif-r9a07g043", 268 "renesas,scif-r9a07g044"; 269 reg = <0 0x1004c400 0 0x400>; 270 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "eri", "rxi", "txi", 277 "bri", "dri", "tei"; 278 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 279 clock-names = "fck"; 280 power-domains = <&cpg>; 281 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 282 status = "disabled"; 283 }; 284 285 scif4: serial@1004c800 { 286 compatible = "renesas,scif-r9a07g043", 287 "renesas,scif-r9a07g044"; 288 reg = <0 0x1004c800 0 0x400>; 289 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 295 interrupt-names = "eri", "rxi", "txi", 296 "bri", "dri", "tei"; 297 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 298 clock-names = "fck"; 299 power-domains = <&cpg>; 300 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 301 status = "disabled"; 302 }; 303 304 sci0: serial@1004d000 { 305 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 306 reg = <0 0x1004d000 0 0x400>; 307 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 311 interrupt-names = "eri", "rxi", "txi", "tei"; 312 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 313 clock-names = "fck"; 314 power-domains = <&cpg>; 315 resets = <&cpg R9A07G043_SCI0_RST>; 316 status = "disabled"; 317 }; 318 319 sci1: serial@1004d400 { 320 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 321 reg = <0 0x1004d400 0 0x400>; 322 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 326 interrupt-names = "eri", "rxi", "txi", "tei"; 327 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 328 clock-names = "fck"; 329 power-domains = <&cpg>; 330 resets = <&cpg R9A07G043_SCI1_RST>; 331 status = "disabled"; 332 }; 333 334 canfd: can@10050000 { 335 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 336 reg = <0 0x10050000 0 0x8000>; 337 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-names = "g_err", "g_recc", 346 "ch0_err", "ch0_rec", "ch0_trx", 347 "ch1_err", "ch1_rec", "ch1_trx"; 348 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 349 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 350 <&can_clk>; 351 clock-names = "fck", "canfd", "can_clk"; 352 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 353 assigned-clock-rates = <50000000>; 354 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 355 <&cpg R9A07G043_CANFD_RSTC_N>; 356 reset-names = "rstp_n", "rstc_n"; 357 power-domains = <&cpg>; 358 status = "disabled"; 359 360 channel0 { 361 status = "disabled"; 362 }; 363 channel1 { 364 status = "disabled"; 365 }; 366 }; 367 368 i2c0: i2c@10058000 { 369 #address-cells = <1>; 370 #size-cells = <0>; 371 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 372 reg = <0 0x10058000 0 0x400>; 373 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 375 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-names = "tei", "ri", "ti", "spi", "sti", 382 "naki", "ali", "tmoi"; 383 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 384 clock-frequency = <100000>; 385 resets = <&cpg R9A07G043_I2C0_MRST>; 386 power-domains = <&cpg>; 387 status = "disabled"; 388 }; 389 390 i2c1: i2c@10058400 { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 394 reg = <0 0x10058400 0 0x400>; 395 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 397 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 398 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "tei", "ri", "ti", "spi", "sti", 404 "naki", "ali", "tmoi"; 405 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 406 clock-frequency = <100000>; 407 resets = <&cpg R9A07G043_I2C1_MRST>; 408 power-domains = <&cpg>; 409 status = "disabled"; 410 }; 411 412 i2c2: i2c@10058800 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 416 reg = <0 0x10058800 0 0x400>; 417 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "tei", "ri", "ti", "spi", "sti", 426 "naki", "ali", "tmoi"; 427 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 428 clock-frequency = <100000>; 429 resets = <&cpg R9A07G043_I2C2_MRST>; 430 power-domains = <&cpg>; 431 status = "disabled"; 432 }; 433 434 i2c3: i2c@10058c00 { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 438 reg = <0 0x10058c00 0 0x400>; 439 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "tei", "ri", "ti", "spi", "sti", 448 "naki", "ali", "tmoi"; 449 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 450 clock-frequency = <100000>; 451 resets = <&cpg R9A07G043_I2C3_MRST>; 452 power-domains = <&cpg>; 453 status = "disabled"; 454 }; 455 456 adc: adc@10059000 { 457 reg = <0 0x10059000 0 0x400>; 458 /* place holder */ 459 }; 460 461 sbc: spi@10060000 { 462 reg = <0 0x10060000 0 0x10000>, 463 <0 0x20000000 0 0x10000000>, 464 <0 0x10070000 0 0x10000>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 /* place holder */ 468 }; 469 470 cpg: clock-controller@11010000 { 471 compatible = "renesas,r9a07g043-cpg"; 472 reg = <0 0x11010000 0 0x10000>; 473 clocks = <&extal_clk>; 474 clock-names = "extal"; 475 #clock-cells = <2>; 476 #reset-cells = <1>; 477 #power-domain-cells = <0>; 478 }; 479 480 sysc: system-controller@11020000 { 481 compatible = "renesas,r9a07g043-sysc"; 482 reg = <0 0x11020000 0 0x10000>; 483 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "lpm_int", "ca55stbydone_int", 488 "cm33stbyr_int", "ca55_deny"; 489 status = "disabled"; 490 }; 491 492 pinctrl: pinctrl@11030000 { 493 compatible = "renesas,r9a07g043-pinctrl"; 494 reg = <0 0x11030000 0 0x10000>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 gpio-ranges = <&pinctrl 0 0 152>; 498 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 499 power-domains = <&cpg>; 500 resets = <&cpg R9A07G043_GPIO_RSTN>, 501 <&cpg R9A07G043_GPIO_PORT_RESETN>, 502 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 503 }; 504 505 dmac: dma-controller@11820000 { 506 compatible = "renesas,r9a07g043-dmac", 507 "renesas,rz-dmac"; 508 reg = <0 0x11820000 0 0x10000>, 509 <0 0x11830000 0 0x10000>; 510 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 511 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 512 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 514 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 515 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 516 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 517 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 518 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 519 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 521 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 522 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 523 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 524 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 525 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 526 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 527 interrupt-names = "error", 528 "ch0", "ch1", "ch2", "ch3", 529 "ch4", "ch5", "ch6", "ch7", 530 "ch8", "ch9", "ch10", "ch11", 531 "ch12", "ch13", "ch14", "ch15"; 532 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 533 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 534 power-domains = <&cpg>; 535 resets = <&cpg R9A07G043_DMAC_ARESETN>, 536 <&cpg R9A07G043_DMAC_RST_ASYNC>; 537 #dma-cells = <1>; 538 dma-channels = <16>; 539 }; 540 541 gic: interrupt-controller@11900000 { 542 compatible = "arm,gic-v3"; 543 #interrupt-cells = <3>; 544 #address-cells = <0>; 545 interrupt-controller; 546 reg = <0x0 0x11900000 0 0x40000>, 547 <0x0 0x11940000 0 0x60000>; 548 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 549 }; 550 551 sdhi0: mmc@11c00000 { 552 compatible = "renesas,sdhi-r9a07g043", 553 "renesas,rcar-gen3-sdhi"; 554 reg = <0x0 0x11c00000 0 0x10000>; 555 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 558 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 559 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 560 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 561 clock-names = "core", "clkh", "cd", "aclk"; 562 resets = <&cpg R9A07G043_SDHI0_IXRST>; 563 power-domains = <&cpg>; 564 status = "disabled"; 565 }; 566 567 sdhi1: mmc@11c10000 { 568 compatible = "renesas,sdhi-r9a07g043", 569 "renesas,rcar-gen3-sdhi"; 570 reg = <0x0 0x11c10000 0 0x10000>; 571 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 574 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 575 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 576 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 577 clock-names = "core", "clkh", "cd", "aclk"; 578 resets = <&cpg R9A07G043_SDHI1_IXRST>; 579 power-domains = <&cpg>; 580 status = "disabled"; 581 }; 582 583 eth0: ethernet@11c20000 { 584 compatible = "renesas,r9a07g043-gbeth", 585 "renesas,rzg2l-gbeth"; 586 reg = <0 0x11c20000 0 0x10000>; 587 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "mux", "fil", "arp_ns"; 591 phy-mode = "rgmii"; 592 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 593 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 594 <&cpg CPG_CORE R9A07G043_CLK_HP>; 595 clock-names = "axi", "chi", "refclk"; 596 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 597 power-domains = <&cpg>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 eth1: ethernet@11c30000 { 604 compatible = "renesas,r9a07g043-gbeth", 605 "renesas,rzg2l-gbeth"; 606 reg = <0 0x11c30000 0 0x10000>; 607 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 610 interrupt-names = "mux", "fil", "arp_ns"; 611 phy-mode = "rgmii"; 612 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 613 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 614 <&cpg CPG_CORE R9A07G043_CLK_HP>; 615 clock-names = "axi", "chi", "refclk"; 616 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 617 power-domains = <&cpg>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 phyrst: usbphy-ctrl@11c40000 { 624 compatible = "renesas,r9a07g043-usbphy-ctrl", 625 "renesas,rzg2l-usbphy-ctrl"; 626 reg = <0 0x11c40000 0 0x10000>; 627 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 628 resets = <&cpg R9A07G043_USB_PRESETN>; 629 power-domains = <&cpg>; 630 #reset-cells = <1>; 631 status = "disabled"; 632 }; 633 634 ohci0: usb@11c50000 { 635 compatible = "generic-ohci"; 636 reg = <0 0x11c50000 0 0x100>; 637 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 639 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 640 resets = <&phyrst 0>, 641 <&cpg R9A07G043_USB_U2H0_HRESETN>; 642 phys = <&usb2_phy0 1>; 643 phy-names = "usb"; 644 power-domains = <&cpg>; 645 status = "disabled"; 646 }; 647 648 ohci1: usb@11c70000 { 649 compatible = "generic-ohci"; 650 reg = <0 0x11c70000 0 0x100>; 651 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 653 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 654 resets = <&phyrst 1>, 655 <&cpg R9A07G043_USB_U2H1_HRESETN>; 656 phys = <&usb2_phy1 1>; 657 phy-names = "usb"; 658 power-domains = <&cpg>; 659 status = "disabled"; 660 }; 661 662 ehci0: usb@11c50100 { 663 compatible = "generic-ehci"; 664 reg = <0 0x11c50100 0 0x100>; 665 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 667 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 668 resets = <&phyrst 0>, 669 <&cpg R9A07G043_USB_U2H0_HRESETN>; 670 phys = <&usb2_phy0 2>; 671 phy-names = "usb"; 672 companion = <&ohci0>; 673 power-domains = <&cpg>; 674 status = "disabled"; 675 }; 676 677 ehci1: usb@11c70100 { 678 compatible = "generic-ehci"; 679 reg = <0 0x11c70100 0 0x100>; 680 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 682 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 683 resets = <&phyrst 1>, 684 <&cpg R9A07G043_USB_U2H1_HRESETN>; 685 phys = <&usb2_phy1 2>; 686 phy-names = "usb"; 687 companion = <&ohci1>; 688 power-domains = <&cpg>; 689 status = "disabled"; 690 }; 691 692 usb2_phy0: usb-phy@11c50200 { 693 compatible = "renesas,usb2-phy-r9a07g043", 694 "renesas,rzg2l-usb2-phy"; 695 reg = <0 0x11c50200 0 0x700>; 696 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 698 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 699 resets = <&phyrst 0>; 700 #phy-cells = <1>; 701 power-domains = <&cpg>; 702 status = "disabled"; 703 }; 704 705 usb2_phy1: usb-phy@11c70200 { 706 compatible = "renesas,usb2-phy-r9a07g043", 707 "renesas,rzg2l-usb2-phy"; 708 reg = <0 0x11c70200 0 0x700>; 709 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 711 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 712 resets = <&phyrst 1>; 713 #phy-cells = <1>; 714 power-domains = <&cpg>; 715 status = "disabled"; 716 }; 717 718 hsusb: usb@11c60000 { 719 compatible = "renesas,usbhs-r9a07g043", 720 "renesas,rza2-usbhs"; 721 reg = <0 0x11c60000 0 0x10000>; 722 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 723 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 727 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 728 resets = <&phyrst 0>, 729 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 730 renesas,buswait = <7>; 731 phys = <&usb2_phy0 3>; 732 phy-names = "usb"; 733 power-domains = <&cpg>; 734 status = "disabled"; 735 }; 736 737 wdt0: watchdog@12800800 { 738 compatible = "renesas,r9a07g043-wdt", 739 "renesas,rzg2l-wdt"; 740 reg = <0 0x12800800 0 0x400>; 741 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 742 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 743 clock-names = "pclk", "oscclk"; 744 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "wdt", "perrout"; 747 resets = <&cpg R9A07G043_WDT0_PRESETN>; 748 power-domains = <&cpg>; 749 status = "disabled"; 750 }; 751 752 wdt2: watchdog@12800400 { 753 compatible = "renesas,r9a07g043-wdt", 754 "renesas,rzg2l-wdt"; 755 reg = <0 0x12800400 0 0x400>; 756 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, 757 <&cpg CPG_MOD R9A07G043_WDT2_CLK>; 758 clock-names = "pclk", "oscclk"; 759 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "wdt", "perrout"; 762 resets = <&cpg R9A07G043_WDT2_PRESETN>; 763 power-domains = <&cpg>; 764 status = "disabled"; 765 }; 766 767 ostm0: timer@12801000 { 768 compatible = "renesas,r9a07g043-ostm", 769 "renesas,ostm"; 770 reg = <0x0 0x12801000 0x0 0x400>; 771 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 772 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 773 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 774 power-domains = <&cpg>; 775 status = "disabled"; 776 }; 777 778 ostm1: timer@12801400 { 779 compatible = "renesas,r9a07g043-ostm", 780 "renesas,ostm"; 781 reg = <0x0 0x12801400 0x0 0x400>; 782 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 783 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 784 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 785 power-domains = <&cpg>; 786 status = "disabled"; 787 }; 788 789 ostm2: timer@12801800 { 790 compatible = "renesas,r9a07g043-ostm", 791 "renesas,ostm"; 792 reg = <0x0 0x12801800 0x0 0x400>; 793 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 794 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 795 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 796 power-domains = <&cpg>; 797 status = "disabled"; 798 }; 799 }; 800 801 timer { 802 compatible = "arm,armv8-timer"; 803 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 804 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 805 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 806 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 807 }; 808}; 809