r9a07g043.dtsi (49669da644cf000eb79dbede55bd04acf3f2f0a0) r9a07g043.dtsi (b9a0be2054964026aa58966ce9724b672f210835)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>
9
10/ {
11 compatible = "renesas,r9a07g043";

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63 opp-1000000000 {
64 opp-hz = /bits/ 64 <1000000000>;
65 opp-microvolt = <1100000>;
66 clock-latency-ns = <300000>;
67 opp-suspend;
68 };
69 };
70
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r9a07g043-cpg.h>
9
10/ {
11 compatible = "renesas,r9a07g043";

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63 opp-1000000000 {
64 opp-hz = /bits/ 64 <1000000000>;
65 opp-microvolt = <1100000>;
66 clock-latency-ns = <300000>;
67 opp-suspend;
68 };
69 };
70
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 cpu0: cpu@0 {
76 compatible = "arm,cortex-a55";
77 reg = <0>;
78 device_type = "cpu";
79 #cooling-cells = <2>;
80 next-level-cache = <&L3_CA55>;
81 enable-method = "psci";
82 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
83 operating-points-v2 = <&cluster0_opp>;
84 };
85
86 L3_CA55: cache-controller-0 {
87 compatible = "cache";
88 cache-unified;
89 cache-size = <0x40000>;
90 };
91 };
92
93 psci {
94 compatible = "arm,psci-1.0", "arm,psci-0.2";
95 method = "smc";
96 };
97
98 soc: soc {
99 compatible = "simple-bus";
71 soc: soc {
72 compatible = "simple-bus";
100 interrupt-parent = <&gic>;
101 #address-cells = <2>;
102 #size-cells = <2>;
103 ranges;
104
105 ssi0: ssi@10049c00 {
106 compatible = "renesas,r9a07g043-ssi",
107 "renesas,rz-ssi";
108 reg = <0 0x10049c00 0 0x400>;

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545 #clock-cells = <2>;
546 #reset-cells = <1>;
547 #power-domain-cells = <0>;
548 };
549
550 sysc: system-controller@11020000 {
551 compatible = "renesas,r9a07g043-sysc";
552 reg = <0 0x11020000 0 0x10000>;
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 ssi0: ssi@10049c00 {
78 compatible = "renesas,r9a07g043-ssi",
79 "renesas,rz-ssi";
80 reg = <0 0x10049c00 0 0x400>;

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517 #clock-cells = <2>;
518 #reset-cells = <1>;
519 #power-domain-cells = <0>;
520 };
521
522 sysc: system-controller@11020000 {
523 compatible = "renesas,r9a07g043-sysc";
524 reg = <0 0x11020000 0 0x10000>;
553 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
554 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
555 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
556 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "lpm_int", "ca55stbydone_int",
558 "cm33stbyr_int", "ca55_deny";
559 status = "disabled";
560 };
561
562 pinctrl: pinctrl@11030000 {
563 compatible = "renesas,r9a07g043-pinctrl";
564 reg = <0 0x11030000 0 0x10000>;
565 gpio-controller;
566 #gpio-cells = <2>;

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603 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
604 power-domains = <&cpg>;
605 resets = <&cpg R9A07G043_DMAC_ARESETN>,
606 <&cpg R9A07G043_DMAC_RST_ASYNC>;
607 #dma-cells = <1>;
608 dma-channels = <16>;
609 };
610
525 status = "disabled";
526 };
527
528 pinctrl: pinctrl@11030000 {
529 compatible = "renesas,r9a07g043-pinctrl";
530 reg = <0 0x11030000 0 0x10000>;
531 gpio-controller;
532 #gpio-cells = <2>;

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569 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
570 power-domains = <&cpg>;
571 resets = <&cpg R9A07G043_DMAC_ARESETN>,
572 <&cpg R9A07G043_DMAC_RST_ASYNC>;
573 #dma-cells = <1>;
574 dma-channels = <16>;
575 };
576
611 gic: interrupt-controller@11900000 {
612 compatible = "arm,gic-v3";
613 #interrupt-cells = <3>;
614 #address-cells = <0>;
615 interrupt-controller;
616 reg = <0x0 0x11900000 0 0x40000>,
617 <0x0 0x11940000 0 0x60000>;
618 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
619 };
620
621 sdhi0: mmc@11c00000 {
622 compatible = "renesas,sdhi-r9a07g043",
623 "renesas,rcar-gen3-sdhi";
624 reg = <0x0 0x11c00000 0 0x10000>;
625 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
626 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
628 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,

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878 target: trip-point {
879 temperature = <100000>;
880 hysteresis = <1000>;
881 type = "passive";
882 };
883 };
884 };
885 };
577 sdhi0: mmc@11c00000 {
578 compatible = "renesas,sdhi-r9a07g043",
579 "renesas,rcar-gen3-sdhi";
580 reg = <0x0 0x11c00000 0 0x10000>;
581 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
582 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
584 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,

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834 target: trip-point {
835 temperature = <100000>;
836 hysteresis = <1000>;
837 type = "passive";
838 };
839 };
840 };
841 };
886
887 timer {
888 compatible = "arm,armv8-timer";
889 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
890 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
891 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
892 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
893 };
894};
842};