1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r9a07g043-cpg.h> 9 10/ { 11 compatible = "renesas,r9a07g043"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 audio_clk1: audio1-clk { 16 compatible = "fixed-clock"; 17 #clock-cells = <0>; 18 /* This value must be overridden by boards that provide it */ 19 clock-frequency = <0>; 20 }; 21 22 audio_clk2: audio2-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 /* This value must be overridden by boards that provide it */ 26 clock-frequency = <0>; 27 }; 28 29 /* External CAN clock - to be overridden by boards that provide it */ 30 can_clk: can-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 37 extal_clk: extal-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 /* This value must be overridden by the board */ 41 clock-frequency = <0>; 42 }; 43 44 cluster0_opp: opp-table-0 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-125000000 { 49 opp-hz = /bits/ 64 <125000000>; 50 opp-microvolt = <1100000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-250000000 { 54 opp-hz = /bits/ 64 <250000000>; 55 opp-microvolt = <1100000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-500000000 { 59 opp-hz = /bits/ 64 <500000000>; 60 opp-microvolt = <1100000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1000000000 { 64 opp-hz = /bits/ 64 <1000000000>; 65 opp-microvolt = <1100000>; 66 clock-latency-ns = <300000>; 67 opp-suspend; 68 }; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu0: cpu@0 { 76 compatible = "arm,cortex-a55"; 77 reg = <0>; 78 device_type = "cpu"; 79 #cooling-cells = <2>; 80 next-level-cache = <&L3_CA55>; 81 enable-method = "psci"; 82 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 83 operating-points-v2 = <&cluster0_opp>; 84 }; 85 86 L3_CA55: cache-controller-0 { 87 compatible = "cache"; 88 cache-unified; 89 cache-size = <0x40000>; 90 }; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0", "arm,psci-0.2"; 95 method = "smc"; 96 }; 97 98 soc: soc { 99 compatible = "simple-bus"; 100 interrupt-parent = <&gic>; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 ssi0: ssi@10049c00 { 106 compatible = "renesas,r9a07g043-ssi", 107 "renesas,rz-ssi"; 108 reg = <0 0x10049c00 0 0x400>; 109 interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>, 110 <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>, 111 <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>, 112 <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>; 113 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 114 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 115 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 116 <&audio_clk1>, <&audio_clk2>; 117 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 118 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 119 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 120 dma-names = "tx", "rx"; 121 power-domains = <&cpg>; 122 #sound-dai-cells = <0>; 123 status = "disabled"; 124 }; 125 126 ssi1: ssi@1004a000 { 127 compatible = "renesas,r9a07g043-ssi", 128 "renesas,rz-ssi"; 129 reg = <0 0x1004a000 0 0x400>; 130 interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>, 131 <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>, 132 <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>, 133 <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>; 134 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 135 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 136 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 137 <&audio_clk1>, <&audio_clk2>; 138 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 139 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 140 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 141 dma-names = "tx", "rx"; 142 power-domains = <&cpg>; 143 #sound-dai-cells = <0>; 144 status = "disabled"; 145 }; 146 147 ssi2: ssi@1004a400 { 148 compatible = "renesas,r9a07g043-ssi", 149 "renesas,rz-ssi"; 150 reg = <0 0x1004a400 0 0x400>; 151 interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>, 152 <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>, 153 <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>, 154 <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>; 155 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 156 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 157 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 158 <&audio_clk1>, <&audio_clk2>; 159 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 160 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 161 dmas = <&dmac 0x265f>; 162 dma-names = "rt"; 163 power-domains = <&cpg>; 164 #sound-dai-cells = <0>; 165 status = "disabled"; 166 }; 167 168 ssi3: ssi@1004a800 { 169 compatible = "renesas,r9a07g043-ssi", 170 "renesas,rz-ssi"; 171 reg = <0 0x1004a800 0 0x400>; 172 interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>, 173 <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>, 174 <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>, 175 <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>; 176 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 177 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 178 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 179 <&audio_clk1>, <&audio_clk2>; 180 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 181 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 182 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 183 dma-names = "tx", "rx"; 184 power-domains = <&cpg>; 185 #sound-dai-cells = <0>; 186 status = "disabled"; 187 }; 188 189 spi0: spi@1004ac00 { 190 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 191 reg = <0 0x1004ac00 0 0x400>; 192 interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>, 193 <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>, 194 <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>; 195 interrupt-names = "error", "rx", "tx"; 196 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 197 resets = <&cpg R9A07G043_RSPI0_RST>; 198 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 199 dma-names = "tx", "rx"; 200 power-domains = <&cpg>; 201 num-cs = <1>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 status = "disabled"; 205 }; 206 207 spi1: spi@1004b000 { 208 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 209 reg = <0 0x1004b000 0 0x400>; 210 interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>, 211 <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>, 212 <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "error", "rx", "tx"; 214 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 215 resets = <&cpg R9A07G043_RSPI1_RST>; 216 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 217 dma-names = "tx", "rx"; 218 power-domains = <&cpg>; 219 num-cs = <1>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 status = "disabled"; 223 }; 224 225 spi2: spi@1004b400 { 226 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 227 reg = <0 0x1004b400 0 0x400>; 228 interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>, 229 <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>, 230 <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "error", "rx", "tx"; 232 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 233 resets = <&cpg R9A07G043_RSPI2_RST>; 234 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 235 dma-names = "tx", "rx"; 236 power-domains = <&cpg>; 237 num-cs = <1>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 scif0: serial@1004b800 { 244 compatible = "renesas,scif-r9a07g043", 245 "renesas,scif-r9a07g044"; 246 reg = <0 0x1004b800 0 0x400>; 247 interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>, 248 <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>, 249 <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>, 250 <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>, 251 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>, 252 <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-names = "eri", "rxi", "txi", 254 "bri", "dri", "tei"; 255 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 256 clock-names = "fck"; 257 power-domains = <&cpg>; 258 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 259 status = "disabled"; 260 }; 261 262 scif1: serial@1004bc00 { 263 compatible = "renesas,scif-r9a07g043", 264 "renesas,scif-r9a07g044"; 265 reg = <0 0x1004bc00 0 0x400>; 266 interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>, 267 <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>, 268 <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>, 269 <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>, 270 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>, 271 <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "eri", "rxi", "txi", 273 "bri", "dri", "tei"; 274 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 275 clock-names = "fck"; 276 power-domains = <&cpg>; 277 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 278 status = "disabled"; 279 }; 280 281 scif2: serial@1004c000 { 282 compatible = "renesas,scif-r9a07g043", 283 "renesas,scif-r9a07g044"; 284 reg = <0 0x1004c000 0 0x400>; 285 interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>, 286 <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>, 287 <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>, 288 <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>, 289 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>, 290 <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>; 291 interrupt-names = "eri", "rxi", "txi", 292 "bri", "dri", "tei"; 293 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 294 clock-names = "fck"; 295 power-domains = <&cpg>; 296 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 297 status = "disabled"; 298 }; 299 300 scif3: serial@1004c400 { 301 compatible = "renesas,scif-r9a07g043", 302 "renesas,scif-r9a07g044"; 303 reg = <0 0x1004c400 0 0x400>; 304 interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>, 305 <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>, 306 <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>, 307 <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>, 308 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>, 309 <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "eri", "rxi", "txi", 311 "bri", "dri", "tei"; 312 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 313 clock-names = "fck"; 314 power-domains = <&cpg>; 315 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 316 status = "disabled"; 317 }; 318 319 scif4: serial@1004c800 { 320 compatible = "renesas,scif-r9a07g043", 321 "renesas,scif-r9a07g044"; 322 reg = <0 0x1004c800 0 0x400>; 323 interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>, 324 <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>, 325 <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>, 326 <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>, 327 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>, 328 <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>; 329 interrupt-names = "eri", "rxi", "txi", 330 "bri", "dri", "tei"; 331 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 332 clock-names = "fck"; 333 power-domains = <&cpg>; 334 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 335 status = "disabled"; 336 }; 337 338 sci0: serial@1004d000 { 339 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 340 reg = <0 0x1004d000 0 0x400>; 341 interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>, 342 <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>, 343 <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>, 344 <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-names = "eri", "rxi", "txi", "tei"; 346 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 347 clock-names = "fck"; 348 power-domains = <&cpg>; 349 resets = <&cpg R9A07G043_SCI0_RST>; 350 status = "disabled"; 351 }; 352 353 sci1: serial@1004d400 { 354 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 355 reg = <0 0x1004d400 0 0x400>; 356 interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>, 357 <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>, 358 <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>, 359 <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "eri", "rxi", "txi", "tei"; 361 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 362 clock-names = "fck"; 363 power-domains = <&cpg>; 364 resets = <&cpg R9A07G043_SCI1_RST>; 365 status = "disabled"; 366 }; 367 368 canfd: can@10050000 { 369 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 370 reg = <0 0x10050000 0 0x8000>; 371 interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>, 372 <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>, 373 <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>, 374 <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>, 375 <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>, 376 <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>, 377 <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>, 378 <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>; 379 interrupt-names = "g_err", "g_recc", 380 "ch0_err", "ch0_rec", "ch0_trx", 381 "ch1_err", "ch1_rec", "ch1_trx"; 382 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 383 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 384 <&can_clk>; 385 clock-names = "fck", "canfd", "can_clk"; 386 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 387 assigned-clock-rates = <50000000>; 388 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 389 <&cpg R9A07G043_CANFD_RSTC_N>; 390 reset-names = "rstp_n", "rstc_n"; 391 power-domains = <&cpg>; 392 status = "disabled"; 393 394 channel0 { 395 status = "disabled"; 396 }; 397 channel1 { 398 status = "disabled"; 399 }; 400 }; 401 402 i2c0: i2c@10058000 { 403 #address-cells = <1>; 404 #size-cells = <0>; 405 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 406 reg = <0 0x10058000 0 0x400>; 407 interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>, 408 <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>, 409 <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>, 410 <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>, 411 <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>, 412 <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>, 413 <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>, 414 <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "tei", "ri", "ti", "spi", "sti", 416 "naki", "ali", "tmoi"; 417 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 418 clock-frequency = <100000>; 419 resets = <&cpg R9A07G043_I2C0_MRST>; 420 power-domains = <&cpg>; 421 status = "disabled"; 422 }; 423 424 i2c1: i2c@10058400 { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 428 reg = <0 0x10058400 0 0x400>; 429 interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>, 430 <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>, 431 <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>, 432 <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>, 433 <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>, 434 <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>, 435 <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>, 436 <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>; 437 interrupt-names = "tei", "ri", "ti", "spi", "sti", 438 "naki", "ali", "tmoi"; 439 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 440 clock-frequency = <100000>; 441 resets = <&cpg R9A07G043_I2C1_MRST>; 442 power-domains = <&cpg>; 443 status = "disabled"; 444 }; 445 446 i2c2: i2c@10058800 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 450 reg = <0 0x10058800 0 0x400>; 451 interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>, 452 <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>, 453 <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>, 454 <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>, 455 <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>, 456 <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>, 457 <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>, 458 <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>; 459 interrupt-names = "tei", "ri", "ti", "spi", "sti", 460 "naki", "ali", "tmoi"; 461 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 462 clock-frequency = <100000>; 463 resets = <&cpg R9A07G043_I2C2_MRST>; 464 power-domains = <&cpg>; 465 status = "disabled"; 466 }; 467 468 i2c3: i2c@10058c00 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 472 reg = <0 0x10058c00 0 0x400>; 473 interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>, 474 <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>, 475 <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>, 476 <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>, 477 <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>, 478 <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>, 479 <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>, 480 <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "tei", "ri", "ti", "spi", "sti", 482 "naki", "ali", "tmoi"; 483 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 484 clock-frequency = <100000>; 485 resets = <&cpg R9A07G043_I2C3_MRST>; 486 power-domains = <&cpg>; 487 status = "disabled"; 488 }; 489 490 adc: adc@10059000 { 491 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; 492 reg = <0 0x10059000 0 0x400>; 493 interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>; 494 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, 495 <&cpg CPG_MOD R9A07G043_ADC_PCLK>; 496 clock-names = "adclk", "pclk"; 497 resets = <&cpg R9A07G043_ADC_PRESETN>, 498 <&cpg R9A07G043_ADC_ADRST_N>; 499 reset-names = "presetn", "adrst-n"; 500 power-domains = <&cpg>; 501 status = "disabled"; 502 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 channel@0 { 507 reg = <0>; 508 }; 509 channel@1 { 510 reg = <1>; 511 }; 512 }; 513 514 tsu: thermal@10059400 { 515 compatible = "renesas,r9a07g043-tsu", 516 "renesas,rzg2l-tsu"; 517 reg = <0 0x10059400 0 0x400>; 518 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; 519 resets = <&cpg R9A07G043_TSU_PRESETN>; 520 power-domains = <&cpg>; 521 #thermal-sensor-cells = <1>; 522 }; 523 524 sbc: spi@10060000 { 525 compatible = "renesas,r9a07g043-rpc-if", 526 "renesas,rzg2l-rpc-if"; 527 reg = <0 0x10060000 0 0x10000>, 528 <0 0x20000000 0 0x10000000>, 529 <0 0x10070000 0 0x10000>; 530 reg-names = "regs", "dirmap", "wbuf"; 531 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, 532 <&cpg CPG_MOD R9A07G043_SPI_CLK>; 533 resets = <&cpg R9A07G043_SPI_RST>; 534 power-domains = <&cpg>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 cpg: clock-controller@11010000 { 541 compatible = "renesas,r9a07g043-cpg"; 542 reg = <0 0x11010000 0 0x10000>; 543 clocks = <&extal_clk>; 544 clock-names = "extal"; 545 #clock-cells = <2>; 546 #reset-cells = <1>; 547 #power-domain-cells = <0>; 548 }; 549 550 sysc: system-controller@11020000 { 551 compatible = "renesas,r9a07g043-sysc"; 552 reg = <0 0x11020000 0 0x10000>; 553 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, 554 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, 555 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, 556 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "lpm_int", "ca55stbydone_int", 558 "cm33stbyr_int", "ca55_deny"; 559 status = "disabled"; 560 }; 561 562 pinctrl: pinctrl@11030000 { 563 compatible = "renesas,r9a07g043-pinctrl"; 564 reg = <0 0x11030000 0 0x10000>; 565 gpio-controller; 566 #gpio-cells = <2>; 567 gpio-ranges = <&pinctrl 0 0 152>; 568 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 569 power-domains = <&cpg>; 570 resets = <&cpg R9A07G043_GPIO_RSTN>, 571 <&cpg R9A07G043_GPIO_PORT_RESETN>, 572 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 573 }; 574 575 dmac: dma-controller@11820000 { 576 compatible = "renesas,r9a07g043-dmac", 577 "renesas,rz-dmac"; 578 reg = <0 0x11820000 0 0x10000>, 579 <0 0x11830000 0 0x10000>; 580 interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>, 581 <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>, 582 <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>, 583 <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>, 584 <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>, 585 <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>, 586 <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>, 587 <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>, 588 <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>, 589 <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>, 590 <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>, 591 <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>, 592 <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>, 593 <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>, 594 <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>, 595 <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>, 596 <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>; 597 interrupt-names = "error", 598 "ch0", "ch1", "ch2", "ch3", 599 "ch4", "ch5", "ch6", "ch7", 600 "ch8", "ch9", "ch10", "ch11", 601 "ch12", "ch13", "ch14", "ch15"; 602 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 603 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 604 power-domains = <&cpg>; 605 resets = <&cpg R9A07G043_DMAC_ARESETN>, 606 <&cpg R9A07G043_DMAC_RST_ASYNC>; 607 #dma-cells = <1>; 608 dma-channels = <16>; 609 }; 610 611 gic: interrupt-controller@11900000 { 612 compatible = "arm,gic-v3"; 613 #interrupt-cells = <3>; 614 #address-cells = <0>; 615 interrupt-controller; 616 reg = <0x0 0x11900000 0 0x40000>, 617 <0x0 0x11940000 0 0x60000>; 618 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 619 }; 620 621 sdhi0: mmc@11c00000 { 622 compatible = "renesas,sdhi-r9a07g043", 623 "renesas,rcar-gen3-sdhi"; 624 reg = <0x0 0x11c00000 0 0x10000>; 625 interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>, 626 <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 628 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 629 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 630 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 631 clock-names = "core", "clkh", "cd", "aclk"; 632 resets = <&cpg R9A07G043_SDHI0_IXRST>; 633 power-domains = <&cpg>; 634 status = "disabled"; 635 }; 636 637 sdhi1: mmc@11c10000 { 638 compatible = "renesas,sdhi-r9a07g043", 639 "renesas,rcar-gen3-sdhi"; 640 reg = <0x0 0x11c10000 0 0x10000>; 641 interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>, 642 <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 644 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 645 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 646 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 647 clock-names = "core", "clkh", "cd", "aclk"; 648 resets = <&cpg R9A07G043_SDHI1_IXRST>; 649 power-domains = <&cpg>; 650 status = "disabled"; 651 }; 652 653 eth0: ethernet@11c20000 { 654 compatible = "renesas,r9a07g043-gbeth", 655 "renesas,rzg2l-gbeth"; 656 reg = <0 0x11c20000 0 0x10000>; 657 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>, 658 <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>, 659 <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>; 660 interrupt-names = "mux", "fil", "arp_ns"; 661 phy-mode = "rgmii"; 662 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 663 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 664 <&cpg CPG_CORE R9A07G043_CLK_HP>; 665 clock-names = "axi", "chi", "refclk"; 666 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 667 power-domains = <&cpg>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 673 eth1: ethernet@11c30000 { 674 compatible = "renesas,r9a07g043-gbeth", 675 "renesas,rzg2l-gbeth"; 676 reg = <0 0x11c30000 0 0x10000>; 677 interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>, 678 <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>, 679 <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "mux", "fil", "arp_ns"; 681 phy-mode = "rgmii"; 682 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 683 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 684 <&cpg CPG_CORE R9A07G043_CLK_HP>; 685 clock-names = "axi", "chi", "refclk"; 686 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 687 power-domains = <&cpg>; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 status = "disabled"; 691 }; 692 693 phyrst: usbphy-ctrl@11c40000 { 694 compatible = "renesas,r9a07g043-usbphy-ctrl", 695 "renesas,rzg2l-usbphy-ctrl"; 696 reg = <0 0x11c40000 0 0x10000>; 697 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 698 resets = <&cpg R9A07G043_USB_PRESETN>; 699 power-domains = <&cpg>; 700 #reset-cells = <1>; 701 status = "disabled"; 702 }; 703 704 ohci0: usb@11c50000 { 705 compatible = "generic-ohci"; 706 reg = <0 0x11c50000 0 0x100>; 707 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 709 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 710 resets = <&phyrst 0>, 711 <&cpg R9A07G043_USB_U2H0_HRESETN>; 712 phys = <&usb2_phy0 1>; 713 phy-names = "usb"; 714 power-domains = <&cpg>; 715 status = "disabled"; 716 }; 717 718 ohci1: usb@11c70000 { 719 compatible = "generic-ohci"; 720 reg = <0 0x11c70000 0 0x100>; 721 interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 723 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 724 resets = <&phyrst 1>, 725 <&cpg R9A07G043_USB_U2H1_HRESETN>; 726 phys = <&usb2_phy1 1>; 727 phy-names = "usb"; 728 power-domains = <&cpg>; 729 status = "disabled"; 730 }; 731 732 ehci0: usb@11c50100 { 733 compatible = "generic-ehci"; 734 reg = <0 0x11c50100 0 0x100>; 735 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 737 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 738 resets = <&phyrst 0>, 739 <&cpg R9A07G043_USB_U2H0_HRESETN>; 740 phys = <&usb2_phy0 2>; 741 phy-names = "usb"; 742 companion = <&ohci0>; 743 power-domains = <&cpg>; 744 status = "disabled"; 745 }; 746 747 ehci1: usb@11c70100 { 748 compatible = "generic-ehci"; 749 reg = <0 0x11c70100 0 0x100>; 750 interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 752 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 753 resets = <&phyrst 1>, 754 <&cpg R9A07G043_USB_U2H1_HRESETN>; 755 phys = <&usb2_phy1 2>; 756 phy-names = "usb"; 757 companion = <&ohci1>; 758 power-domains = <&cpg>; 759 status = "disabled"; 760 }; 761 762 usb2_phy0: usb-phy@11c50200 { 763 compatible = "renesas,usb2-phy-r9a07g043", 764 "renesas,rzg2l-usb2-phy"; 765 reg = <0 0x11c50200 0 0x700>; 766 interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 768 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 769 resets = <&phyrst 0>; 770 #phy-cells = <1>; 771 power-domains = <&cpg>; 772 status = "disabled"; 773 }; 774 775 usb2_phy1: usb-phy@11c70200 { 776 compatible = "renesas,usb2-phy-r9a07g043", 777 "renesas,rzg2l-usb2-phy"; 778 reg = <0 0x11c70200 0 0x700>; 779 interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 781 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 782 resets = <&phyrst 1>; 783 #phy-cells = <1>; 784 power-domains = <&cpg>; 785 status = "disabled"; 786 }; 787 788 hsusb: usb@11c60000 { 789 compatible = "renesas,usbhs-r9a07g043", 790 "renesas,rza2-usbhs"; 791 reg = <0 0x11c60000 0 0x10000>; 792 interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>, 793 <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>, 794 <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>, 795 <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 797 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 798 resets = <&phyrst 0>, 799 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 800 renesas,buswait = <7>; 801 phys = <&usb2_phy0 3>; 802 phy-names = "usb"; 803 power-domains = <&cpg>; 804 status = "disabled"; 805 }; 806 807 wdt0: watchdog@12800800 { 808 compatible = "renesas,r9a07g043-wdt", 809 "renesas,rzg2l-wdt"; 810 reg = <0 0x12800800 0 0x400>; 811 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 812 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 813 clock-names = "pclk", "oscclk"; 814 interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>, 815 <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "wdt", "perrout"; 817 resets = <&cpg R9A07G043_WDT0_PRESETN>; 818 power-domains = <&cpg>; 819 status = "disabled"; 820 }; 821 822 ostm0: timer@12801000 { 823 compatible = "renesas,r9a07g043-ostm", 824 "renesas,ostm"; 825 reg = <0x0 0x12801000 0x0 0x400>; 826 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>; 827 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 828 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 829 power-domains = <&cpg>; 830 status = "disabled"; 831 }; 832 833 ostm1: timer@12801400 { 834 compatible = "renesas,r9a07g043-ostm", 835 "renesas,ostm"; 836 reg = <0x0 0x12801400 0x0 0x400>; 837 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>; 838 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 839 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 840 power-domains = <&cpg>; 841 status = "disabled"; 842 }; 843 844 ostm2: timer@12801800 { 845 compatible = "renesas,r9a07g043-ostm", 846 "renesas,ostm"; 847 reg = <0x0 0x12801800 0x0 0x400>; 848 interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>; 849 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 850 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 851 power-domains = <&cpg>; 852 status = "disabled"; 853 }; 854 }; 855 856 thermal-zones { 857 cpu-thermal { 858 polling-delay-passive = <250>; 859 polling-delay = <1000>; 860 thermal-sensors = <&tsu 0>; 861 sustainable-power = <717>; 862 863 cooling-maps { 864 map0 { 865 trip = <&target>; 866 cooling-device = <&cpu0 0 2>; 867 contribution = <1024>; 868 }; 869 }; 870 871 trips { 872 sensor_crit: sensor-crit { 873 temperature = <125000>; 874 hysteresis = <1000>; 875 type = "critical"; 876 }; 877 878 target: trip-point { 879 temperature = <100000>; 880 hysteresis = <1000>; 881 type = "passive"; 882 }; 883 }; 884 }; 885 }; 886 887 timer { 888 compatible = "arm,armv8-timer"; 889 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 890 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 891 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 892 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 893 }; 894}; 895