r9a07g043.dtsi (20e63d3948985672b9e8efa98ff3643d91378e84) r9a07g043.dtsi (13ea8b3584c09f0ab94d5447ff2965d255329a88)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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360 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
361 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
362 clock-names = "core", "clkh", "cd", "aclk";
363 resets = <&cpg R9A07G043_SDHI1_IXRST>;
364 power-domains = <&cpg>;
365 status = "disabled";
366 };
367
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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360 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
361 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
362 clock-names = "core", "clkh", "cd", "aclk";
363 resets = <&cpg R9A07G043_SDHI1_IXRST>;
364 power-domains = <&cpg>;
365 status = "disabled";
366 };
367
368 eth0: ethernet@11c20000 {
369 compatible = "renesas,r9a07g043-gbeth",
370 "renesas,rzg2l-gbeth";
371 reg = <0 0x11c20000 0 0x10000>;
372 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "mux", "fil", "arp_ns";
376 phy-mode = "rgmii";
377 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
378 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
379 <&cpg CPG_CORE R9A07G043_CLK_HP>;
380 clock-names = "axi", "chi", "refclk";
381 resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
382 power-domains = <&cpg>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 status = "disabled";
386 };
387
388 eth1: ethernet@11c30000 {
389 compatible = "renesas,r9a07g043-gbeth",
390 "renesas,rzg2l-gbeth";
391 reg = <0 0x11c30000 0 0x10000>;
392 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-names = "mux", "fil", "arp_ns";
396 phy-mode = "rgmii";
397 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
398 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
399 <&cpg CPG_CORE R9A07G043_CLK_HP>;
400 clock-names = "axi", "chi", "refclk";
401 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
402 power-domains = <&cpg>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 };
407
368 phyrst: usbphy-ctrl@11c40000 {
369 reg = <0 0x11c40000 0 0x10000>;
370 /* place holder */
371 };
372
373 ohci0: usb@11c50000 {
374 reg = <0 0x11c50000 0 0x100>;
375 /* place holder */

--- 66 unchanged lines hidden --- 		408 phyrst: usbphy-ctrl@11c40000 {
409 reg = <0 0x11c40000 0 0x10000>;
410 /* place holder */
411 };
412
413 ohci0: usb@11c50000 {
414 reg = <0 0x11c50000 0 0x100>;
415 /* place holder */

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