1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio-clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio-clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a55"; 51 reg = <0>; 52 device_type = "cpu"; 53 next-level-cache = <&L3_CA55>; 54 enable-method = "psci"; 55 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 56 }; 57 58 L3_CA55: cache-controller-0 { 59 compatible = "cache"; 60 cache-unified; 61 cache-size = <0x40000>; 62 }; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0", "arm,psci-0.2"; 67 method = "smc"; 68 }; 69 70 soc: soc { 71 compatible = "simple-bus"; 72 interrupt-parent = <&gic>; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 ssi0: ssi@10049c00 { 78 reg = <0 0x10049c00 0 0x400>; 79 #sound-dai-cells = <0>; 80 /* place holder */ 81 }; 82 83 spi1: spi@1004b000 { 84 reg = <0 0x1004b000 0 0x400>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 /* place holder */ 88 }; 89 90 scif0: serial@1004b800 { 91 compatible = "renesas,scif-r9a07g043", 92 "renesas,scif-r9a07g044"; 93 reg = <0 0x1004b800 0 0x400>; 94 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 100 interrupt-names = "eri", "rxi", "txi", 101 "bri", "dri", "tei"; 102 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 103 clock-names = "fck"; 104 power-domains = <&cpg>; 105 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 106 status = "disabled"; 107 }; 108 109 scif1: serial@1004bc00 { 110 compatible = "renesas,scif-r9a07g043", 111 "renesas,scif-r9a07g044"; 112 reg = <0 0x1004bc00 0 0x400>; 113 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-names = "eri", "rxi", "txi", 120 "bri", "dri", "tei"; 121 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 122 clock-names = "fck"; 123 power-domains = <&cpg>; 124 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 125 status = "disabled"; 126 }; 127 128 scif2: serial@1004c000 { 129 compatible = "renesas,scif-r9a07g043", 130 "renesas,scif-r9a07g044"; 131 reg = <0 0x1004c000 0 0x400>; 132 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-names = "eri", "rxi", "txi", 139 "bri", "dri", "tei"; 140 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 141 clock-names = "fck"; 142 power-domains = <&cpg>; 143 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 144 status = "disabled"; 145 }; 146 147 scif3: serial@1004c400 { 148 compatible = "renesas,scif-r9a07g043", 149 "renesas,scif-r9a07g044"; 150 reg = <0 0x1004c400 0 0x400>; 151 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 157 interrupt-names = "eri", "rxi", "txi", 158 "bri", "dri", "tei"; 159 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 160 clock-names = "fck"; 161 power-domains = <&cpg>; 162 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 163 status = "disabled"; 164 }; 165 166 scif4: serial@1004c800 { 167 compatible = "renesas,scif-r9a07g043", 168 "renesas,scif-r9a07g044"; 169 reg = <0 0x1004c800 0 0x400>; 170 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "eri", "rxi", "txi", 177 "bri", "dri", "tei"; 178 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 179 clock-names = "fck"; 180 power-domains = <&cpg>; 181 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 182 status = "disabled"; 183 }; 184 185 sci0: serial@1004d000 { 186 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 187 reg = <0 0x1004d000 0 0x400>; 188 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 192 interrupt-names = "eri", "rxi", "txi", "tei"; 193 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 194 clock-names = "fck"; 195 power-domains = <&cpg>; 196 resets = <&cpg R9A07G043_SCI0_RST>; 197 status = "disabled"; 198 }; 199 200 sci1: serial@1004d400 { 201 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 202 reg = <0 0x1004d400 0 0x400>; 203 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 207 interrupt-names = "eri", "rxi", "txi", "tei"; 208 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 209 clock-names = "fck"; 210 power-domains = <&cpg>; 211 resets = <&cpg R9A07G043_SCI1_RST>; 212 status = "disabled"; 213 }; 214 215 canfd: can@10050000 { 216 reg = <0 0x10050000 0 0x8000>; 217 /* place holder */ 218 }; 219 220 i2c0: i2c@10058000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 reg = <0 0x10058000 0 0x400>; 224 /* place holder */ 225 }; 226 227 i2c1: i2c@10058400 { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 reg = <0 0x10058400 0 0x400>; 231 /* place holder */ 232 }; 233 234 i2c3: i2c@10058c00 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 reg = <0 0x10058c00 0 0x400>; 238 /* place holder */ 239 }; 240 241 adc: adc@10059000 { 242 reg = <0 0x10059000 0 0x400>; 243 /* place holder */ 244 }; 245 246 sbc: spi@10060000 { 247 reg = <0 0x10060000 0 0x10000>, 248 <0 0x20000000 0 0x10000000>, 249 <0 0x10070000 0 0x10000>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 /* place holder */ 253 }; 254 255 cpg: clock-controller@11010000 { 256 compatible = "renesas,r9a07g043-cpg"; 257 reg = <0 0x11010000 0 0x10000>; 258 clocks = <&extal_clk>; 259 clock-names = "extal"; 260 #clock-cells = <2>; 261 #reset-cells = <1>; 262 #power-domain-cells = <0>; 263 }; 264 265 sysc: system-controller@11020000 { 266 compatible = "renesas,r9a07g043-sysc"; 267 reg = <0 0x11020000 0 0x10000>; 268 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "lpm_int", "ca55stbydone_int", 273 "cm33stbyr_int", "ca55_deny"; 274 status = "disabled"; 275 }; 276 277 pinctrl: pinctrl@11030000 { 278 compatible = "renesas,r9a07g043-pinctrl"; 279 reg = <0 0x11030000 0 0x10000>; 280 gpio-controller; 281 #gpio-cells = <2>; 282 gpio-ranges = <&pinctrl 0 0 152>; 283 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 284 power-domains = <&cpg>; 285 resets = <&cpg R9A07G043_GPIO_RSTN>, 286 <&cpg R9A07G043_GPIO_PORT_RESETN>, 287 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 288 }; 289 290 dmac: dma-controller@11820000 { 291 compatible = "renesas,r9a07g043-dmac", 292 "renesas,rz-dmac"; 293 reg = <0 0x11820000 0 0x10000>, 294 <0 0x11830000 0 0x10000>; 295 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 312 interrupt-names = "error", 313 "ch0", "ch1", "ch2", "ch3", 314 "ch4", "ch5", "ch6", "ch7", 315 "ch8", "ch9", "ch10", "ch11", 316 "ch12", "ch13", "ch14", "ch15"; 317 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 318 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 319 power-domains = <&cpg>; 320 resets = <&cpg R9A07G043_DMAC_ARESETN>, 321 <&cpg R9A07G043_DMAC_RST_ASYNC>; 322 #dma-cells = <1>; 323 dma-channels = <16>; 324 }; 325 326 gic: interrupt-controller@11900000 { 327 compatible = "arm,gic-v3"; 328 #interrupt-cells = <3>; 329 #address-cells = <0>; 330 interrupt-controller; 331 reg = <0x0 0x11900000 0 0x40000>, 332 <0x0 0x11940000 0 0x60000>; 333 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 334 }; 335 336 sdhi0: mmc@11c00000 { 337 compatible = "renesas,sdhi-r9a07g043", 338 "renesas,rcar-gen3-sdhi"; 339 reg = <0x0 0x11c00000 0 0x10000>; 340 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 343 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 344 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 345 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 346 clock-names = "core", "clkh", "cd", "aclk"; 347 resets = <&cpg R9A07G043_SDHI0_IXRST>; 348 power-domains = <&cpg>; 349 status = "disabled"; 350 }; 351 352 sdhi1: mmc@11c10000 { 353 compatible = "renesas,sdhi-r9a07g043", 354 "renesas,rcar-gen3-sdhi"; 355 reg = <0x0 0x11c10000 0 0x10000>; 356 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 359 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 360 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 361 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 362 clock-names = "core", "clkh", "cd", "aclk"; 363 resets = <&cpg R9A07G043_SDHI1_IXRST>; 364 power-domains = <&cpg>; 365 status = "disabled"; 366 }; 367 368 phyrst: usbphy-ctrl@11c40000 { 369 reg = <0 0x11c40000 0 0x10000>; 370 /* place holder */ 371 }; 372 373 ohci0: usb@11c50000 { 374 reg = <0 0x11c50000 0 0x100>; 375 /* place holder */ 376 }; 377 378 ohci1: usb@11c70000 { 379 reg = <0 0x11c70000 0 0x100>; 380 /* place holder */ 381 }; 382 383 ehci0: usb@11c50100 { 384 reg = <0 0x11c50100 0 0x100>; 385 /* place holder */ 386 }; 387 388 ehci1: usb@11c70100 { 389 reg = <0 0x11c70100 0 0x100>; 390 /* place holder */ 391 }; 392 393 usb2_phy0: usb-phy@11c50200 { 394 reg = <0 0x11c50200 0 0x700>; 395 /* place holder */ 396 }; 397 398 usb2_phy1: usb-phy@11c70200 { 399 reg = <0 0x11c70200 0 0x700>; 400 /* place holder */ 401 }; 402 403 hsusb: usb@11c60000 { 404 reg = <0 0x11c60000 0 0x10000>; 405 /* place holder */ 406 }; 407 408 wdt0: watchdog@12800800 { 409 reg = <0 0x12800800 0 0x400>; 410 /* place holder */ 411 }; 412 413 wdt2: watchdog@12800400 { 414 reg = <0 0x12800400 0 0x400>; 415 /* place holder */ 416 }; 417 418 ostm0: timer@12801000 { 419 reg = <0x0 0x12801000 0x0 0x400>; 420 /* place holder */ 421 }; 422 423 ostm1: timer@12801400 { 424 reg = <0x0 0x12801400 0x0 0x400>; 425 /* place holder */ 426 }; 427 428 ostm2: timer@12801800 { 429 reg = <0x0 0x12801800 0x0 0x400>; 430 /* place holder */ 431 }; 432 }; 433 434 timer { 435 compatible = "arm,armv8-timer"; 436 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 437 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 438 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 439 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 440 }; 441}; 442