r8a77990.dtsi (ec70407ae7d790d6b34bfe582901c1149e842248) r8a77990.dtsi (bc011dfa30652380bf432fd52441077b52b4eadc)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a77990-sysc.h>
11
12/ {
13 compatible = "renesas,r8a77990";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a77990-sysc.h>
11
12/ {
13 compatible = "renesas,r8a77990";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 i2c6 = &i2c6;
25 i2c7 = &i2c7;
26 };
27
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 a53_0: cpu@0 {
22 compatible = "arm,cortex-a53", "arm,armv8";
23 reg = <0>;
24 device_type = "cpu";

--- 162 unchanged lines hidden (view full) ---

187 gpio-ranges = <&pfc 0 192 18>;
188 #interrupt-cells = <2>;
189 interrupt-controller;
190 clocks = <&cpg CPG_MOD 906>;
191 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
192 resets = <&cpg 906>;
193 };
194
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 a53_0: cpu@0 {
33 compatible = "arm,cortex-a53", "arm,armv8";
34 reg = <0>;
35 device_type = "cpu";

--- 162 unchanged lines hidden (view full) ---

198 gpio-ranges = <&pfc 0 192 18>;
199 #interrupt-cells = <2>;
200 interrupt-controller;
201 clocks = <&cpg CPG_MOD 906>;
202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
203 resets = <&cpg 906>;
204 };
205
206 i2c0: i2c@e6500000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,i2c-r8a77990",
210 "renesas,rcar-gen3-i2c";
211 reg = <0 0xe6500000 0 0x40>;
212 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cpg CPG_MOD 931>;
214 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
215 resets = <&cpg 931>;
216 i2c-scl-internal-delay-ns = <110>;
217 status = "disabled";
218 };
219
220 i2c1: i2c@e6508000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "renesas,i2c-r8a77990",
224 "renesas,rcar-gen3-i2c";
225 reg = <0 0xe6508000 0 0x40>;
226 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cpg CPG_MOD 930>;
228 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
229 resets = <&cpg 930>;
230 i2c-scl-internal-delay-ns = <6>;
231 status = "disabled";
232 };
233
234 i2c2: i2c@e6510000 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 compatible = "renesas,i2c-r8a77990",
238 "renesas,rcar-gen3-i2c";
239 reg = <0 0xe6510000 0 0x40>;
240 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cpg CPG_MOD 929>;
242 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
243 resets = <&cpg 929>;
244 i2c-scl-internal-delay-ns = <6>;
245 status = "disabled";
246 };
247
248 i2c3: i2c@e66d0000 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "renesas,i2c-r8a77990",
252 "renesas,rcar-gen3-i2c";
253 reg = <0 0xe66d0000 0 0x40>;
254 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cpg CPG_MOD 928>;
256 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
257 resets = <&cpg 928>;
258 i2c-scl-internal-delay-ns = <110>;
259 status = "disabled";
260 };
261
262 i2c4: i2c@e66d8000 {
263 #address-cells = <1>;
264 #size-cells = <0>;
265 compatible = "renesas,i2c-r8a77990",
266 "renesas,rcar-gen3-i2c";
267 reg = <0 0xe66d8000 0 0x40>;
268 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 927>;
270 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
271 resets = <&cpg 927>;
272 i2c-scl-internal-delay-ns = <6>;
273 status = "disabled";
274 };
275
276 i2c5: i2c@e66e0000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "renesas,i2c-r8a77990",
280 "renesas,rcar-gen3-i2c";
281 reg = <0 0xe66e0000 0 0x40>;
282 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&cpg CPG_MOD 919>;
284 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
285 resets = <&cpg 919>;
286 i2c-scl-internal-delay-ns = <6>;
287 status = "disabled";
288 };
289
290 i2c6: i2c@e66e8000 {
291 #address-cells = <1>;
292 #size-cells = <0>;
293 compatible = "renesas,i2c-r8a77990",
294 "renesas,rcar-gen3-i2c";
295 reg = <0 0xe66e8000 0 0x40>;
296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cpg CPG_MOD 918>;
298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
299 resets = <&cpg 918>;
300 i2c-scl-internal-delay-ns = <6>;
301 status = "disabled";
302 };
303
304 i2c7: i2c@e6690000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "renesas,i2c-r8a77990",
308 "renesas,rcar-gen3-i2c";
309 reg = <0 0xe6690000 0 0x40>;
310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cpg CPG_MOD 1003>;
312 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
313 resets = <&cpg 1003>;
314 i2c-scl-internal-delay-ns = <6>;
315 status = "disabled";
316 };
317
195 pfc: pin-controller@e6060000 {
196 compatible = "renesas,pfc-r8a77990";
197 reg = <0 0xe6060000 0 0x508>;
198 };
199
200 cpg: clock-controller@e6150000 {
201 compatible = "renesas,r8a77990-cpg-mssr";
202 reg = <0 0xe6150000 0 0x1000>;

--- 439 unchanged lines hidden --- 		318 pfc: pin-controller@e6060000 {
319 compatible = "renesas,pfc-r8a77990";
320 reg = <0 0xe6060000 0 0x508>;
321 };
322
323 cpg: clock-controller@e6150000 {
324 compatible = "renesas,r8a77990-cpg-mssr";
325 reg = <0 0xe6150000 0 0x1000>;

--- 439 unchanged lines hidden ---