1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77990-sysc.h> 11 12/ { 13 compatible = "renesas,r8a77990"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 i2c7 = &i2c7; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 reg = <0>; 35 device_type = "cpu"; 36 power-domains = <&sysc R8A77990_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 a53_1: cpu@1 { 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <1>; 44 device_type = "cpu"; 45 power-domains = <&sysc R8A77990_PD_CA53_CPU1>; 46 next-level-cache = <&L2_CA53>; 47 enable-method = "psci"; 48 }; 49 50 L2_CA53: cache-controller-0 { 51 compatible = "cache"; 52 power-domains = <&sysc R8A77990_PD_CA53_SCU>; 53 cache-unified; 54 cache-level = <2>; 55 }; 56 }; 57 58 extal_clk: extal { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 /* This value must be overridden by the board */ 62 clock-frequency = <0>; 63 }; 64 65 pmu_a53 { 66 compatible = "arm,cortex-a53-pmu"; 67 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 68 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&a53_0>, <&a53_1>; 70 }; 71 72 psci { 73 compatible = "arm,psci-1.0", "arm,psci-0.2"; 74 method = "smc"; 75 }; 76 77 /* External SCIF clock - to be overridden by boards that provide it */ 78 scif_clk: scif { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <0>; 82 }; 83 84 soc: soc { 85 compatible = "simple-bus"; 86 interrupt-parent = <&gic>; 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 rwdt: watchdog@e6020000 { 92 compatible = "renesas,r8a77990-wdt", 93 "renesas,rcar-gen3-wdt"; 94 reg = <0 0xe6020000 0 0x0c>; 95 clocks = <&cpg CPG_MOD 402>; 96 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 97 resets = <&cpg 402>; 98 status = "disabled"; 99 }; 100 101 gpio0: gpio@e6050000 { 102 compatible = "renesas,gpio-r8a77990", 103 "renesas,rcar-gen3-gpio"; 104 reg = <0 0xe6050000 0 0x50>; 105 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 106 #gpio-cells = <2>; 107 gpio-controller; 108 gpio-ranges = <&pfc 0 0 18>; 109 #interrupt-cells = <2>; 110 interrupt-controller; 111 clocks = <&cpg CPG_MOD 912>; 112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 113 resets = <&cpg 912>; 114 }; 115 116 gpio1: gpio@e6051000 { 117 compatible = "renesas,gpio-r8a77990", 118 "renesas,rcar-gen3-gpio"; 119 reg = <0 0xe6051000 0 0x50>; 120 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 121 #gpio-cells = <2>; 122 gpio-controller; 123 gpio-ranges = <&pfc 0 32 23>; 124 #interrupt-cells = <2>; 125 interrupt-controller; 126 clocks = <&cpg CPG_MOD 911>; 127 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 128 resets = <&cpg 911>; 129 }; 130 131 gpio2: gpio@e6052000 { 132 compatible = "renesas,gpio-r8a77990", 133 "renesas,rcar-gen3-gpio"; 134 reg = <0 0xe6052000 0 0x50>; 135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 136 #gpio-cells = <2>; 137 gpio-controller; 138 gpio-ranges = <&pfc 0 64 26>; 139 #interrupt-cells = <2>; 140 interrupt-controller; 141 clocks = <&cpg CPG_MOD 910>; 142 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 143 resets = <&cpg 910>; 144 }; 145 146 gpio3: gpio@e6053000 { 147 compatible = "renesas,gpio-r8a77990", 148 "renesas,rcar-gen3-gpio"; 149 reg = <0 0xe6053000 0 0x50>; 150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 96 16>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&cpg CPG_MOD 909>; 157 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 158 resets = <&cpg 909>; 159 }; 160 161 gpio4: gpio@e6054000 { 162 compatible = "renesas,gpio-r8a77990", 163 "renesas,rcar-gen3-gpio"; 164 reg = <0 0xe6054000 0 0x50>; 165 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 128 11>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&cpg CPG_MOD 908>; 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 173 resets = <&cpg 908>; 174 }; 175 176 gpio5: gpio@e6055000 { 177 compatible = "renesas,gpio-r8a77990", 178 "renesas,rcar-gen3-gpio"; 179 reg = <0 0xe6055000 0 0x50>; 180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 181 #gpio-cells = <2>; 182 gpio-controller; 183 gpio-ranges = <&pfc 0 160 20>; 184 #interrupt-cells = <2>; 185 interrupt-controller; 186 clocks = <&cpg CPG_MOD 907>; 187 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 188 resets = <&cpg 907>; 189 }; 190 191 gpio6: gpio@e6055400 { 192 compatible = "renesas,gpio-r8a77990", 193 "renesas,rcar-gen3-gpio"; 194 reg = <0 0xe6055400 0 0x50>; 195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 196 #gpio-cells = <2>; 197 gpio-controller; 198 gpio-ranges = <&pfc 0 192 18>; 199 #interrupt-cells = <2>; 200 interrupt-controller; 201 clocks = <&cpg CPG_MOD 906>; 202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 203 resets = <&cpg 906>; 204 }; 205 206 i2c0: i2c@e6500000 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 compatible = "renesas,i2c-r8a77990", 210 "renesas,rcar-gen3-i2c"; 211 reg = <0 0xe6500000 0 0x40>; 212 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cpg CPG_MOD 931>; 214 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 215 resets = <&cpg 931>; 216 i2c-scl-internal-delay-ns = <110>; 217 status = "disabled"; 218 }; 219 220 i2c1: i2c@e6508000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "renesas,i2c-r8a77990", 224 "renesas,rcar-gen3-i2c"; 225 reg = <0 0xe6508000 0 0x40>; 226 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cpg CPG_MOD 930>; 228 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 229 resets = <&cpg 930>; 230 i2c-scl-internal-delay-ns = <6>; 231 status = "disabled"; 232 }; 233 234 i2c2: i2c@e6510000 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 compatible = "renesas,i2c-r8a77990", 238 "renesas,rcar-gen3-i2c"; 239 reg = <0 0xe6510000 0 0x40>; 240 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&cpg CPG_MOD 929>; 242 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 243 resets = <&cpg 929>; 244 i2c-scl-internal-delay-ns = <6>; 245 status = "disabled"; 246 }; 247 248 i2c3: i2c@e66d0000 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "renesas,i2c-r8a77990", 252 "renesas,rcar-gen3-i2c"; 253 reg = <0 0xe66d0000 0 0x40>; 254 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cpg CPG_MOD 928>; 256 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 257 resets = <&cpg 928>; 258 i2c-scl-internal-delay-ns = <110>; 259 status = "disabled"; 260 }; 261 262 i2c4: i2c@e66d8000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "renesas,i2c-r8a77990", 266 "renesas,rcar-gen3-i2c"; 267 reg = <0 0xe66d8000 0 0x40>; 268 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cpg CPG_MOD 927>; 270 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 271 resets = <&cpg 927>; 272 i2c-scl-internal-delay-ns = <6>; 273 status = "disabled"; 274 }; 275 276 i2c5: i2c@e66e0000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "renesas,i2c-r8a77990", 280 "renesas,rcar-gen3-i2c"; 281 reg = <0 0xe66e0000 0 0x40>; 282 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&cpg CPG_MOD 919>; 284 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 285 resets = <&cpg 919>; 286 i2c-scl-internal-delay-ns = <6>; 287 status = "disabled"; 288 }; 289 290 i2c6: i2c@e66e8000 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 compatible = "renesas,i2c-r8a77990", 294 "renesas,rcar-gen3-i2c"; 295 reg = <0 0xe66e8000 0 0x40>; 296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cpg CPG_MOD 918>; 298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 299 resets = <&cpg 918>; 300 i2c-scl-internal-delay-ns = <6>; 301 status = "disabled"; 302 }; 303 304 i2c7: i2c@e6690000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "renesas,i2c-r8a77990", 308 "renesas,rcar-gen3-i2c"; 309 reg = <0 0xe6690000 0 0x40>; 310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 1003>; 312 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 313 resets = <&cpg 1003>; 314 i2c-scl-internal-delay-ns = <6>; 315 status = "disabled"; 316 }; 317 318 pfc: pin-controller@e6060000 { 319 compatible = "renesas,pfc-r8a77990"; 320 reg = <0 0xe6060000 0 0x508>; 321 }; 322 323 cpg: clock-controller@e6150000 { 324 compatible = "renesas,r8a77990-cpg-mssr"; 325 reg = <0 0xe6150000 0 0x1000>; 326 clocks = <&extal_clk>; 327 clock-names = "extal"; 328 #clock-cells = <2>; 329 #power-domain-cells = <0>; 330 #reset-cells = <1>; 331 }; 332 333 rst: reset-controller@e6160000 { 334 compatible = "renesas,r8a77990-rst"; 335 reg = <0 0xe6160000 0 0x0200>; 336 }; 337 338 sysc: system-controller@e6180000 { 339 compatible = "renesas,r8a77990-sysc"; 340 reg = <0 0xe6180000 0 0x0400>; 341 #power-domain-cells = <1>; 342 }; 343 344 ipmmu_ds0: mmu@e6740000 { 345 compatible = "renesas,ipmmu-r8a77990"; 346 reg = <0 0xe6740000 0 0x1000>; 347 renesas,ipmmu-main = <&ipmmu_mm 0>; 348 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 349 #iommu-cells = <1>; 350 }; 351 352 ipmmu_ds1: mmu@e7740000 { 353 compatible = "renesas,ipmmu-r8a77990"; 354 reg = <0 0xe7740000 0 0x1000>; 355 renesas,ipmmu-main = <&ipmmu_mm 1>; 356 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 357 #iommu-cells = <1>; 358 }; 359 360 ipmmu_hc: mmu@e6570000 { 361 compatible = "renesas,ipmmu-r8a77990"; 362 reg = <0 0xe6570000 0 0x1000>; 363 renesas,ipmmu-main = <&ipmmu_mm 2>; 364 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 365 #iommu-cells = <1>; 366 }; 367 368 ipmmu_mm: mmu@e67b0000 { 369 compatible = "renesas,ipmmu-r8a77990"; 370 reg = <0 0xe67b0000 0 0x1000>; 371 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 373 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 374 #iommu-cells = <1>; 375 }; 376 377 ipmmu_mp: mmu@ec670000 { 378 compatible = "renesas,ipmmu-r8a77990"; 379 reg = <0 0xec670000 0 0x1000>; 380 renesas,ipmmu-main = <&ipmmu_mm 4>; 381 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 382 #iommu-cells = <1>; 383 }; 384 385 ipmmu_pv0: mmu@fd800000 { 386 compatible = "renesas,ipmmu-r8a77990"; 387 reg = <0 0xfd800000 0 0x1000>; 388 renesas,ipmmu-main = <&ipmmu_mm 6>; 389 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 390 #iommu-cells = <1>; 391 }; 392 393 ipmmu_rt: mmu@ffc80000 { 394 compatible = "renesas,ipmmu-r8a77990"; 395 reg = <0 0xffc80000 0 0x1000>; 396 renesas,ipmmu-main = <&ipmmu_mm 10>; 397 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 398 #iommu-cells = <1>; 399 }; 400 401 ipmmu_vc0: mmu@fe6b0000 { 402 compatible = "renesas,ipmmu-r8a77990"; 403 reg = <0 0xfe6b0000 0 0x1000>; 404 renesas,ipmmu-main = <&ipmmu_mm 12>; 405 power-domains = <&sysc R8A77990_PD_A3VC>; 406 #iommu-cells = <1>; 407 }; 408 409 ipmmu_vi0: mmu@febd0000 { 410 compatible = "renesas,ipmmu-r8a77990"; 411 reg = <0 0xfebd0000 0 0x1000>; 412 renesas,ipmmu-main = <&ipmmu_mm 14>; 413 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 414 #iommu-cells = <1>; 415 }; 416 417 ipmmu_vp0: mmu@fe990000 { 418 compatible = "renesas,ipmmu-r8a77990"; 419 reg = <0 0xfe990000 0 0x1000>; 420 renesas,ipmmu-main = <&ipmmu_mm 16>; 421 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 422 #iommu-cells = <1>; 423 }; 424 425 avb: ethernet@e6800000 { 426 compatible = "renesas,etheravb-r8a77990", 427 "renesas,etheravb-rcar-gen3"; 428 reg = <0 0xe6800000 0 0x800>; 429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "ch0", "ch1", "ch2", "ch3", 455 "ch4", "ch5", "ch6", "ch7", 456 "ch8", "ch9", "ch10", "ch11", 457 "ch12", "ch13", "ch14", "ch15", 458 "ch16", "ch17", "ch18", "ch19", 459 "ch20", "ch21", "ch22", "ch23", 460 "ch24"; 461 clocks = <&cpg CPG_MOD 812>; 462 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 463 resets = <&cpg 812>; 464 phy-mode = "rgmii"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 pwm0: pwm@e6e30000 { 471 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 472 reg = <0 0xe6e30000 0 0x8>; 473 clocks = <&cpg CPG_MOD 523>; 474 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 475 resets = <&cpg 523>; 476 #pwm-cells = <2>; 477 status = "disabled"; 478 }; 479 480 pwm1: pwm@e6e31000 { 481 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 482 reg = <0 0xe6e31000 0 0x8>; 483 clocks = <&cpg CPG_MOD 523>; 484 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 485 resets = <&cpg 523>; 486 #pwm-cells = <2>; 487 status = "disabled"; 488 }; 489 490 pwm2: pwm@e6e32000 { 491 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 492 reg = <0 0xe6e32000 0 0x8>; 493 clocks = <&cpg CPG_MOD 523>; 494 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 495 resets = <&cpg 523>; 496 #pwm-cells = <2>; 497 status = "disabled"; 498 }; 499 500 pwm3: pwm@e6e33000 { 501 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 502 reg = <0 0xe6e33000 0 0x8>; 503 clocks = <&cpg CPG_MOD 523>; 504 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 505 resets = <&cpg 523>; 506 #pwm-cells = <2>; 507 status = "disabled"; 508 }; 509 510 pwm4: pwm@e6e34000 { 511 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 512 reg = <0 0xe6e34000 0 0x8>; 513 clocks = <&cpg CPG_MOD 523>; 514 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 515 resets = <&cpg 523>; 516 #pwm-cells = <2>; 517 status = "disabled"; 518 }; 519 520 pwm5: pwm@e6e35000 { 521 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 522 reg = <0 0xe6e35000 0 0x8>; 523 clocks = <&cpg CPG_MOD 523>; 524 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 525 resets = <&cpg 523>; 526 #pwm-cells = <2>; 527 status = "disabled"; 528 }; 529 530 pwm6: pwm@e6e36000 { 531 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 532 reg = <0 0xe6e36000 0 0x8>; 533 clocks = <&cpg CPG_MOD 523>; 534 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 535 resets = <&cpg 523>; 536 #pwm-cells = <2>; 537 status = "disabled"; 538 }; 539 540 scif2: serial@e6e88000 { 541 compatible = "renesas,scif-r8a77990", 542 "renesas,rcar-gen3-scif", "renesas,scif"; 543 reg = <0 0xe6e88000 0 64>; 544 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cpg CPG_MOD 310>, 546 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 547 <&scif_clk>; 548 clock-names = "fck", "brg_int", "scif_clk"; 549 550 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 551 resets = <&cpg 310>; 552 status = "disabled"; 553 }; 554 555 msiof0: spi@e6e90000 { 556 compatible = "renesas,msiof-r8a77990", 557 "renesas,rcar-gen3-msiof"; 558 reg = <0 0xe6e90000 0 0x0064>; 559 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cpg CPG_MOD 211>; 561 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 562 resets = <&cpg 211>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 msiof1: spi@e6ea0000 { 569 compatible = "renesas,msiof-r8a77990", 570 "renesas,rcar-gen3-msiof"; 571 reg = <0 0xe6ea0000 0 0x0064>; 572 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD 210>; 574 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 575 resets = <&cpg 210>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 status = "disabled"; 579 }; 580 581 msiof2: spi@e6c00000 { 582 compatible = "renesas,msiof-r8a77990", 583 "renesas,rcar-gen3-msiof"; 584 reg = <0 0xe6c00000 0 0x0064>; 585 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cpg CPG_MOD 209>; 587 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 588 resets = <&cpg 209>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 msiof3: spi@e6c10000 { 595 compatible = "renesas,msiof-r8a77990", 596 "renesas,rcar-gen3-msiof"; 597 reg = <0 0xe6c10000 0 0x0064>; 598 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&cpg CPG_MOD 208>; 600 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 601 resets = <&cpg 208>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 vin4: video@e6ef4000 { 608 compatible = "renesas,vin-r8a77990"; 609 reg = <0 0xe6ef4000 0 0x1000>; 610 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 807>; 612 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 613 resets = <&cpg 807>; 614 renesas,id = <4>; 615 status = "disabled"; 616 617 ports { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 621 port@1 { 622 reg = <1>; 623 624 vin4csi40: endpoint { 625 remote-endpoint= <&csi40vin4>; 626 }; 627 }; 628 }; 629 }; 630 631 vin5: video@e6ef5000 { 632 compatible = "renesas,vin-r8a77990"; 633 reg = <0 0xe6ef5000 0 0x1000>; 634 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 806>; 636 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 637 resets = <&cpg 806>; 638 renesas,id = <5>; 639 status = "disabled"; 640 641 ports { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 port@1 { 646 reg = <1>; 647 648 vin5csi40: endpoint { 649 remote-endpoint= <&csi40vin5>; 650 }; 651 }; 652 }; 653 }; 654 655 xhci0: usb@ee000000 { 656 compatible = "renesas,xhci-r8a77990", 657 "renesas,rcar-gen3-xhci"; 658 reg = <0 0xee000000 0 0xc00>; 659 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cpg CPG_MOD 328>; 661 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 662 resets = <&cpg 328>; 663 status = "disabled"; 664 }; 665 666 ohci0: usb@ee080000 { 667 compatible = "generic-ohci"; 668 reg = <0 0xee080000 0 0x100>; 669 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cpg CPG_MOD 703>; 671 phys = <&usb2_phy0>; 672 phy-names = "usb"; 673 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 674 resets = <&cpg 703>; 675 status = "disabled"; 676 }; 677 678 ehci0: usb@ee080100 { 679 compatible = "generic-ehci"; 680 reg = <0 0xee080100 0 0x100>; 681 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 703>; 683 phys = <&usb2_phy0>; 684 phy-names = "usb"; 685 companion = <&ohci0>; 686 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 687 resets = <&cpg 703>; 688 status = "disabled"; 689 }; 690 691 usb2_phy0: usb-phy@ee080200 { 692 compatible = "renesas,usb2-phy-r8a77990", 693 "renesas,rcar-gen3-usb2-phy"; 694 reg = <0 0xee080200 0 0x700>; 695 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cpg CPG_MOD 703>; 697 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 698 resets = <&cpg 703>; 699 #phy-cells = <0>; 700 status = "disabled"; 701 }; 702 703 gic: interrupt-controller@f1010000 { 704 compatible = "arm,gic-400"; 705 #interrupt-cells = <3>; 706 #address-cells = <0>; 707 interrupt-controller; 708 reg = <0x0 0xf1010000 0 0x1000>, 709 <0x0 0xf1020000 0 0x20000>, 710 <0x0 0xf1040000 0 0x20000>, 711 <0x0 0xf1060000 0 0x20000>; 712 interrupts = <GIC_PPI 9 713 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 714 clocks = <&cpg CPG_MOD 408>; 715 clock-names = "clk"; 716 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 717 resets = <&cpg 408>; 718 }; 719 720 csi40: csi2@feaa0000 { 721 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; 722 reg = <0 0xfeaa0000 0 0x10000>; 723 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&cpg CPG_MOD 716>; 725 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 726 resets = <&cpg 716>; 727 status = "disabled"; 728 729 ports { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 733 port@1 { 734 #address-cells = <1>; 735 #size-cells = <0>; 736 737 reg = <1>; 738 739 csi40vin4: endpoint@0 { 740 reg = <0>; 741 remote-endpoint = <&vin4csi40>; 742 }; 743 csi40vin5: endpoint@1 { 744 reg = <1>; 745 remote-endpoint = <&vin5csi40>; 746 }; 747 }; 748 }; 749 }; 750 751 prr: chipid@fff00044 { 752 compatible = "renesas,prr"; 753 reg = <0 0xfff00044 0 4>; 754 }; 755 }; 756 757 timer { 758 compatible = "arm,armv8-timer"; 759 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 760 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 761 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 762 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 763 }; 764}; 765