r8a77990.dtsi (0aab5b914b41601ee7e4ba9bd81344665db1fbca) | r8a77990.dtsi (9504a9f27a8c2c3a78f566c5cde75b53657b386a) |
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1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h> --- 1621 unchanged lines hidden (view full) --- 1630 pciec0: pcie@fe000000 { 1631 compatible = "renesas,pcie-r8a77990", 1632 "renesas,pcie-rcar-gen3"; 1633 reg = <0 0xfe000000 0 0x80000>; 1634 #address-cells = <3>; 1635 #size-cells = <2>; 1636 bus-range = <0x00 0xff>; 1637 device_type = "pci"; | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h> --- 1621 unchanged lines hidden (view full) --- 1630 pciec0: pcie@fe000000 { 1631 compatible = "renesas,pcie-r8a77990", 1632 "renesas,pcie-rcar-gen3"; 1633 reg = <0 0xfe000000 0 0x80000>; 1634 #address-cells = <3>; 1635 #size-cells = <2>; 1636 bus-range = <0x00 0xff>; 1637 device_type = "pci"; |
1638 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1639 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1640 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1641 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | 1638 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1639 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1640 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1641 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; |
1642 /* Map all possible DDR as inbound ranges */ 1643 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1644 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1647 #interrupt-cells = <1>; 1648 interrupt-map-mask = <0 0 0 0>; 1649 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; --- 275 unchanged lines hidden --- | 1642 /* Map all possible DDR as inbound ranges */ 1643 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1644 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1647 #interrupt-cells = <1>; 1648 interrupt-map-mask = <0 0 0 0>; 1649 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; --- 275 unchanged lines hidden --- |