r8a77980.dtsi (f38c41727211f2cdd9bb6f2999d46daafeacc5aa) r8a77980.dtsi (22fb06cd54f92132bf7a8b7740abc7db79a5130b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cpg CPG_MOD 914>,
187 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
188 <&can_clk>;
189 clock-names = "fck", "canfd", "can_clk";
190 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
191 assigned-clock-rates = <40000000>;
192 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

--- 176 unchanged lines hidden (view full) ---

185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cpg CPG_MOD 914>,
187 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
188 <&can_clk>;
189 clock-names = "fck", "canfd", "can_clk";
190 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
191 assigned-clock-rates = <40000000>;
192 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
193 resets = <&cpg 914>;
193 status = "disabled";
194
195 channel0 {
196 status = "disabled";
197 };
198
199 channel1 {
200 status = "disabled";

--- 234 unchanged lines hidden --- 		194 status = "disabled";
195
196 channel0 {
197 status = "disabled";
198 };
199
200 channel1 {
201 status = "disabled";

--- 234 unchanged lines hidden ---