1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 a53_0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a53", "arm,armv8"; 26 reg = <0>; 27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 29 next-level-cache = <&L2_CA53>; 30 enable-method = "psci"; 31 }; 32 33 L2_CA53: cache-controller { 34 compatible = "cache"; 35 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 36 cache-unified; 37 cache-level = <2>; 38 }; 39 }; 40 41 /* External CAN clock - to be overridden by boards that provide it */ 42 can_clk: can { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 extal_clk: extal { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 /* This value must be overridden by the board */ 52 clock-frequency = <0>; 53 }; 54 55 extalr_clk: extalr { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 /* This value must be overridden by the board */ 59 clock-frequency = <0>; 60 }; 61 62 psci { 63 compatible = "arm,psci-1.0", "arm,psci-0.2"; 64 method = "smc"; 65 }; 66 67 /* External SCIF clock - to be overridden by boards that provide it */ 68 scif_clk: scif { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 }; 73 74 soc { 75 compatible = "simple-bus"; 76 interrupt-parent = <&gic>; 77 78 #address-cells = <2>; 79 #size-cells = <2>; 80 ranges; 81 82 pfc: pin-controller@e6060000 { 83 compatible = "renesas,pfc-r8a77980"; 84 reg = <0 0xe6060000 0 0x50c>; 85 }; 86 87 cpg: clock-controller@e6150000 { 88 compatible = "renesas,r8a77980-cpg-mssr"; 89 reg = <0 0xe6150000 0 0x1000>; 90 clocks = <&extal_clk>, <&extalr_clk>; 91 clock-names = "extal", "extalr"; 92 #clock-cells = <2>; 93 #power-domain-cells = <0>; 94 #reset-cells = <1>; 95 }; 96 97 rst: reset-controller@e6160000 { 98 compatible = "renesas,r8a77980-rst"; 99 reg = <0 0xe6160000 0 0x200>; 100 }; 101 102 sysc: system-controller@e6180000 { 103 compatible = "renesas,r8a77980-sysc"; 104 reg = <0 0xe6180000 0 0x440>; 105 #power-domain-cells = <1>; 106 }; 107 108 hscif0: serial@e6540000 { 109 compatible = "renesas,hscif-r8a77980", 110 "renesas,rcar-gen3-hscif", 111 "renesas,hscif"; 112 reg = <0 0xe6540000 0 0x60>; 113 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&cpg CPG_MOD 520>, 115 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 116 <&scif_clk>; 117 clock-names = "fck", "brg_int", "scif_clk"; 118 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 119 <&dmac2 0x31>, <&dmac2 0x30>; 120 dma-names = "tx", "rx", "tx", "rx"; 121 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 122 resets = <&cpg 520>; 123 status = "disabled"; 124 }; 125 126 hscif1: serial@e6550000 { 127 compatible = "renesas,hscif-r8a77980", 128 "renesas,rcar-gen3-hscif", 129 "renesas,hscif"; 130 reg = <0 0xe6550000 0 0x60>; 131 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&cpg CPG_MOD 519>, 133 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 134 <&scif_clk>; 135 clock-names = "fck", "brg_int", "scif_clk"; 136 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 137 <&dmac2 0x33>, <&dmac2 0x32>; 138 dma-names = "tx", "rx", "tx", "rx"; 139 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 140 resets = <&cpg 519>; 141 status = "disabled"; 142 }; 143 144 hscif2: serial@e6560000 { 145 compatible = "renesas,hscif-r8a77980", 146 "renesas,rcar-gen3-hscif", 147 "renesas,hscif"; 148 reg = <0 0xe6560000 0 0x60>; 149 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&cpg CPG_MOD 518>, 151 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 152 <&scif_clk>; 153 clock-names = "fck", "brg_int", "scif_clk"; 154 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 155 <&dmac2 0x35>, <&dmac2 0x34>; 156 dma-names = "tx", "rx", "tx", "rx"; 157 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 158 resets = <&cpg 518>; 159 status = "disabled"; 160 }; 161 162 hscif3: serial@e66a0000 { 163 compatible = "renesas,hscif-r8a77980", 164 "renesas,rcar-gen3-hscif", 165 "renesas,hscif"; 166 reg = <0 0xe66a0000 0 0x60>; 167 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&cpg CPG_MOD 517>, 169 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 170 <&scif_clk>; 171 clock-names = "fck", "brg_int", "scif_clk"; 172 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 173 <&dmac2 0x37>, <&dmac2 0x36>; 174 dma-names = "tx", "rx", "tx", "rx"; 175 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 176 resets = <&cpg 517>; 177 status = "disabled"; 178 }; 179 180 canfd: can@e66c0000 { 181 compatible = "renesas,r8a77980-canfd", 182 "renesas,rcar-gen3-canfd"; 183 reg = <0 0xe66c0000 0 0x8000>; 184 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cpg CPG_MOD 914>, 187 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 188 <&can_clk>; 189 clock-names = "fck", "canfd", "can_clk"; 190 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 191 assigned-clock-rates = <40000000>; 192 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 193 resets = <&cpg 914>; 194 status = "disabled"; 195 196 channel0 { 197 status = "disabled"; 198 }; 199 200 channel1 { 201 status = "disabled"; 202 }; 203 }; 204 205 avb: ethernet@e6800000 { 206 compatible = "renesas,etheravb-r8a77980", 207 "renesas,etheravb-rcar-gen3"; 208 reg = <0 0xe6800000 0 0x800>; 209 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 234 interrupt-names = "ch0", "ch1", "ch2", "ch3", 235 "ch4", "ch5", "ch6", "ch7", 236 "ch8", "ch9", "ch10", "ch11", 237 "ch12", "ch13", "ch14", "ch15", 238 "ch16", "ch17", "ch18", "ch19", 239 "ch20", "ch21", "ch22", "ch23", 240 "ch24"; 241 clocks = <&cpg CPG_MOD 812>; 242 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 243 resets = <&cpg 812>; 244 phy-mode = "rgmii"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 scif0: serial@e6e60000 { 250 compatible = "renesas,scif-r8a77980", 251 "renesas,rcar-gen3-scif", 252 "renesas,scif"; 253 reg = <0 0xe6e60000 0 0x40>; 254 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cpg CPG_MOD 207>, 256 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 257 <&scif_clk>; 258 clock-names = "fck", "brg_int", "scif_clk"; 259 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 260 <&dmac2 0x51>, <&dmac2 0x50>; 261 dma-names = "tx", "rx", "tx", "rx"; 262 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 263 resets = <&cpg 207>; 264 status = "disabled"; 265 }; 266 267 scif1: serial@e6e68000 { 268 compatible = "renesas,scif-r8a77980", 269 "renesas,rcar-gen3-scif", 270 "renesas,scif"; 271 reg = <0 0xe6e68000 0 0x40>; 272 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&cpg CPG_MOD 206>, 274 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 275 <&scif_clk>; 276 clock-names = "fck", "brg_int", "scif_clk"; 277 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 278 <&dmac2 0x53>, <&dmac2 0x52>; 279 dma-names = "tx", "rx", "tx", "rx"; 280 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 281 resets = <&cpg 206>; 282 status = "disabled"; 283 }; 284 285 scif3: serial@e6c50000 { 286 compatible = "renesas,scif-r8a77980", 287 "renesas,rcar-gen3-scif", 288 "renesas,scif"; 289 reg = <0 0xe6c50000 0 0x40>; 290 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cpg CPG_MOD 204>, 292 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 293 <&scif_clk>; 294 clock-names = "fck", "brg_int", "scif_clk"; 295 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 296 <&dmac2 0x57>, <&dmac2 0x56>; 297 dma-names = "tx", "rx", "tx", "rx"; 298 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 299 resets = <&cpg 204>; 300 status = "disabled"; 301 }; 302 303 scif4: serial@e6c40000 { 304 compatible = "renesas,scif-r8a77980", 305 "renesas,rcar-gen3-scif", 306 "renesas,scif"; 307 reg = <0 0xe6c40000 0 0x40>; 308 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&cpg CPG_MOD 203>, 310 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 311 <&scif_clk>; 312 clock-names = "fck", "brg_int", "scif_clk"; 313 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 314 <&dmac2 0x59>, <&dmac2 0x58>; 315 dma-names = "tx", "rx", "tx", "rx"; 316 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 317 resets = <&cpg 203>; 318 status = "disabled"; 319 }; 320 321 dmac1: dma-controller@e7300000 { 322 compatible = "renesas,dmac-r8a77980", 323 "renesas,rcar-dmac"; 324 reg = <0 0xe7300000 0 0x10000>; 325 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 326 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "error", 343 "ch0", "ch1", "ch2", "ch3", 344 "ch4", "ch5", "ch6", "ch7", 345 "ch8", "ch9", "ch10", "ch11", 346 "ch12", "ch13", "ch14", "ch15"; 347 clocks = <&cpg CPG_MOD 218>; 348 clock-names = "fck"; 349 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 350 resets = <&cpg 218>; 351 #dma-cells = <1>; 352 dma-channels = <16>; 353 }; 354 355 dmac2: dma-controller@e7310000 { 356 compatible = "renesas,dmac-r8a77980", 357 "renesas,rcar-dmac"; 358 reg = <0 0xe7310000 0 0x10000>; 359 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 360 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 361 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 362 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 376 interrupt-names = "error", 377 "ch0", "ch1", "ch2", "ch3", 378 "ch4", "ch5", "ch6", "ch7", 379 "ch8", "ch9", "ch10", "ch11", 380 "ch12", "ch13", "ch14", "ch15"; 381 clocks = <&cpg CPG_MOD 217>; 382 clock-names = "fck"; 383 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 384 resets = <&cpg 217>; 385 #dma-cells = <1>; 386 dma-channels = <16>; 387 }; 388 389 mmc0: mmc@ee140000 { 390 compatible = "renesas,sdhi-r8a77980", 391 "renesas,rcar-gen3-sdhi"; 392 reg = <0 0xee140000 0 0x2000>; 393 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cpg CPG_MOD 314>; 395 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 396 resets = <&cpg 314>; 397 max-frequency = <200000000>; 398 status = "disabled"; 399 }; 400 401 gic: interrupt-controller@f1010000 { 402 compatible = "arm,gic-400"; 403 #interrupt-cells = <3>; 404 #address-cells = <0>; 405 interrupt-controller; 406 reg = <0x0 0xf1010000 0 0x1000>, 407 <0x0 0xf1020000 0 0x20000>, 408 <0x0 0xf1040000 0 0x20000>, 409 <0x0 0xf1060000 0 0x20000>; 410 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 411 IRQ_TYPE_LEVEL_HIGH)>; 412 clocks = <&cpg CPG_MOD 408>; 413 clock-names = "clk"; 414 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 415 resets = <&cpg 408>; 416 }; 417 418 prr: chipid@fff00044 { 419 compatible = "renesas,prr"; 420 reg = <0 0xfff00044 0 4>; 421 }; 422 }; 423 424 timer { 425 compatible = "arm,armv8-timer"; 426 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 427 IRQ_TYPE_LEVEL_LOW)>, 428 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 429 IRQ_TYPE_LEVEL_LOW)>, 430 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 431 IRQ_TYPE_LEVEL_LOW)>, 432 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 433 IRQ_TYPE_LEVEL_LOW)>; 434 }; 435}; 436