r8a77980.dtsi (c64cc3683ff2622fe3528af93a5df01a6584e871) r8a77980.dtsi (1184ea3fd4c83a7bf6a8f51fcf73d620706557ce)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/power/r8a77980-sysc.h>
12
13/ {
14 compatible = "renesas,r8a77980";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 a53_0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a53", "arm,armv8";
25 reg = <0>;
26 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
13
14/ {
15 compatible = "renesas,r8a77980";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 a53_0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a53", "arm,armv8";
26 reg = <0>;
27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
27 power-domains = <&sysc 5>;
28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
28 next-level-cache = <&L2_CA53>;
29 enable-method = "psci";
30 };
31
32 L2_CA53: cache-controller {
33 compatible = "cache";
29 next-level-cache = <&L2_CA53>;
30 enable-method = "psci";
31 };
32
33 L2_CA53: cache-controller {
34 compatible = "cache";
34 power-domains = <&sysc 21>;
35 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
35 cache-unified;
36 cache-level = <2>;
37 };
38 };
39
40 extal_clk: extal {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;

--- 62 unchanged lines hidden (view full) ---

105 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&cpg CPG_MOD 520>,
107 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
108 <&scif_clk>;
109 clock-names = "fck", "brg_int", "scif_clk";
110 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
111 <&dmac2 0x31>, <&dmac2 0x30>;
112 dma-names = "tx", "rx", "tx", "rx";
36 cache-unified;
37 cache-level = <2>;
38 };
39 };
40
41 extal_clk: extal {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;

--- 62 unchanged lines hidden (view full) ---

106 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&cpg CPG_MOD 520>,
108 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
109 <&scif_clk>;
110 clock-names = "fck", "brg_int", "scif_clk";
111 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
112 <&dmac2 0x31>, <&dmac2 0x30>;
113 dma-names = "tx", "rx", "tx", "rx";
113 power-domains = <&sysc 32>;
114 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
114 resets = <&cpg 520>;
115 status = "disabled";
116 };
117
118 hscif1: serial@e6550000 {
119 compatible = "renesas,hscif-r8a77980",
120 "renesas,rcar-gen3-hscif",
121 "renesas,hscif";
122 reg = <0 0xe6550000 0 0x60>;
123 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cpg CPG_MOD 519>,
125 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
126 <&scif_clk>;
127 clock-names = "fck", "brg_int", "scif_clk";
128 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
129 <&dmac2 0x33>, <&dmac2 0x32>;
130 dma-names = "tx", "rx", "tx", "rx";
115 resets = <&cpg 520>;
116 status = "disabled";
117 };
118
119 hscif1: serial@e6550000 {
120 compatible = "renesas,hscif-r8a77980",
121 "renesas,rcar-gen3-hscif",
122 "renesas,hscif";
123 reg = <0 0xe6550000 0 0x60>;
124 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&cpg CPG_MOD 519>,
126 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
127 <&scif_clk>;
128 clock-names = "fck", "brg_int", "scif_clk";
129 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
130 <&dmac2 0x33>, <&dmac2 0x32>;
131 dma-names = "tx", "rx", "tx", "rx";
131 power-domains = <&sysc 32>;
132 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
132 resets = <&cpg 519>;
133 status = "disabled";
134 };
135
136 hscif2: serial@e6560000 {
137 compatible = "renesas,hscif-r8a77980",
138 "renesas,rcar-gen3-hscif",
139 "renesas,hscif";
140 reg = <0 0xe6560000 0 0x60>;
141 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&cpg CPG_MOD 518>,
143 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
144 <&scif_clk>;
145 clock-names = "fck", "brg_int", "scif_clk";
146 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
147 <&dmac2 0x35>, <&dmac2 0x34>;
148 dma-names = "tx", "rx", "tx", "rx";
133 resets = <&cpg 519>;
134 status = "disabled";
135 };
136
137 hscif2: serial@e6560000 {
138 compatible = "renesas,hscif-r8a77980",
139 "renesas,rcar-gen3-hscif",
140 "renesas,hscif";
141 reg = <0 0xe6560000 0 0x60>;
142 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&cpg CPG_MOD 518>,
144 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
145 <&scif_clk>;
146 clock-names = "fck", "brg_int", "scif_clk";
147 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
148 <&dmac2 0x35>, <&dmac2 0x34>;
149 dma-names = "tx", "rx", "tx", "rx";
149 power-domains = <&sysc 32>;
150 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
150 resets = <&cpg 518>;
151 status = "disabled";
152 };
153
154 hscif3: serial@e66a0000 {
155 compatible = "renesas,hscif-r8a77980",
156 "renesas,rcar-gen3-hscif",
157 "renesas,hscif";
158 reg = <0 0xe66a0000 0 0x60>;
159 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cpg CPG_MOD 517>,
161 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
162 <&scif_clk>;
163 clock-names = "fck", "brg_int", "scif_clk";
164 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
165 <&dmac2 0x37>, <&dmac2 0x36>;
166 dma-names = "tx", "rx", "tx", "rx";
151 resets = <&cpg 518>;
152 status = "disabled";
153 };
154
155 hscif3: serial@e66a0000 {
156 compatible = "renesas,hscif-r8a77980",
157 "renesas,rcar-gen3-hscif",
158 "renesas,hscif";
159 reg = <0 0xe66a0000 0 0x60>;
160 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpg CPG_MOD 517>,
162 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
163 <&scif_clk>;
164 clock-names = "fck", "brg_int", "scif_clk";
165 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
166 <&dmac2 0x37>, <&dmac2 0x36>;
167 dma-names = "tx", "rx", "tx", "rx";
167 power-domains = <&sysc 32>;
168 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
168 resets = <&cpg 517>;
169 status = "disabled";
170 };
171
172 avb: ethernet@e6800000 {
173 compatible = "renesas,etheravb-r8a77980",
174 "renesas,etheravb-rcar-gen3";
175 reg = <0 0xe6800000 0 0x800>;

--- 25 unchanged lines hidden (view full) ---

201 interrupt-names = "ch0", "ch1", "ch2", "ch3",
202 "ch4", "ch5", "ch6", "ch7",
203 "ch8", "ch9", "ch10", "ch11",
204 "ch12", "ch13", "ch14", "ch15",
205 "ch16", "ch17", "ch18", "ch19",
206 "ch20", "ch21", "ch22", "ch23",
207 "ch24";
208 clocks = <&cpg CPG_MOD 812>;
169 resets = <&cpg 517>;
170 status = "disabled";
171 };
172
173 avb: ethernet@e6800000 {
174 compatible = "renesas,etheravb-r8a77980",
175 "renesas,etheravb-rcar-gen3";
176 reg = <0 0xe6800000 0 0x800>;

--- 25 unchanged lines hidden (view full) ---

202 interrupt-names = "ch0", "ch1", "ch2", "ch3",
203 "ch4", "ch5", "ch6", "ch7",
204 "ch8", "ch9", "ch10", "ch11",
205 "ch12", "ch13", "ch14", "ch15",
206 "ch16", "ch17", "ch18", "ch19",
207 "ch20", "ch21", "ch22", "ch23",
208 "ch24";
209 clocks = <&cpg CPG_MOD 812>;
209 power-domains = <&sysc 32>;
210 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
210 resets = <&cpg 812>;
211 phy-mode = "rgmii";
212 #address-cells = <1>;
213 #size-cells = <0>;
214 };
215
216 scif0: serial@e6e60000 {
217 compatible = "renesas,scif-r8a77980",
218 "renesas,rcar-gen3-scif",
219 "renesas,scif";
220 reg = <0 0xe6e60000 0 0x40>;
221 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cpg CPG_MOD 207>,
223 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
224 <&scif_clk>;
225 clock-names = "fck", "brg_int", "scif_clk";
226 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
227 <&dmac2 0x51>, <&dmac2 0x50>;
228 dma-names = "tx", "rx", "tx", "rx";
211 resets = <&cpg 812>;
212 phy-mode = "rgmii";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 };
216
217 scif0: serial@e6e60000 {
218 compatible = "renesas,scif-r8a77980",
219 "renesas,rcar-gen3-scif",
220 "renesas,scif";
221 reg = <0 0xe6e60000 0 0x40>;
222 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cpg CPG_MOD 207>,
224 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
225 <&scif_clk>;
226 clock-names = "fck", "brg_int", "scif_clk";
227 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
228 <&dmac2 0x51>, <&dmac2 0x50>;
229 dma-names = "tx", "rx", "tx", "rx";
229 power-domains = <&sysc 32>;
230 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
230 resets = <&cpg 207>;
231 status = "disabled";
232 };
233
234 scif1: serial@e6e68000 {
235 compatible = "renesas,scif-r8a77980",
236 "renesas,rcar-gen3-scif",
237 "renesas,scif";
238 reg = <0 0xe6e68000 0 0x40>;
239 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cpg CPG_MOD 206>,
241 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
242 <&scif_clk>;
243 clock-names = "fck", "brg_int", "scif_clk";
244 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
245 <&dmac2 0x53>, <&dmac2 0x52>;
246 dma-names = "tx", "rx", "tx", "rx";
231 resets = <&cpg 207>;
232 status = "disabled";
233 };
234
235 scif1: serial@e6e68000 {
236 compatible = "renesas,scif-r8a77980",
237 "renesas,rcar-gen3-scif",
238 "renesas,scif";
239 reg = <0 0xe6e68000 0 0x40>;
240 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&cpg CPG_MOD 206>,
242 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
243 <&scif_clk>;
244 clock-names = "fck", "brg_int", "scif_clk";
245 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
246 <&dmac2 0x53>, <&dmac2 0x52>;
247 dma-names = "tx", "rx", "tx", "rx";
247 power-domains = <&sysc 32>;
248 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
248 resets = <&cpg 206>;
249 status = "disabled";
250 };
251
252 scif3: serial@e6c50000 {
253 compatible = "renesas,scif-r8a77980",
254 "renesas,rcar-gen3-scif",
255 "renesas,scif";
256 reg = <0 0xe6c50000 0 0x40>;
257 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cpg CPG_MOD 204>,
259 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
260 <&scif_clk>;
261 clock-names = "fck", "brg_int", "scif_clk";
262 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
263 <&dmac2 0x57>, <&dmac2 0x56>;
264 dma-names = "tx", "rx", "tx", "rx";
249 resets = <&cpg 206>;
250 status = "disabled";
251 };
252
253 scif3: serial@e6c50000 {
254 compatible = "renesas,scif-r8a77980",
255 "renesas,rcar-gen3-scif",
256 "renesas,scif";
257 reg = <0 0xe6c50000 0 0x40>;
258 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&cpg CPG_MOD 204>,
260 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
261 <&scif_clk>;
262 clock-names = "fck", "brg_int", "scif_clk";
263 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
264 <&dmac2 0x57>, <&dmac2 0x56>;
265 dma-names = "tx", "rx", "tx", "rx";
265 power-domains = <&sysc 32>;
266 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
266 resets = <&cpg 204>;
267 status = "disabled";
268 };
269
270 scif4: serial@e6c40000 {
271 compatible = "renesas,scif-r8a77980",
272 "renesas,rcar-gen3-scif",
273 "renesas,scif";
274 reg = <0 0xe6c40000 0 0x40>;
275 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&cpg CPG_MOD 203>,
277 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
278 <&scif_clk>;
279 clock-names = "fck", "brg_int", "scif_clk";
280 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
281 <&dmac2 0x59>, <&dmac2 0x58>;
282 dma-names = "tx", "rx", "tx", "rx";
267 resets = <&cpg 204>;
268 status = "disabled";
269 };
270
271 scif4: serial@e6c40000 {
272 compatible = "renesas,scif-r8a77980",
273 "renesas,rcar-gen3-scif",
274 "renesas,scif";
275 reg = <0 0xe6c40000 0 0x40>;
276 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&cpg CPG_MOD 203>,
278 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
279 <&scif_clk>;
280 clock-names = "fck", "brg_int", "scif_clk";
281 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
282 <&dmac2 0x59>, <&dmac2 0x58>;
283 dma-names = "tx", "rx", "tx", "rx";
283 power-domains = <&sysc 32>;
284 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
284 resets = <&cpg 203>;
285 status = "disabled";
286 };
287
288 dmac1: dma-controller@e7300000 {
289 compatible = "renesas,dmac-r8a77980",
290 "renesas,rcar-dmac";
291 reg = <0 0xe7300000 0 0x10000>;

--- 16 unchanged lines hidden (view full) ---

308 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
309 interrupt-names = "error",
310 "ch0", "ch1", "ch2", "ch3",
311 "ch4", "ch5", "ch6", "ch7",
312 "ch8", "ch9", "ch10", "ch11",
313 "ch12", "ch13", "ch14", "ch15";
314 clocks = <&cpg CPG_MOD 218>;
315 clock-names = "fck";
285 resets = <&cpg 203>;
286 status = "disabled";
287 };
288
289 dmac1: dma-controller@e7300000 {
290 compatible = "renesas,dmac-r8a77980",
291 "renesas,rcar-dmac";
292 reg = <0 0xe7300000 0 0x10000>;

--- 16 unchanged lines hidden (view full) ---

309 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-names = "error",
311 "ch0", "ch1", "ch2", "ch3",
312 "ch4", "ch5", "ch6", "ch7",
313 "ch8", "ch9", "ch10", "ch11",
314 "ch12", "ch13", "ch14", "ch15";
315 clocks = <&cpg CPG_MOD 218>;
316 clock-names = "fck";
316 power-domains = <&sysc 32>;
317 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
317 resets = <&cpg 218>;
318 #dma-cells = <1>;
319 dma-channels = <16>;
320 };
321
322 dmac2: dma-controller@e7310000 {
323 compatible = "renesas,dmac-r8a77980",
324 "renesas,rcar-dmac";

--- 17 unchanged lines hidden (view full) ---

342 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-names = "error",
344 "ch0", "ch1", "ch2", "ch3",
345 "ch4", "ch5", "ch6", "ch7",
346 "ch8", "ch9", "ch10", "ch11",
347 "ch12", "ch13", "ch14", "ch15";
348 clocks = <&cpg CPG_MOD 217>;
349 clock-names = "fck";
318 resets = <&cpg 218>;
319 #dma-cells = <1>;
320 dma-channels = <16>;
321 };
322
323 dmac2: dma-controller@e7310000 {
324 compatible = "renesas,dmac-r8a77980",
325 "renesas,rcar-dmac";

--- 17 unchanged lines hidden (view full) ---

343 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-names = "error",
345 "ch0", "ch1", "ch2", "ch3",
346 "ch4", "ch5", "ch6", "ch7",
347 "ch8", "ch9", "ch10", "ch11",
348 "ch12", "ch13", "ch14", "ch15";
349 clocks = <&cpg CPG_MOD 217>;
350 clock-names = "fck";
350 power-domains = <&sysc 32>;
351 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
351 resets = <&cpg 217>;
352 #dma-cells = <1>;
353 dma-channels = <16>;
354 };
355
356 mmc0: mmc@ee140000 {
357 compatible = "renesas,sdhi-r8a77980",
358 "renesas,rcar-gen3-sdhi";
359 reg = <0 0xee140000 0 0x2000>;
360 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cpg CPG_MOD 314>;
352 resets = <&cpg 217>;
353 #dma-cells = <1>;
354 dma-channels = <16>;
355 };
356
357 mmc0: mmc@ee140000 {
358 compatible = "renesas,sdhi-r8a77980",
359 "renesas,rcar-gen3-sdhi";
360 reg = <0 0xee140000 0 0x2000>;
361 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&cpg CPG_MOD 314>;
362 power-domains = <&sysc 32>;
363 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
363 resets = <&cpg 314>;
364 max-frequency = <200000000>;
365 status = "disabled";
366 };
367
368 gic: interrupt-controller@f1010000 {
369 compatible = "arm,gic-400";
370 #interrupt-cells = <3>;
371 #address-cells = <0>;
372 interrupt-controller;
373 reg = <0x0 0xf1010000 0 0x1000>,
374 <0x0 0xf1020000 0 0x20000>,
375 <0x0 0xf1040000 0 0x20000>,
376 <0x0 0xf1060000 0 0x20000>;
377 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
378 IRQ_TYPE_LEVEL_HIGH)>;
379 clocks = <&cpg CPG_MOD 408>;
380 clock-names = "clk";
364 resets = <&cpg 314>;
365 max-frequency = <200000000>;
366 status = "disabled";
367 };
368
369 gic: interrupt-controller@f1010000 {
370 compatible = "arm,gic-400";
371 #interrupt-cells = <3>;
372 #address-cells = <0>;
373 interrupt-controller;
374 reg = <0x0 0xf1010000 0 0x1000>,
375 <0x0 0xf1020000 0 0x20000>,
376 <0x0 0xf1040000 0 0x20000>,
377 <0x0 0xf1060000 0 0x20000>;
378 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
379 IRQ_TYPE_LEVEL_HIGH)>;
380 clocks = <&cpg CPG_MOD 408>;
381 clock-names = "clk";
381 power-domains = <&sysc 32>;
382 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
382 resets = <&cpg 408>;
383 };
384
385 prr: chipid@fff00044 {
386 compatible = "renesas,prr";
387 reg = <0 0xfff00044 0 4>;
388 };
389 };

--- 13 unchanged lines hidden --- 		383 resets = <&cpg 408>;
384 };
385
386 prr: chipid@fff00044 {
387 compatible = "renesas,prr";
388 reg = <0 0xfff00044 0 4>;
389 };
390 };

--- 13 unchanged lines hidden ---