1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 a53_0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a53", "arm,armv8"; 26 reg = <0>; 27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 29 next-level-cache = <&L2_CA53>; 30 enable-method = "psci"; 31 }; 32 33 L2_CA53: cache-controller { 34 compatible = "cache"; 35 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 36 cache-unified; 37 cache-level = <2>; 38 }; 39 }; 40 41 extal_clk: extal { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 /* This value must be overridden by the board */ 45 clock-frequency = <0>; 46 }; 47 48 extalr_clk: extalr { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 /* This value must be overridden by the board */ 52 clock-frequency = <0>; 53 }; 54 55 psci { 56 compatible = "arm,psci-1.0", "arm,psci-0.2"; 57 method = "smc"; 58 }; 59 60 /* External SCIF clock - to be overridden by boards that provide it */ 61 scif_clk: scif { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 65 }; 66 67 soc { 68 compatible = "simple-bus"; 69 interrupt-parent = <&gic>; 70 71 #address-cells = <2>; 72 #size-cells = <2>; 73 ranges; 74 75 pfc: pin-controller@e6060000 { 76 compatible = "renesas,pfc-r8a77980"; 77 reg = <0 0xe6060000 0 0x50c>; 78 }; 79 80 cpg: clock-controller@e6150000 { 81 compatible = "renesas,r8a77980-cpg-mssr"; 82 reg = <0 0xe6150000 0 0x1000>; 83 clocks = <&extal_clk>, <&extalr_clk>; 84 clock-names = "extal", "extalr"; 85 #clock-cells = <2>; 86 #power-domain-cells = <0>; 87 #reset-cells = <1>; 88 }; 89 90 rst: reset-controller@e6160000 { 91 compatible = "renesas,r8a77980-rst"; 92 reg = <0 0xe6160000 0 0x200>; 93 }; 94 95 sysc: system-controller@e6180000 { 96 compatible = "renesas,r8a77980-sysc"; 97 reg = <0 0xe6180000 0 0x440>; 98 #power-domain-cells = <1>; 99 }; 100 101 hscif0: serial@e6540000 { 102 compatible = "renesas,hscif-r8a77980", 103 "renesas,rcar-gen3-hscif", 104 "renesas,hscif"; 105 reg = <0 0xe6540000 0 0x60>; 106 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&cpg CPG_MOD 520>, 108 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 109 <&scif_clk>; 110 clock-names = "fck", "brg_int", "scif_clk"; 111 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 112 <&dmac2 0x31>, <&dmac2 0x30>; 113 dma-names = "tx", "rx", "tx", "rx"; 114 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 115 resets = <&cpg 520>; 116 status = "disabled"; 117 }; 118 119 hscif1: serial@e6550000 { 120 compatible = "renesas,hscif-r8a77980", 121 "renesas,rcar-gen3-hscif", 122 "renesas,hscif"; 123 reg = <0 0xe6550000 0 0x60>; 124 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&cpg CPG_MOD 519>, 126 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 127 <&scif_clk>; 128 clock-names = "fck", "brg_int", "scif_clk"; 129 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 130 <&dmac2 0x33>, <&dmac2 0x32>; 131 dma-names = "tx", "rx", "tx", "rx"; 132 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 133 resets = <&cpg 519>; 134 status = "disabled"; 135 }; 136 137 hscif2: serial@e6560000 { 138 compatible = "renesas,hscif-r8a77980", 139 "renesas,rcar-gen3-hscif", 140 "renesas,hscif"; 141 reg = <0 0xe6560000 0 0x60>; 142 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&cpg CPG_MOD 518>, 144 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 145 <&scif_clk>; 146 clock-names = "fck", "brg_int", "scif_clk"; 147 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 148 <&dmac2 0x35>, <&dmac2 0x34>; 149 dma-names = "tx", "rx", "tx", "rx"; 150 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 151 resets = <&cpg 518>; 152 status = "disabled"; 153 }; 154 155 hscif3: serial@e66a0000 { 156 compatible = "renesas,hscif-r8a77980", 157 "renesas,rcar-gen3-hscif", 158 "renesas,hscif"; 159 reg = <0 0xe66a0000 0 0x60>; 160 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&cpg CPG_MOD 517>, 162 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 163 <&scif_clk>; 164 clock-names = "fck", "brg_int", "scif_clk"; 165 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 166 <&dmac2 0x37>, <&dmac2 0x36>; 167 dma-names = "tx", "rx", "tx", "rx"; 168 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 169 resets = <&cpg 517>; 170 status = "disabled"; 171 }; 172 173 avb: ethernet@e6800000 { 174 compatible = "renesas,etheravb-r8a77980", 175 "renesas,etheravb-rcar-gen3"; 176 reg = <0 0xe6800000 0 0x800>; 177 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "ch0", "ch1", "ch2", "ch3", 203 "ch4", "ch5", "ch6", "ch7", 204 "ch8", "ch9", "ch10", "ch11", 205 "ch12", "ch13", "ch14", "ch15", 206 "ch16", "ch17", "ch18", "ch19", 207 "ch20", "ch21", "ch22", "ch23", 208 "ch24"; 209 clocks = <&cpg CPG_MOD 812>; 210 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 211 resets = <&cpg 812>; 212 phy-mode = "rgmii"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 }; 216 217 scif0: serial@e6e60000 { 218 compatible = "renesas,scif-r8a77980", 219 "renesas,rcar-gen3-scif", 220 "renesas,scif"; 221 reg = <0 0xe6e60000 0 0x40>; 222 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cpg CPG_MOD 207>, 224 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 225 <&scif_clk>; 226 clock-names = "fck", "brg_int", "scif_clk"; 227 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 228 <&dmac2 0x51>, <&dmac2 0x50>; 229 dma-names = "tx", "rx", "tx", "rx"; 230 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 231 resets = <&cpg 207>; 232 status = "disabled"; 233 }; 234 235 scif1: serial@e6e68000 { 236 compatible = "renesas,scif-r8a77980", 237 "renesas,rcar-gen3-scif", 238 "renesas,scif"; 239 reg = <0 0xe6e68000 0 0x40>; 240 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&cpg CPG_MOD 206>, 242 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 243 <&scif_clk>; 244 clock-names = "fck", "brg_int", "scif_clk"; 245 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 246 <&dmac2 0x53>, <&dmac2 0x52>; 247 dma-names = "tx", "rx", "tx", "rx"; 248 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 249 resets = <&cpg 206>; 250 status = "disabled"; 251 }; 252 253 scif3: serial@e6c50000 { 254 compatible = "renesas,scif-r8a77980", 255 "renesas,rcar-gen3-scif", 256 "renesas,scif"; 257 reg = <0 0xe6c50000 0 0x40>; 258 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cpg CPG_MOD 204>, 260 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 261 <&scif_clk>; 262 clock-names = "fck", "brg_int", "scif_clk"; 263 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 264 <&dmac2 0x57>, <&dmac2 0x56>; 265 dma-names = "tx", "rx", "tx", "rx"; 266 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 267 resets = <&cpg 204>; 268 status = "disabled"; 269 }; 270 271 scif4: serial@e6c40000 { 272 compatible = "renesas,scif-r8a77980", 273 "renesas,rcar-gen3-scif", 274 "renesas,scif"; 275 reg = <0 0xe6c40000 0 0x40>; 276 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&cpg CPG_MOD 203>, 278 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 279 <&scif_clk>; 280 clock-names = "fck", "brg_int", "scif_clk"; 281 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 282 <&dmac2 0x59>, <&dmac2 0x58>; 283 dma-names = "tx", "rx", "tx", "rx"; 284 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 285 resets = <&cpg 203>; 286 status = "disabled"; 287 }; 288 289 dmac1: dma-controller@e7300000 { 290 compatible = "renesas,dmac-r8a77980", 291 "renesas,rcar-dmac"; 292 reg = <0 0xe7300000 0 0x10000>; 293 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 294 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 295 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 296 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 297 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 298 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 299 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 300 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 301 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 303 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 304 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "error", 311 "ch0", "ch1", "ch2", "ch3", 312 "ch4", "ch5", "ch6", "ch7", 313 "ch8", "ch9", "ch10", "ch11", 314 "ch12", "ch13", "ch14", "ch15"; 315 clocks = <&cpg CPG_MOD 218>; 316 clock-names = "fck"; 317 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 318 resets = <&cpg 218>; 319 #dma-cells = <1>; 320 dma-channels = <16>; 321 }; 322 323 dmac2: dma-controller@e7310000 { 324 compatible = "renesas,dmac-r8a77980", 325 "renesas,rcar-dmac"; 326 reg = <0 0xe7310000 0 0x10000>; 327 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "error", 345 "ch0", "ch1", "ch2", "ch3", 346 "ch4", "ch5", "ch6", "ch7", 347 "ch8", "ch9", "ch10", "ch11", 348 "ch12", "ch13", "ch14", "ch15"; 349 clocks = <&cpg CPG_MOD 217>; 350 clock-names = "fck"; 351 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 352 resets = <&cpg 217>; 353 #dma-cells = <1>; 354 dma-channels = <16>; 355 }; 356 357 mmc0: mmc@ee140000 { 358 compatible = "renesas,sdhi-r8a77980", 359 "renesas,rcar-gen3-sdhi"; 360 reg = <0 0xee140000 0 0x2000>; 361 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cpg CPG_MOD 314>; 363 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 364 resets = <&cpg 314>; 365 max-frequency = <200000000>; 366 status = "disabled"; 367 }; 368 369 gic: interrupt-controller@f1010000 { 370 compatible = "arm,gic-400"; 371 #interrupt-cells = <3>; 372 #address-cells = <0>; 373 interrupt-controller; 374 reg = <0x0 0xf1010000 0 0x1000>, 375 <0x0 0xf1020000 0 0x20000>, 376 <0x0 0xf1040000 0 0x20000>, 377 <0x0 0xf1060000 0 0x20000>; 378 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 379 IRQ_TYPE_LEVEL_HIGH)>; 380 clocks = <&cpg CPG_MOD 408>; 381 clock-names = "clk"; 382 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 383 resets = <&cpg 408>; 384 }; 385 386 prr: chipid@fff00044 { 387 compatible = "renesas,prr"; 388 reg = <0 0xfff00044 0 4>; 389 }; 390 }; 391 392 timer { 393 compatible = "arm,armv8-timer"; 394 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 395 IRQ_TYPE_LEVEL_LOW)>, 396 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 397 IRQ_TYPE_LEVEL_LOW)>, 398 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 399 IRQ_TYPE_LEVEL_LOW)>, 400 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 401 IRQ_TYPE_LEVEL_LOW)>; 402 }; 403}; 404