r8a77980.dtsi (87bea6780b952dac7f58ed2395d2eaa434deb0fb) r8a77980.dtsi (bc620474c6e283c0e1e60796ed0ac9b04da9890c)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/power/r8a77980-sysc.h>
13
14/ {
15 compatible = "renesas,r8a77980";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/power/r8a77980-sysc.h>
13
14/ {
15 compatible = "renesas,r8a77980";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 };
27
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 a53_0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a53", "arm,armv8";
26 reg = <0>;

--- 103 unchanged lines hidden (view full) ---

130 };
131
132 sysc: system-controller@e6180000 {
133 compatible = "renesas,r8a77980-sysc";
134 reg = <0 0xe6180000 0 0x440>;
135 #power-domain-cells = <1>;
136 };
137
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 a53_0: cpu@0 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a53", "arm,armv8";
35 reg = <0>;

--- 103 unchanged lines hidden (view full) ---

139 };
140
141 sysc: system-controller@e6180000 {
142 compatible = "renesas,r8a77980-sysc";
143 reg = <0 0xe6180000 0 0x440>;
144 #power-domain-cells = <1>;
145 };
146
147 i2c0: i2c@e6500000 {
148 compatible = "renesas,i2c-r8a77980",
149 "renesas,rcar-gen3-i2c";
150 reg = <0 0xe6500000 0 0x40>;
151 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cpg CPG_MOD 931>;
153 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
154 resets = <&cpg 931>;
155 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
156 <&dmac2 0x91>, <&dmac2 0x90>;
157 dma-names = "tx", "rx", "tx", "rx";
158 i2c-scl-internal-delay-ns = <6>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 status = "disabled";
162 };
163
164 i2c1: i2c@e6508000 {
165 compatible = "renesas,i2c-r8a77980",
166 "renesas,rcar-gen3-i2c";
167 reg = <0 0xe6508000 0 0x40>;
168 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&cpg CPG_MOD 930>;
170 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
171 resets = <&cpg 930>;
172 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
173 <&dmac2 0x93>, <&dmac2 0x92>;
174 dma-names = "tx", "rx", "tx", "rx";
175 i2c-scl-internal-delay-ns = <6>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 status = "disabled";
179 };
180
181 i2c2: i2c@e6510000 {
182 compatible = "renesas,i2c-r8a77980",
183 "renesas,rcar-gen3-i2c";
184 reg = <0 0xe6510000 0 0x40>;
185 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cpg CPG_MOD 929>;
187 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
188 resets = <&cpg 929>;
189 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
190 <&dmac2 0x95>, <&dmac2 0x94>;
191 dma-names = "tx", "rx", "tx", "rx";
192 i2c-scl-internal-delay-ns = <6>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 status = "disabled";
196 };
197
198 i2c3: i2c@e66d0000 {
199 compatible = "renesas,i2c-r8a77980",
200 "renesas,rcar-gen3-i2c";
201 reg = <0 0xe66d0000 0 0x40>;
202 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cpg CPG_MOD 928>;
204 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
205 resets = <&cpg 928>;
206 i2c-scl-internal-delay-ns = <6>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 status = "disabled";
210 };
211
212 i2c4: i2c@e66d8000 {
213 compatible = "renesas,i2c-r8a77980",
214 "renesas,rcar-gen3-i2c";
215 reg = <0 0xe66d8000 0 0x40>;
216 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cpg CPG_MOD 927>;
218 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
219 resets = <&cpg 927>;
220 i2c-scl-internal-delay-ns = <6>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 status = "disabled";
224 };
225
226 i2c5: i2c@e66e0000 {
227 compatible = "renesas,i2c-r8a77980",
228 "renesas,rcar-gen3-i2c";
229 reg = <0 0xe66e0000 0 0x40>;
230 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&cpg CPG_MOD 919>;
232 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
233 resets = <&cpg 919>;
234 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
235 <&dmac2 0x9b>, <&dmac2 0x9a>;
236 dma-names = "tx", "rx", "tx", "rx";
237 i2c-scl-internal-delay-ns = <6>;
238 #address-cells = <1>;
239 #size-cells = <0>;
240 status = "disabled";
241 };
242
138 hscif0: serial@e6540000 {
139 compatible = "renesas,hscif-r8a77980",
140 "renesas,rcar-gen3-hscif",
141 "renesas,hscif";
142 reg = <0 0xe6540000 0 0x60>;
143 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cpg CPG_MOD 520>,
145 <&cpg CPG_CORE R8A77980_CLK_S3D1>,

--- 333 unchanged lines hidden --- 		243 hscif0: serial@e6540000 {
244 compatible = "renesas,hscif-r8a77980",
245 "renesas,rcar-gen3-hscif",
246 "renesas,hscif";
247 reg = <0 0xe6540000 0 0x60>;
248 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&cpg CPG_MOD 520>,
250 <&cpg CPG_CORE R8A77980_CLK_S3D1>,

--- 333 unchanged lines hidden ---