1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a77980 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 a53_0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a53", "arm,armv8"; 26 reg = <0>; 27 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 28 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 29 next-level-cache = <&L2_CA53>; 30 enable-method = "psci"; 31 }; 32 33 a53_1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <1>; 37 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 38 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 39 next-level-cache = <&L2_CA53>; 40 enable-method = "psci"; 41 }; 42 43 a53_2: cpu@2 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53", "arm,armv8"; 46 reg = <2>; 47 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 48 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 49 next-level-cache = <&L2_CA53>; 50 enable-method = "psci"; 51 }; 52 53 a53_3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53", "arm,armv8"; 56 reg = <3>; 57 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 58 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 59 next-level-cache = <&L2_CA53>; 60 enable-method = "psci"; 61 }; 62 63 L2_CA53: cache-controller { 64 compatible = "cache"; 65 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 66 cache-unified; 67 cache-level = <2>; 68 }; 69 }; 70 71 /* External CAN clock - to be overridden by boards that provide it */ 72 can_clk: can { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <0>; 76 }; 77 78 extal_clk: extal { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 /* This value must be overridden by the board */ 82 clock-frequency = <0>; 83 }; 84 85 extalr_clk: extalr { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 /* This value must be overridden by the board */ 89 clock-frequency = <0>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0", "arm,psci-0.2"; 94 method = "smc"; 95 }; 96 97 /* External SCIF clock - to be overridden by boards that provide it */ 98 scif_clk: scif { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <0>; 102 }; 103 104 soc { 105 compatible = "simple-bus"; 106 interrupt-parent = <&gic>; 107 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges; 111 112 pfc: pin-controller@e6060000 { 113 compatible = "renesas,pfc-r8a77980"; 114 reg = <0 0xe6060000 0 0x50c>; 115 }; 116 117 cpg: clock-controller@e6150000 { 118 compatible = "renesas,r8a77980-cpg-mssr"; 119 reg = <0 0xe6150000 0 0x1000>; 120 clocks = <&extal_clk>, <&extalr_clk>; 121 clock-names = "extal", "extalr"; 122 #clock-cells = <2>; 123 #power-domain-cells = <0>; 124 #reset-cells = <1>; 125 }; 126 127 rst: reset-controller@e6160000 { 128 compatible = "renesas,r8a77980-rst"; 129 reg = <0 0xe6160000 0 0x200>; 130 }; 131 132 sysc: system-controller@e6180000 { 133 compatible = "renesas,r8a77980-sysc"; 134 reg = <0 0xe6180000 0 0x440>; 135 #power-domain-cells = <1>; 136 }; 137 138 hscif0: serial@e6540000 { 139 compatible = "renesas,hscif-r8a77980", 140 "renesas,rcar-gen3-hscif", 141 "renesas,hscif"; 142 reg = <0 0xe6540000 0 0x60>; 143 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&cpg CPG_MOD 520>, 145 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 146 <&scif_clk>; 147 clock-names = "fck", "brg_int", "scif_clk"; 148 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 149 <&dmac2 0x31>, <&dmac2 0x30>; 150 dma-names = "tx", "rx", "tx", "rx"; 151 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 152 resets = <&cpg 520>; 153 status = "disabled"; 154 }; 155 156 hscif1: serial@e6550000 { 157 compatible = "renesas,hscif-r8a77980", 158 "renesas,rcar-gen3-hscif", 159 "renesas,hscif"; 160 reg = <0 0xe6550000 0 0x60>; 161 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cpg CPG_MOD 519>, 163 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 164 <&scif_clk>; 165 clock-names = "fck", "brg_int", "scif_clk"; 166 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 167 <&dmac2 0x33>, <&dmac2 0x32>; 168 dma-names = "tx", "rx", "tx", "rx"; 169 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 170 resets = <&cpg 519>; 171 status = "disabled"; 172 }; 173 174 hscif2: serial@e6560000 { 175 compatible = "renesas,hscif-r8a77980", 176 "renesas,rcar-gen3-hscif", 177 "renesas,hscif"; 178 reg = <0 0xe6560000 0 0x60>; 179 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cpg CPG_MOD 518>, 181 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 182 <&scif_clk>; 183 clock-names = "fck", "brg_int", "scif_clk"; 184 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 185 <&dmac2 0x35>, <&dmac2 0x34>; 186 dma-names = "tx", "rx", "tx", "rx"; 187 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 188 resets = <&cpg 518>; 189 status = "disabled"; 190 }; 191 192 hscif3: serial@e66a0000 { 193 compatible = "renesas,hscif-r8a77980", 194 "renesas,rcar-gen3-hscif", 195 "renesas,hscif"; 196 reg = <0 0xe66a0000 0 0x60>; 197 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&cpg CPG_MOD 517>, 199 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 200 <&scif_clk>; 201 clock-names = "fck", "brg_int", "scif_clk"; 202 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 203 <&dmac2 0x37>, <&dmac2 0x36>; 204 dma-names = "tx", "rx", "tx", "rx"; 205 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 206 resets = <&cpg 517>; 207 status = "disabled"; 208 }; 209 210 canfd: can@e66c0000 { 211 compatible = "renesas,r8a77980-canfd", 212 "renesas,rcar-gen3-canfd"; 213 reg = <0 0xe66c0000 0 0x8000>; 214 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cpg CPG_MOD 914>, 217 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 218 <&can_clk>; 219 clock-names = "fck", "canfd", "can_clk"; 220 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 221 assigned-clock-rates = <40000000>; 222 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 223 resets = <&cpg 914>; 224 status = "disabled"; 225 226 channel0 { 227 status = "disabled"; 228 }; 229 230 channel1 { 231 status = "disabled"; 232 }; 233 }; 234 235 avb: ethernet@e6800000 { 236 compatible = "renesas,etheravb-r8a77980", 237 "renesas,etheravb-rcar-gen3"; 238 reg = <0 0xe6800000 0 0x800>; 239 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 264 interrupt-names = "ch0", "ch1", "ch2", "ch3", 265 "ch4", "ch5", "ch6", "ch7", 266 "ch8", "ch9", "ch10", "ch11", 267 "ch12", "ch13", "ch14", "ch15", 268 "ch16", "ch17", "ch18", "ch19", 269 "ch20", "ch21", "ch22", "ch23", 270 "ch24"; 271 clocks = <&cpg CPG_MOD 812>; 272 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 273 resets = <&cpg 812>; 274 phy-mode = "rgmii"; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 status = "disabled"; 278 }; 279 280 scif0: serial@e6e60000 { 281 compatible = "renesas,scif-r8a77980", 282 "renesas,rcar-gen3-scif", 283 "renesas,scif"; 284 reg = <0 0xe6e60000 0 0x40>; 285 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 207>, 287 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 288 <&scif_clk>; 289 clock-names = "fck", "brg_int", "scif_clk"; 290 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 291 <&dmac2 0x51>, <&dmac2 0x50>; 292 dma-names = "tx", "rx", "tx", "rx"; 293 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 294 resets = <&cpg 207>; 295 status = "disabled"; 296 }; 297 298 scif1: serial@e6e68000 { 299 compatible = "renesas,scif-r8a77980", 300 "renesas,rcar-gen3-scif", 301 "renesas,scif"; 302 reg = <0 0xe6e68000 0 0x40>; 303 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cpg CPG_MOD 206>, 305 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 306 <&scif_clk>; 307 clock-names = "fck", "brg_int", "scif_clk"; 308 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 309 <&dmac2 0x53>, <&dmac2 0x52>; 310 dma-names = "tx", "rx", "tx", "rx"; 311 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 312 resets = <&cpg 206>; 313 status = "disabled"; 314 }; 315 316 scif3: serial@e6c50000 { 317 compatible = "renesas,scif-r8a77980", 318 "renesas,rcar-gen3-scif", 319 "renesas,scif"; 320 reg = <0 0xe6c50000 0 0x40>; 321 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cpg CPG_MOD 204>, 323 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 324 <&scif_clk>; 325 clock-names = "fck", "brg_int", "scif_clk"; 326 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 327 <&dmac2 0x57>, <&dmac2 0x56>; 328 dma-names = "tx", "rx", "tx", "rx"; 329 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 330 resets = <&cpg 204>; 331 status = "disabled"; 332 }; 333 334 scif4: serial@e6c40000 { 335 compatible = "renesas,scif-r8a77980", 336 "renesas,rcar-gen3-scif", 337 "renesas,scif"; 338 reg = <0 0xe6c40000 0 0x40>; 339 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 203>, 341 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 342 <&scif_clk>; 343 clock-names = "fck", "brg_int", "scif_clk"; 344 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 345 <&dmac2 0x59>, <&dmac2 0x58>; 346 dma-names = "tx", "rx", "tx", "rx"; 347 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 348 resets = <&cpg 203>; 349 status = "disabled"; 350 }; 351 352 dmac1: dma-controller@e7300000 { 353 compatible = "renesas,dmac-r8a77980", 354 "renesas,rcar-dmac"; 355 reg = <0 0xe7300000 0 0x10000>; 356 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 357 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 358 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 359 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 360 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 361 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 362 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-names = "error", 374 "ch0", "ch1", "ch2", "ch3", 375 "ch4", "ch5", "ch6", "ch7", 376 "ch8", "ch9", "ch10", "ch11", 377 "ch12", "ch13", "ch14", "ch15"; 378 clocks = <&cpg CPG_MOD 218>; 379 clock-names = "fck"; 380 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 381 resets = <&cpg 218>; 382 #dma-cells = <1>; 383 dma-channels = <16>; 384 }; 385 386 dmac2: dma-controller@e7310000 { 387 compatible = "renesas,dmac-r8a77980", 388 "renesas,rcar-dmac"; 389 reg = <0 0xe7310000 0 0x10000>; 390 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 391 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 392 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 394 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 395 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 396 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 397 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 399 GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 400 GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 401 GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 402 GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 403 GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 404 GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 405 GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 406 GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "error", 408 "ch0", "ch1", "ch2", "ch3", 409 "ch4", "ch5", "ch6", "ch7", 410 "ch8", "ch9", "ch10", "ch11", 411 "ch12", "ch13", "ch14", "ch15"; 412 clocks = <&cpg CPG_MOD 217>; 413 clock-names = "fck"; 414 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 415 resets = <&cpg 217>; 416 #dma-cells = <1>; 417 dma-channels = <16>; 418 }; 419 420 gether: ethernet@e7400000 { 421 compatible = "renesas,gether-r8a77980"; 422 reg = <0 0xe7400000 0 0x1000>; 423 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&cpg CPG_MOD 813>; 425 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 426 resets = <&cpg 813>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 mmc0: mmc@ee140000 { 433 compatible = "renesas,sdhi-r8a77980", 434 "renesas,rcar-gen3-sdhi"; 435 reg = <0 0xee140000 0 0x2000>; 436 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cpg CPG_MOD 314>; 438 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 439 resets = <&cpg 314>; 440 max-frequency = <200000000>; 441 status = "disabled"; 442 }; 443 444 gic: interrupt-controller@f1010000 { 445 compatible = "arm,gic-400"; 446 #interrupt-cells = <3>; 447 #address-cells = <0>; 448 interrupt-controller; 449 reg = <0x0 0xf1010000 0 0x1000>, 450 <0x0 0xf1020000 0 0x20000>, 451 <0x0 0xf1040000 0 0x20000>, 452 <0x0 0xf1060000 0 0x20000>; 453 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 454 IRQ_TYPE_LEVEL_HIGH)>; 455 clocks = <&cpg CPG_MOD 408>; 456 clock-names = "clk"; 457 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 458 resets = <&cpg 408>; 459 }; 460 461 prr: chipid@fff00044 { 462 compatible = "renesas,prr"; 463 reg = <0 0xfff00044 0 4>; 464 }; 465 }; 466 467 timer { 468 compatible = "arm,armv8-timer"; 469 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 470 IRQ_TYPE_LEVEL_LOW)>, 471 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 472 IRQ_TYPE_LEVEL_LOW)>, 473 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 474 IRQ_TYPE_LEVEL_LOW)>, 475 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 476 IRQ_TYPE_LEVEL_LOW)>; 477 }; 478}; 479