r8a77980.dtsi (1184ea3fd4c83a7bf6a8f51fcf73d620706557ce) r8a77980.dtsi (f38c41727211f2cdd9bb6f2999d46daafeacc5aa)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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33 L2_CA53: cache-controller {
34 compatible = "cache";
35 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
36 cache-unified;
37 cache-level = <2>;
38 };
39 };
40
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a77980 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8

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33 L2_CA53: cache-controller {
34 compatible = "cache";
35 power-domains = <&sysc R8A77980_PD_CA53_SCU>;
36 cache-unified;
37 cache-level = <2>;
38 };
39 };
40
41 /* External CAN clock - to be overridden by boards that provide it */
42 can_clk: can {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
46 };
47
41 extal_clk: extal {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 /* This value must be overridden by the board */
45 clock-frequency = <0>;
46 };
47
48 extalr_clk: extalr {

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165 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
166 <&dmac2 0x37>, <&dmac2 0x36>;
167 dma-names = "tx", "rx", "tx", "rx";
168 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
169 resets = <&cpg 517>;
170 status = "disabled";
171 };
172
48 extal_clk: extal {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 /* This value must be overridden by the board */
52 clock-frequency = <0>;
53 };
54
55 extalr_clk: extalr {

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172 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
173 <&dmac2 0x37>, <&dmac2 0x36>;
174 dma-names = "tx", "rx", "tx", "rx";
175 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
176 resets = <&cpg 517>;
177 status = "disabled";
178 };
179
180 canfd: can@e66c0000 {
181 compatible = "renesas,r8a77980-canfd",
182 "renesas,rcar-gen3-canfd";
183 reg = <0 0xe66c0000 0 0x8000>;
184 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&cpg CPG_MOD 914>,
187 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
188 <&can_clk>;
189 clock-names = "fck", "canfd", "can_clk";
190 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
191 assigned-clock-rates = <40000000>;
192 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
193 status = "disabled";
194
195 channel0 {
196 status = "disabled";
197 };
198
199 channel1 {
200 status = "disabled";
201 };
202 };
203
173 avb: ethernet@e6800000 {
174 compatible = "renesas,etheravb-r8a77980",
175 "renesas,etheravb-rcar-gen3";
176 reg = <0 0xe6800000 0 0x800>;
177 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

--- 223 unchanged lines hidden --- 		204 avb: ethernet@e6800000 {
205 compatible = "renesas,etheravb-r8a77980",
206 "renesas,etheravb-rcar-gen3";
207 reg = <0 0xe6800000 0 0x800>;
208 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

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