r8a77961.dtsi (aa10fab0f859ef86e998ee1cdaa89fc8e542e2c9) r8a77961.dtsi (44b615ac9fab16d1552cd8360454077d411e3c35)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <820000>;
61 clock-latency-ns = <300000>;
62 };
63 opp-1500000000 {
64 opp-hz = /bits/ 64 <1500000000>;
65 opp-microvolt = <820000>;
66 clock-latency-ns = <300000>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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59 opp-hz = /bits/ 64 <1000000000>;
60 opp-microvolt = <820000>;
61 clock-latency-ns = <300000>;
62 };
63 opp-1500000000 {
64 opp-hz = /bits/ 64 <1500000000>;
65 opp-microvolt = <820000>;
66 clock-latency-ns = <300000>;
67 opp-suspend;
67 };
68 opp-1600000000 {
69 opp-hz = /bits/ 64 <1600000000>;
70 opp-microvolt = <900000>;
71 clock-latency-ns = <300000>;
72 turbo-mode;
73 };
74 opp-1700000000 {

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1139 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1140 "ch4", "ch5", "ch6", "ch7",
1141 "ch8", "ch9", "ch10", "ch11",
1142 "ch12", "ch13", "ch14", "ch15",
1143 "ch16", "ch17", "ch18", "ch19",
1144 "ch20", "ch21", "ch22", "ch23",
1145 "ch24";
1146 clocks = <&cpg CPG_MOD 812>;
68 };
69 opp-1600000000 {
70 opp-hz = /bits/ 64 <1600000000>;
71 opp-microvolt = <900000>;
72 clock-latency-ns = <300000>;
73 turbo-mode;
74 };
75 opp-1700000000 {

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1140 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1141 "ch4", "ch5", "ch6", "ch7",
1142 "ch8", "ch9", "ch10", "ch11",
1143 "ch12", "ch13", "ch14", "ch15",
1144 "ch16", "ch17", "ch18", "ch19",
1145 "ch20", "ch21", "ch22", "ch23",
1146 "ch24";
1147 clocks = <&cpg CPG_MOD 812>;
1148 clock-names = "fck";
1147 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1148 resets = <&cpg 812>;
1149 phy-mode = "rgmii";
1150 rx-internal-delay-ps = <0>;
1151 tx-internal-delay-ps = <0>;
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154 status = "disabled";

--- 1612 unchanged lines hidden --- 		1149 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1150 resets = <&cpg 812>;
1151 phy-mode = "rgmii";
1152 rx-internal-delay-ps = <0>;
1153 tx-internal-delay-ps = <0>;
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1156 status = "disabled";

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