r8a77961.dtsi (8ab47ffc8d5d8df240ea56cdc5da9c6606dd7c36) r8a77961.dtsi (3971a7734862570a75a88d52b3906751421b899b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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621 clocks = <&cpg CPG_MOD 926>;
622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
623 resets = <&cpg 926>;
624 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
625 dma-names = "tx", "rx";
626 status = "disabled";
627 };
628
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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621 clocks = <&cpg CPG_MOD 926>;
622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
623 resets = <&cpg 926>;
624 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
625 dma-names = "tx", "rx";
626 status = "disabled";
627 };
628
629 hscif0: serial@e6540000 {
630 compatible = "renesas,hscif-r8a77961",
631 "renesas,rcar-gen3-hscif",
632 "renesas,hscif";
633 reg = <0 0xe6540000 0 0x60>;
634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cpg CPG_MOD 520>,
636 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
637 <&scif_clk>;
638 clock-names = "fck", "brg_int", "scif_clk";
639 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
640 <&dmac2 0x31>, <&dmac2 0x30>;
641 dma-names = "tx", "rx", "tx", "rx";
642 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
643 resets = <&cpg 520>;
644 status = "disabled";
645 };
629
630 hscif1: serial@e6550000 {
646
647 hscif1: serial@e6550000 {
648 compatible = "renesas,hscif-r8a77961",
649 "renesas,rcar-gen3-hscif",
650 "renesas,hscif";
631 reg = <0 0xe6550000 0 0x60>;
651 reg = <0 0xe6550000 0 0x60>;
632 /* placeholder */
652 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cpg CPG_MOD 519>,
654 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
655 <&scif_clk>;
656 clock-names = "fck", "brg_int", "scif_clk";
657 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
658 <&dmac2 0x33>, <&dmac2 0x32>;
659 dma-names = "tx", "rx", "tx", "rx";
660 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
661 resets = <&cpg 519>;
662 status = "disabled";
633 };
634
663 };
664
665 hscif2: serial@e6560000 {
666 compatible = "renesas,hscif-r8a77961",
667 "renesas,rcar-gen3-hscif",
668 "renesas,hscif";
669 reg = <0 0xe6560000 0 0x60>;
670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 518>,
672 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
673 <&scif_clk>;
674 clock-names = "fck", "brg_int", "scif_clk";
675 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
676 <&dmac2 0x35>, <&dmac2 0x34>;
677 dma-names = "tx", "rx", "tx", "rx";
678 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
679 resets = <&cpg 518>;
680 status = "disabled";
681 };
682
683 hscif3: serial@e66a0000 {
684 compatible = "renesas,hscif-r8a77961",
685 "renesas,rcar-gen3-hscif",
686 "renesas,hscif";
687 reg = <0 0xe66a0000 0 0x60>;
688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cpg CPG_MOD 517>,
690 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
691 <&scif_clk>;
692 clock-names = "fck", "brg_int", "scif_clk";
693 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
694 dma-names = "tx", "rx";
695 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
696 resets = <&cpg 517>;
697 status = "disabled";
698 };
699
700 hscif4: serial@e66b0000 {
701 compatible = "renesas,hscif-r8a77961",
702 "renesas,rcar-gen3-hscif",
703 "renesas,hscif";
704 reg = <0 0xe66b0000 0 0x60>;
705 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 516>,
707 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
708 <&scif_clk>;
709 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
711 dma-names = "tx", "rx";
712 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
713 resets = <&cpg 516>;
714 status = "disabled";
715 };
716
635 hsusb: usb@e6590000 {
636 compatible = "renesas,usbhs-r8a77961",
637 "renesas,rcar-gen3-usbhs";
638 reg = <0 0xe6590000 0 0x200>;
639 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
641 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
642 <&usb_dmac1 0>, <&usb_dmac1 1>;

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847 };
848
849 pwm1: pwm@e6e31000 {
850 reg = <0 0xe6e31000 0 8>;
851 #pwm-cells = <2>;
852 /* placeholder */
853 };
854
717 hsusb: usb@e6590000 {
718 compatible = "renesas,usbhs-r8a77961",
719 "renesas,rcar-gen3-usbhs";
720 reg = <0 0xe6590000 0 0x200>;
721 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
723 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
724 <&usb_dmac1 0>, <&usb_dmac1 1>;

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929 };
930
931 pwm1: pwm@e6e31000 {
932 reg = <0 0xe6e31000 0 8>;
933 #pwm-cells = <2>;
934 /* placeholder */
935 };
936
937 scif0: serial@e6e60000 {
938 compatible = "renesas,scif-r8a77961",
939 "renesas,rcar-gen3-scif", "renesas,scif";
940 reg = <0 0xe6e60000 0 64>;
941 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&cpg CPG_MOD 207>,
943 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
944 <&scif_clk>;
945 clock-names = "fck", "brg_int", "scif_clk";
946 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
947 <&dmac2 0x51>, <&dmac2 0x50>;
948 dma-names = "tx", "rx", "tx", "rx";
949 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
950 resets = <&cpg 207>;
951 status = "disabled";
952 };
953
855 scif1: serial@e6e68000 {
954 scif1: serial@e6e68000 {
955 compatible = "renesas,scif-r8a77961",
956 "renesas,rcar-gen3-scif", "renesas,scif";
856 reg = <0 0xe6e68000 0 64>;
957 reg = <0 0xe6e68000 0 64>;
857 /* placeholder */
958 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&cpg CPG_MOD 206>,
960 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
961 <&scif_clk>;
962 clock-names = "fck", "brg_int", "scif_clk";
963 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
964 <&dmac2 0x53>, <&dmac2 0x52>;
965 dma-names = "tx", "rx", "tx", "rx";
966 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
967 resets = <&cpg 206>;
968 status = "disabled";
858 };
859
860 scif2: serial@e6e88000 {
861 compatible = "renesas,scif-r8a77961",
862 "renesas,rcar-gen3-scif", "renesas,scif";
863 reg = <0 0xe6e88000 0 64>;
864 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cpg CPG_MOD 310>,
866 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
867 <&scif_clk>;
868 clock-names = "fck", "brg_int", "scif_clk";
969 };
970
971 scif2: serial@e6e88000 {
972 compatible = "renesas,scif-r8a77961",
973 "renesas,rcar-gen3-scif", "renesas,scif";
974 reg = <0 0xe6e88000 0 64>;
975 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&cpg CPG_MOD 310>,
977 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
978 <&scif_clk>;
979 clock-names = "fck", "brg_int", "scif_clk";
980 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
981 <&dmac2 0x13>, <&dmac2 0x12>;
982 dma-names = "tx", "rx", "tx", "rx";
869 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
870 resets = <&cpg 310>;
871 status = "disabled";
872 };
873
983 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
984 resets = <&cpg 310>;
985 status = "disabled";
986 };
987
988 scif3: serial@e6c50000 {
989 compatible = "renesas,scif-r8a77961",
990 "renesas,rcar-gen3-scif", "renesas,scif";
991 reg = <0 0xe6c50000 0 64>;
992 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&cpg CPG_MOD 204>,
994 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
995 <&scif_clk>;
996 clock-names = "fck", "brg_int", "scif_clk";
997 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
998 dma-names = "tx", "rx";
999 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1000 resets = <&cpg 204>;
1001 status = "disabled";
1002 };
1003
1004 scif4: serial@e6c40000 {
1005 compatible = "renesas,scif-r8a77961",
1006 "renesas,rcar-gen3-scif", "renesas,scif";
1007 reg = <0 0xe6c40000 0 64>;
1008 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&cpg CPG_MOD 203>,
1010 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
1011 <&scif_clk>;
1012 clock-names = "fck", "brg_int", "scif_clk";
1013 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1014 dma-names = "tx", "rx";
1015 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1016 resets = <&cpg 203>;
1017 status = "disabled";
1018 };
1019
1020 scif5: serial@e6f30000 {
1021 compatible = "renesas,scif-r8a77961",
1022 "renesas,rcar-gen3-scif", "renesas,scif";
1023 reg = <0 0xe6f30000 0 64>;
1024 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&cpg CPG_MOD 202>,
1026 <&cpg CPG_CORE R8A77961_CLK_S3D1>,
1027 <&scif_clk>;
1028 clock-names = "fck", "brg_int", "scif_clk";
1029 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1030 <&dmac2 0x5b>, <&dmac2 0x5a>;
1031 dma-names = "tx", "rx", "tx", "rx";
1032 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1033 resets = <&cpg 202>;
1034 status = "disabled";
1035 };
1036
874 vin0: video@e6ef0000 {
875 reg = <0 0xe6ef0000 0 0x1000>;
876 /* placeholder */
877 };
878
879 vin1: video@e6ef1000 {
880 reg = <0 0xe6ef1000 0 0x1000>;
881 /* placeholder */

--- 397 unchanged lines hidden --- 		1037 vin0: video@e6ef0000 {
1038 reg = <0 0xe6ef0000 0 0x1000>;
1039 /* placeholder */
1040 };
1041
1042 vin1: video@e6ef1000 {
1043 reg = <0 0xe6ef1000 0 0x1000>;
1044 /* placeholder */

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