r8a77961.dtsi (5edf8bd6f4a225f7ad0501f921f9717df152e7fb) r8a77961.dtsi (4e4c17c6c3907dfc34051cc450a78a38fb371b4f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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560
561 intc_ex: interrupt-controller@e61c0000 {
562 #interrupt-cells = <2>;
563 interrupt-controller;
564 reg = <0 0xe61c0000 0 0x200>;
565 /* placeholder */
566 };
567
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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560
561 intc_ex: interrupt-controller@e61c0000 {
562 #interrupt-cells = <2>;
563 interrupt-controller;
564 reg = <0 0xe61c0000 0 0x200>;
565 /* placeholder */
566 };
567
568 tmu0: timer@e61e0000 {
569 compatible = "renesas,tmu-r8a77961", "renesas,tmu";
570 reg = <0 0xe61e0000 0 0x30>;
571 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 125>;
575 clock-names = "fck";
576 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
577 resets = <&cpg 125>;
578 status = "disabled";
579 };
580
581 tmu1: timer@e6fc0000 {
582 compatible = "renesas,tmu-r8a77961", "renesas,tmu";
583 reg = <0 0xe6fc0000 0 0x30>;
584 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 124>;
588 clock-names = "fck";
589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
590 resets = <&cpg 124>;
591 status = "disabled";
592 };
593
594 tmu2: timer@e6fd0000 {
595 compatible = "renesas,tmu-r8a77961", "renesas,tmu";
596 reg = <0 0xe6fd0000 0 0x30>;
597 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&cpg CPG_MOD 123>;
601 clock-names = "fck";
602 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
603 resets = <&cpg 123>;
604 status = "disabled";
605 };
606
607 tmu3: timer@e6fe0000 {
608 compatible = "renesas,tmu-r8a77961", "renesas,tmu";
609 reg = <0 0xe6fe0000 0 0x30>;
610 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cpg CPG_MOD 122>;
614 clock-names = "fck";
615 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
616 resets = <&cpg 122>;
617 status = "disabled";
618 };
619
620 tmu4: timer@ffc00000 {
621 compatible = "renesas,tmu-r8a77961", "renesas,tmu";
622 reg = <0 0xffc00000 0 0x30>;
623 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&cpg CPG_MOD 121>;
627 clock-names = "fck";
628 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
629 resets = <&cpg 121>;
630 status = "disabled";
631 };
632
568 i2c0: i2c@e6500000 {
569 #address-cells = <1>;
570 #size-cells = <0>;
571 compatible = "renesas,i2c-r8a77961",
572 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6500000 0 0x40>;
574 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 931>;

--- 1802 unchanged lines hidden --- 		633 i2c0: i2c@e6500000 {
634 #address-cells = <1>;
635 #size-cells = <0>;
636 compatible = "renesas,i2c-r8a77961",
637 "renesas,rcar-gen3-i2c";
638 reg = <0 0xe6500000 0 0x40>;
639 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 931>;

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