1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cmt0: timer@e60f0000 { 457 compatible = "renesas,r8a77961-cmt0", 458 "renesas,rcar-gen3-cmt0"; 459 reg = <0 0xe60f0000 0 0x1004>; 460 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cpg CPG_MOD 303>; 463 clock-names = "fck"; 464 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 465 resets = <&cpg 303>; 466 status = "disabled"; 467 }; 468 469 cmt1: timer@e6130000 { 470 compatible = "renesas,r8a77961-cmt1", 471 "renesas,rcar-gen3-cmt1"; 472 reg = <0 0xe6130000 0 0x1004>; 473 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD 302>; 482 clock-names = "fck"; 483 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 484 resets = <&cpg 302>; 485 status = "disabled"; 486 }; 487 488 cmt2: timer@e6140000 { 489 compatible = "renesas,r8a77961-cmt1", 490 "renesas,rcar-gen3-cmt1"; 491 reg = <0 0xe6140000 0 0x1004>; 492 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cpg CPG_MOD 301>; 501 clock-names = "fck"; 502 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 503 resets = <&cpg 301>; 504 status = "disabled"; 505 }; 506 507 cmt3: timer@e6148000 { 508 compatible = "renesas,r8a77961-cmt1", 509 "renesas,rcar-gen3-cmt1"; 510 reg = <0 0xe6148000 0 0x1004>; 511 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_MOD 300>; 520 clock-names = "fck"; 521 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 522 resets = <&cpg 300>; 523 status = "disabled"; 524 }; 525 526 cpg: clock-controller@e6150000 { 527 compatible = "renesas,r8a77961-cpg-mssr"; 528 reg = <0 0xe6150000 0 0x1000>; 529 clocks = <&extal_clk>, <&extalr_clk>; 530 clock-names = "extal", "extalr"; 531 #clock-cells = <2>; 532 #power-domain-cells = <0>; 533 #reset-cells = <1>; 534 }; 535 536 rst: reset-controller@e6160000 { 537 compatible = "renesas,r8a77961-rst"; 538 reg = <0 0xe6160000 0 0x0200>; 539 }; 540 541 sysc: system-controller@e6180000 { 542 compatible = "renesas,r8a77961-sysc"; 543 reg = <0 0xe6180000 0 0x0400>; 544 #power-domain-cells = <1>; 545 }; 546 547 tsc: thermal@e6198000 { 548 compatible = "renesas,r8a77961-thermal"; 549 reg = <0 0xe6198000 0 0x100>, 550 <0 0xe61a0000 0 0x100>, 551 <0 0xe61a8000 0 0x100>; 552 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 522>; 556 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 557 resets = <&cpg 522>; 558 #thermal-sensor-cells = <1>; 559 }; 560 561 intc_ex: interrupt-controller@e61c0000 { 562 #interrupt-cells = <2>; 563 interrupt-controller; 564 reg = <0 0xe61c0000 0 0x200>; 565 /* placeholder */ 566 }; 567 568 i2c0: i2c@e6500000 { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 compatible = "renesas,i2c-r8a77961", 572 "renesas,rcar-gen3-i2c"; 573 reg = <0 0xe6500000 0 0x40>; 574 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&cpg CPG_MOD 931>; 576 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 577 resets = <&cpg 931>; 578 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 579 <&dmac2 0x91>, <&dmac2 0x90>; 580 dma-names = "tx", "rx", "tx", "rx"; 581 i2c-scl-internal-delay-ns = <110>; 582 status = "disabled"; 583 }; 584 585 i2c1: i2c@e6508000 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 compatible = "renesas,i2c-r8a77961", 589 "renesas,rcar-gen3-i2c"; 590 reg = <0 0xe6508000 0 0x40>; 591 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cpg CPG_MOD 930>; 593 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 594 resets = <&cpg 930>; 595 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 596 <&dmac2 0x93>, <&dmac2 0x92>; 597 dma-names = "tx", "rx", "tx", "rx"; 598 i2c-scl-internal-delay-ns = <6>; 599 status = "disabled"; 600 }; 601 602 i2c2: i2c@e6510000 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 compatible = "renesas,i2c-r8a77961", 606 "renesas,rcar-gen3-i2c"; 607 reg = <0 0xe6510000 0 0x40>; 608 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cpg CPG_MOD 929>; 610 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 611 resets = <&cpg 929>; 612 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 613 <&dmac2 0x95>, <&dmac2 0x94>; 614 dma-names = "tx", "rx", "tx", "rx"; 615 i2c-scl-internal-delay-ns = <6>; 616 status = "disabled"; 617 }; 618 619 i2c3: i2c@e66d0000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "renesas,i2c-r8a77961", 623 "renesas,rcar-gen3-i2c"; 624 reg = <0 0xe66d0000 0 0x40>; 625 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 928>; 627 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 628 resets = <&cpg 928>; 629 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 630 dma-names = "tx", "rx"; 631 i2c-scl-internal-delay-ns = <110>; 632 status = "disabled"; 633 }; 634 635 i2c4: i2c@e66d8000 { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 compatible = "renesas,i2c-r8a77961", 639 "renesas,rcar-gen3-i2c"; 640 reg = <0 0xe66d8000 0 0x40>; 641 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD 927>; 643 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 644 resets = <&cpg 927>; 645 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 646 dma-names = "tx", "rx"; 647 i2c-scl-internal-delay-ns = <110>; 648 status = "disabled"; 649 }; 650 651 i2c5: i2c@e66e0000 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 compatible = "renesas,i2c-r8a77961", 655 "renesas,rcar-gen3-i2c"; 656 reg = <0 0xe66e0000 0 0x40>; 657 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 919>; 659 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 660 resets = <&cpg 919>; 661 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 662 dma-names = "tx", "rx"; 663 i2c-scl-internal-delay-ns = <110>; 664 status = "disabled"; 665 }; 666 667 i2c6: i2c@e66e8000 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 compatible = "renesas,i2c-r8a77961", 671 "renesas,rcar-gen3-i2c"; 672 reg = <0 0xe66e8000 0 0x40>; 673 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cpg CPG_MOD 918>; 675 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 676 resets = <&cpg 918>; 677 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 678 dma-names = "tx", "rx"; 679 i2c-scl-internal-delay-ns = <6>; 680 status = "disabled"; 681 }; 682 683 i2c_dvfs: i2c@e60b0000 { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 compatible = "renesas,iic-r8a77961", 687 "renesas,rcar-gen3-iic", 688 "renesas,rmobile-iic"; 689 reg = <0 0xe60b0000 0 0x425>; 690 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cpg CPG_MOD 926>; 692 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 693 resets = <&cpg 926>; 694 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 695 dma-names = "tx", "rx"; 696 status = "disabled"; 697 }; 698 699 hscif0: serial@e6540000 { 700 compatible = "renesas,hscif-r8a77961", 701 "renesas,rcar-gen3-hscif", 702 "renesas,hscif"; 703 reg = <0 0xe6540000 0 0x60>; 704 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cpg CPG_MOD 520>, 706 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 707 <&scif_clk>; 708 clock-names = "fck", "brg_int", "scif_clk"; 709 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 710 <&dmac2 0x31>, <&dmac2 0x30>; 711 dma-names = "tx", "rx", "tx", "rx"; 712 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 713 resets = <&cpg 520>; 714 status = "disabled"; 715 }; 716 717 hscif1: serial@e6550000 { 718 compatible = "renesas,hscif-r8a77961", 719 "renesas,rcar-gen3-hscif", 720 "renesas,hscif"; 721 reg = <0 0xe6550000 0 0x60>; 722 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cpg CPG_MOD 519>, 724 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 725 <&scif_clk>; 726 clock-names = "fck", "brg_int", "scif_clk"; 727 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 728 <&dmac2 0x33>, <&dmac2 0x32>; 729 dma-names = "tx", "rx", "tx", "rx"; 730 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 731 resets = <&cpg 519>; 732 status = "disabled"; 733 }; 734 735 hscif2: serial@e6560000 { 736 compatible = "renesas,hscif-r8a77961", 737 "renesas,rcar-gen3-hscif", 738 "renesas,hscif"; 739 reg = <0 0xe6560000 0 0x60>; 740 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cpg CPG_MOD 518>, 742 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 743 <&scif_clk>; 744 clock-names = "fck", "brg_int", "scif_clk"; 745 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 746 <&dmac2 0x35>, <&dmac2 0x34>; 747 dma-names = "tx", "rx", "tx", "rx"; 748 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 749 resets = <&cpg 518>; 750 status = "disabled"; 751 }; 752 753 hscif3: serial@e66a0000 { 754 compatible = "renesas,hscif-r8a77961", 755 "renesas,rcar-gen3-hscif", 756 "renesas,hscif"; 757 reg = <0 0xe66a0000 0 0x60>; 758 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cpg CPG_MOD 517>, 760 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 761 <&scif_clk>; 762 clock-names = "fck", "brg_int", "scif_clk"; 763 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 764 dma-names = "tx", "rx"; 765 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 766 resets = <&cpg 517>; 767 status = "disabled"; 768 }; 769 770 hscif4: serial@e66b0000 { 771 compatible = "renesas,hscif-r8a77961", 772 "renesas,rcar-gen3-hscif", 773 "renesas,hscif"; 774 reg = <0 0xe66b0000 0 0x60>; 775 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 516>, 777 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 778 <&scif_clk>; 779 clock-names = "fck", "brg_int", "scif_clk"; 780 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 781 dma-names = "tx", "rx"; 782 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 783 resets = <&cpg 516>; 784 status = "disabled"; 785 }; 786 787 hsusb: usb@e6590000 { 788 compatible = "renesas,usbhs-r8a77961", 789 "renesas,rcar-gen3-usbhs"; 790 reg = <0 0xe6590000 0 0x200>; 791 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 793 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 794 <&usb_dmac1 0>, <&usb_dmac1 1>; 795 dma-names = "ch0", "ch1", "ch2", "ch3"; 796 renesas,buswait = <11>; 797 phys = <&usb2_phy0 3>; 798 phy-names = "usb"; 799 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 800 resets = <&cpg 704>, <&cpg 703>; 801 status = "disabled"; 802 }; 803 804 usb_dmac0: dma-controller@e65a0000 { 805 compatible = "renesas,r8a77961-usb-dmac", 806 "renesas,usb-dmac"; 807 reg = <0 0xe65a0000 0 0x100>; 808 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "ch0", "ch1"; 811 clocks = <&cpg CPG_MOD 330>; 812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 813 resets = <&cpg 330>; 814 #dma-cells = <1>; 815 dma-channels = <2>; 816 }; 817 818 usb_dmac1: dma-controller@e65b0000 { 819 compatible = "renesas,r8a77961-usb-dmac", 820 "renesas,usb-dmac"; 821 reg = <0 0xe65b0000 0 0x100>; 822 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 824 interrupt-names = "ch0", "ch1"; 825 clocks = <&cpg CPG_MOD 331>; 826 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 827 resets = <&cpg 331>; 828 #dma-cells = <1>; 829 dma-channels = <2>; 830 }; 831 832 usb3_phy0: usb-phy@e65ee000 { 833 compatible = "renesas,r8a77961-usb3-phy", 834 "renesas,rcar-gen3-usb3-phy"; 835 reg = <0 0xe65ee000 0 0x90>; 836 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 837 <&usb_extal_clk>; 838 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 839 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 840 resets = <&cpg 328>; 841 #phy-cells = <0>; 842 status = "disabled"; 843 }; 844 845 arm_cc630p: crypto@e6601000 { 846 compatible = "arm,cryptocell-630p-ree"; 847 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 848 reg = <0x0 0xe6601000 0 0x1000>; 849 clocks = <&cpg CPG_MOD 229>; 850 resets = <&cpg 229>; 851 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 852 }; 853 854 dmac0: dma-controller@e6700000 { 855 compatible = "renesas,dmac-r8a77961", 856 "renesas,rcar-dmac"; 857 reg = <0 0xe6700000 0 0x10000>; 858 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "error", 876 "ch0", "ch1", "ch2", "ch3", 877 "ch4", "ch5", "ch6", "ch7", 878 "ch8", "ch9", "ch10", "ch11", 879 "ch12", "ch13", "ch14", "ch15"; 880 clocks = <&cpg CPG_MOD 219>; 881 clock-names = "fck"; 882 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 883 resets = <&cpg 219>; 884 #dma-cells = <1>; 885 dma-channels = <16>; 886 }; 887 888 dmac1: dma-controller@e7300000 { 889 compatible = "renesas,dmac-r8a77961", 890 "renesas,rcar-dmac"; 891 reg = <0 0xe7300000 0 0x10000>; 892 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-names = "error", 910 "ch0", "ch1", "ch2", "ch3", 911 "ch4", "ch5", "ch6", "ch7", 912 "ch8", "ch9", "ch10", "ch11", 913 "ch12", "ch13", "ch14", "ch15"; 914 clocks = <&cpg CPG_MOD 218>; 915 clock-names = "fck"; 916 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 917 resets = <&cpg 218>; 918 #dma-cells = <1>; 919 dma-channels = <16>; 920 }; 921 922 dmac2: dma-controller@e7310000 { 923 compatible = "renesas,dmac-r8a77961", 924 "renesas,rcar-dmac"; 925 reg = <0 0xe7310000 0 0x10000>; 926 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "error", 944 "ch0", "ch1", "ch2", "ch3", 945 "ch4", "ch5", "ch6", "ch7", 946 "ch8", "ch9", "ch10", "ch11", 947 "ch12", "ch13", "ch14", "ch15"; 948 clocks = <&cpg CPG_MOD 217>; 949 clock-names = "fck"; 950 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 951 resets = <&cpg 217>; 952 #dma-cells = <1>; 953 dma-channels = <16>; 954 }; 955 956 ipmmu_ds0: iommu@e6740000 { 957 compatible = "renesas,ipmmu-r8a77961"; 958 reg = <0 0xe6740000 0 0x1000>; 959 renesas,ipmmu-main = <&ipmmu_mm 0>; 960 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 961 #iommu-cells = <1>; 962 }; 963 964 ipmmu_ds1: iommu@e7740000 { 965 compatible = "renesas,ipmmu-r8a77961"; 966 reg = <0 0xe7740000 0 0x1000>; 967 renesas,ipmmu-main = <&ipmmu_mm 1>; 968 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 969 #iommu-cells = <1>; 970 }; 971 972 ipmmu_hc: iommu@e6570000 { 973 compatible = "renesas,ipmmu-r8a77961"; 974 reg = <0 0xe6570000 0 0x1000>; 975 renesas,ipmmu-main = <&ipmmu_mm 2>; 976 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 977 #iommu-cells = <1>; 978 }; 979 980 ipmmu_ir: iommu@ff8b0000 { 981 compatible = "renesas,ipmmu-r8a77961"; 982 reg = <0 0xff8b0000 0 0x1000>; 983 renesas,ipmmu-main = <&ipmmu_mm 3>; 984 power-domains = <&sysc R8A77961_PD_A3IR>; 985 #iommu-cells = <1>; 986 }; 987 988 ipmmu_mm: iommu@e67b0000 { 989 compatible = "renesas,ipmmu-r8a77961"; 990 reg = <0 0xe67b0000 0 0x1000>; 991 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 993 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 994 #iommu-cells = <1>; 995 }; 996 997 ipmmu_mp: iommu@ec670000 { 998 compatible = "renesas,ipmmu-r8a77961"; 999 reg = <0 0xec670000 0 0x1000>; 1000 renesas,ipmmu-main = <&ipmmu_mm 4>; 1001 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1002 #iommu-cells = <1>; 1003 }; 1004 1005 ipmmu_pv0: iommu@fd800000 { 1006 compatible = "renesas,ipmmu-r8a77961"; 1007 reg = <0 0xfd800000 0 0x1000>; 1008 renesas,ipmmu-main = <&ipmmu_mm 5>; 1009 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1010 #iommu-cells = <1>; 1011 }; 1012 1013 ipmmu_pv1: iommu@fd950000 { 1014 compatible = "renesas,ipmmu-r8a77961"; 1015 reg = <0 0xfd950000 0 0x1000>; 1016 renesas,ipmmu-main = <&ipmmu_mm 6>; 1017 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1018 #iommu-cells = <1>; 1019 }; 1020 1021 ipmmu_rt: iommu@ffc80000 { 1022 compatible = "renesas,ipmmu-r8a77961"; 1023 reg = <0 0xffc80000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 7>; 1025 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 ipmmu_vc0: iommu@fe6b0000 { 1030 compatible = "renesas,ipmmu-r8a77961"; 1031 reg = <0 0xfe6b0000 0 0x1000>; 1032 renesas,ipmmu-main = <&ipmmu_mm 8>; 1033 power-domains = <&sysc R8A77961_PD_A3VC>; 1034 #iommu-cells = <1>; 1035 }; 1036 1037 ipmmu_vi0: iommu@febd0000 { 1038 compatible = "renesas,ipmmu-r8a77961"; 1039 reg = <0 0xfebd0000 0 0x1000>; 1040 renesas,ipmmu-main = <&ipmmu_mm 9>; 1041 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1042 #iommu-cells = <1>; 1043 }; 1044 1045 avb: ethernet@e6800000 { 1046 compatible = "renesas,etheravb-r8a77961", 1047 "renesas,etheravb-rcar-gen3"; 1048 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1049 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1074 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1075 "ch4", "ch5", "ch6", "ch7", 1076 "ch8", "ch9", "ch10", "ch11", 1077 "ch12", "ch13", "ch14", "ch15", 1078 "ch16", "ch17", "ch18", "ch19", 1079 "ch20", "ch21", "ch22", "ch23", 1080 "ch24"; 1081 clocks = <&cpg CPG_MOD 812>; 1082 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1083 resets = <&cpg 812>; 1084 phy-mode = "rgmii"; 1085 rx-internal-delay-ps = <0>; 1086 tx-internal-delay-ps = <0>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 can0: can@e6c30000 { 1093 reg = <0 0xe6c30000 0 0x1000>; 1094 /* placeholder */ 1095 }; 1096 1097 can1: can@e6c38000 { 1098 reg = <0 0xe6c38000 0 0x1000>; 1099 /* placeholder */ 1100 }; 1101 1102 pwm0: pwm@e6e30000 { 1103 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1104 reg = <0 0xe6e30000 0 8>; 1105 #pwm-cells = <2>; 1106 clocks = <&cpg CPG_MOD 523>; 1107 resets = <&cpg 523>; 1108 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1109 status = "disabled"; 1110 }; 1111 1112 pwm1: pwm@e6e31000 { 1113 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1114 reg = <0 0xe6e31000 0 8>; 1115 #pwm-cells = <2>; 1116 clocks = <&cpg CPG_MOD 523>; 1117 resets = <&cpg 523>; 1118 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1119 status = "disabled"; 1120 }; 1121 1122 pwm2: pwm@e6e32000 { 1123 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1124 reg = <0 0xe6e32000 0 8>; 1125 #pwm-cells = <2>; 1126 clocks = <&cpg CPG_MOD 523>; 1127 resets = <&cpg 523>; 1128 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1129 status = "disabled"; 1130 }; 1131 1132 pwm3: pwm@e6e33000 { 1133 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1134 reg = <0 0xe6e33000 0 8>; 1135 #pwm-cells = <2>; 1136 clocks = <&cpg CPG_MOD 523>; 1137 resets = <&cpg 523>; 1138 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1139 status = "disabled"; 1140 }; 1141 1142 pwm4: pwm@e6e34000 { 1143 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1144 reg = <0 0xe6e34000 0 8>; 1145 #pwm-cells = <2>; 1146 clocks = <&cpg CPG_MOD 523>; 1147 resets = <&cpg 523>; 1148 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1149 status = "disabled"; 1150 }; 1151 1152 pwm5: pwm@e6e35000 { 1153 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1154 reg = <0 0xe6e35000 0 8>; 1155 #pwm-cells = <2>; 1156 clocks = <&cpg CPG_MOD 523>; 1157 resets = <&cpg 523>; 1158 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1159 status = "disabled"; 1160 }; 1161 1162 pwm6: pwm@e6e36000 { 1163 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1164 reg = <0 0xe6e36000 0 8>; 1165 #pwm-cells = <2>; 1166 clocks = <&cpg CPG_MOD 523>; 1167 resets = <&cpg 523>; 1168 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1169 status = "disabled"; 1170 }; 1171 1172 scif0: serial@e6e60000 { 1173 compatible = "renesas,scif-r8a77961", 1174 "renesas,rcar-gen3-scif", "renesas,scif"; 1175 reg = <0 0xe6e60000 0 64>; 1176 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&cpg CPG_MOD 207>, 1178 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1179 <&scif_clk>; 1180 clock-names = "fck", "brg_int", "scif_clk"; 1181 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1182 <&dmac2 0x51>, <&dmac2 0x50>; 1183 dma-names = "tx", "rx", "tx", "rx"; 1184 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1185 resets = <&cpg 207>; 1186 status = "disabled"; 1187 }; 1188 1189 scif1: serial@e6e68000 { 1190 compatible = "renesas,scif-r8a77961", 1191 "renesas,rcar-gen3-scif", "renesas,scif"; 1192 reg = <0 0xe6e68000 0 64>; 1193 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&cpg CPG_MOD 206>, 1195 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1196 <&scif_clk>; 1197 clock-names = "fck", "brg_int", "scif_clk"; 1198 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1199 <&dmac2 0x53>, <&dmac2 0x52>; 1200 dma-names = "tx", "rx", "tx", "rx"; 1201 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1202 resets = <&cpg 206>; 1203 status = "disabled"; 1204 }; 1205 1206 scif2: serial@e6e88000 { 1207 compatible = "renesas,scif-r8a77961", 1208 "renesas,rcar-gen3-scif", "renesas,scif"; 1209 reg = <0 0xe6e88000 0 64>; 1210 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&cpg CPG_MOD 310>, 1212 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1213 <&scif_clk>; 1214 clock-names = "fck", "brg_int", "scif_clk"; 1215 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1216 <&dmac2 0x13>, <&dmac2 0x12>; 1217 dma-names = "tx", "rx", "tx", "rx"; 1218 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1219 resets = <&cpg 310>; 1220 status = "disabled"; 1221 }; 1222 1223 scif3: serial@e6c50000 { 1224 compatible = "renesas,scif-r8a77961", 1225 "renesas,rcar-gen3-scif", "renesas,scif"; 1226 reg = <0 0xe6c50000 0 64>; 1227 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cpg CPG_MOD 204>, 1229 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1230 <&scif_clk>; 1231 clock-names = "fck", "brg_int", "scif_clk"; 1232 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1233 dma-names = "tx", "rx"; 1234 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1235 resets = <&cpg 204>; 1236 status = "disabled"; 1237 }; 1238 1239 scif4: serial@e6c40000 { 1240 compatible = "renesas,scif-r8a77961", 1241 "renesas,rcar-gen3-scif", "renesas,scif"; 1242 reg = <0 0xe6c40000 0 64>; 1243 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&cpg CPG_MOD 203>, 1245 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1246 <&scif_clk>; 1247 clock-names = "fck", "brg_int", "scif_clk"; 1248 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1251 resets = <&cpg 203>; 1252 status = "disabled"; 1253 }; 1254 1255 scif5: serial@e6f30000 { 1256 compatible = "renesas,scif-r8a77961", 1257 "renesas,rcar-gen3-scif", "renesas,scif"; 1258 reg = <0 0xe6f30000 0 64>; 1259 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&cpg CPG_MOD 202>, 1261 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1262 <&scif_clk>; 1263 clock-names = "fck", "brg_int", "scif_clk"; 1264 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1265 <&dmac2 0x5b>, <&dmac2 0x5a>; 1266 dma-names = "tx", "rx", "tx", "rx"; 1267 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1268 resets = <&cpg 202>; 1269 status = "disabled"; 1270 }; 1271 1272 msiof0: spi@e6e90000 { 1273 compatible = "renesas,msiof-r8a77961", 1274 "renesas,rcar-gen3-msiof"; 1275 reg = <0 0xe6e90000 0 0x0064>; 1276 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&cpg CPG_MOD 211>; 1278 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1279 <&dmac2 0x41>, <&dmac2 0x40>; 1280 dma-names = "tx", "rx", "tx", "rx"; 1281 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1282 resets = <&cpg 211>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 status = "disabled"; 1286 }; 1287 1288 msiof1: spi@e6ea0000 { 1289 compatible = "renesas,msiof-r8a77961", 1290 "renesas,rcar-gen3-msiof"; 1291 reg = <0 0xe6ea0000 0 0x0064>; 1292 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&cpg CPG_MOD 210>; 1294 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1295 <&dmac2 0x43>, <&dmac2 0x42>; 1296 dma-names = "tx", "rx", "tx", "rx"; 1297 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1298 resets = <&cpg 210>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 status = "disabled"; 1302 }; 1303 1304 msiof2: spi@e6c00000 { 1305 compatible = "renesas,msiof-r8a77961", 1306 "renesas,rcar-gen3-msiof"; 1307 reg = <0 0xe6c00000 0 0x0064>; 1308 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&cpg CPG_MOD 209>; 1310 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1311 dma-names = "tx", "rx"; 1312 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1313 resets = <&cpg 209>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 msiof3: spi@e6c10000 { 1320 compatible = "renesas,msiof-r8a77961", 1321 "renesas,rcar-gen3-msiof"; 1322 reg = <0 0xe6c10000 0 0x0064>; 1323 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1324 clocks = <&cpg CPG_MOD 208>; 1325 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1326 dma-names = "tx", "rx"; 1327 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1328 resets = <&cpg 208>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 vin0: video@e6ef0000 { 1335 reg = <0 0xe6ef0000 0 0x1000>; 1336 /* placeholder */ 1337 }; 1338 1339 vin1: video@e6ef1000 { 1340 reg = <0 0xe6ef1000 0 0x1000>; 1341 /* placeholder */ 1342 }; 1343 1344 vin2: video@e6ef2000 { 1345 reg = <0 0xe6ef2000 0 0x1000>; 1346 /* placeholder */ 1347 }; 1348 1349 vin3: video@e6ef3000 { 1350 reg = <0 0xe6ef3000 0 0x1000>; 1351 /* placeholder */ 1352 }; 1353 1354 vin4: video@e6ef4000 { 1355 reg = <0 0xe6ef4000 0 0x1000>; 1356 /* placeholder */ 1357 }; 1358 1359 vin5: video@e6ef5000 { 1360 reg = <0 0xe6ef5000 0 0x1000>; 1361 /* placeholder */ 1362 }; 1363 1364 vin6: video@e6ef6000 { 1365 reg = <0 0xe6ef6000 0 0x1000>; 1366 /* placeholder */ 1367 }; 1368 1369 vin7: video@e6ef7000 { 1370 reg = <0 0xe6ef7000 0 0x1000>; 1371 /* placeholder */ 1372 }; 1373 1374 rcar_sound: sound@ec500000 { 1375 /* 1376 * #sound-dai-cells is required 1377 * 1378 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1379 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1380 */ 1381 /* 1382 * #clock-cells is required for audio_clkout0/1/2/3 1383 * 1384 * clkout : #clock-cells = <0>; <&rcar_sound>; 1385 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1386 */ 1387 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1388 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1389 <0 0xec5a0000 0 0x100>, /* ADG */ 1390 <0 0xec540000 0 0x1000>, /* SSIU */ 1391 <0 0xec541000 0 0x280>, /* SSI */ 1392 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1393 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1394 1395 clocks = <&cpg CPG_MOD 1005>, 1396 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1397 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1398 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1399 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1400 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1401 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1402 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1403 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1404 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1405 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1406 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1407 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1408 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1409 <&audio_clk_a>, <&audio_clk_b>, 1410 <&audio_clk_c>, 1411 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1412 clock-names = "ssi-all", 1413 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1414 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1415 "ssi.1", "ssi.0", 1416 "src.9", "src.8", "src.7", "src.6", 1417 "src.5", "src.4", "src.3", "src.2", 1418 "src.1", "src.0", 1419 "mix.1", "mix.0", 1420 "ctu.1", "ctu.0", 1421 "dvc.0", "dvc.1", 1422 "clk_a", "clk_b", "clk_c", "clk_i"; 1423 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1424 resets = <&cpg 1005>, 1425 <&cpg 1006>, <&cpg 1007>, 1426 <&cpg 1008>, <&cpg 1009>, 1427 <&cpg 1010>, <&cpg 1011>, 1428 <&cpg 1012>, <&cpg 1013>, 1429 <&cpg 1014>, <&cpg 1015>; 1430 reset-names = "ssi-all", 1431 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1432 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1433 "ssi.1", "ssi.0"; 1434 status = "disabled"; 1435 1436 rcar_sound,ctu { 1437 ctu00: ctu-0 { }; 1438 ctu01: ctu-1 { }; 1439 ctu02: ctu-2 { }; 1440 ctu03: ctu-3 { }; 1441 ctu10: ctu-4 { }; 1442 ctu11: ctu-5 { }; 1443 ctu12: ctu-6 { }; 1444 ctu13: ctu-7 { }; 1445 }; 1446 1447 rcar_sound,dvc { 1448 dvc0: dvc-0 { 1449 dmas = <&audma1 0xbc>; 1450 dma-names = "tx"; 1451 }; 1452 dvc1: dvc-1 { 1453 dmas = <&audma1 0xbe>; 1454 dma-names = "tx"; 1455 }; 1456 }; 1457 1458 rcar_sound,mix { 1459 mix0: mix-0 { }; 1460 mix1: mix-1 { }; 1461 }; 1462 1463 rcar_sound,src { 1464 src0: src-0 { 1465 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1466 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1467 dma-names = "rx", "tx"; 1468 }; 1469 src1: src-1 { 1470 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1471 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1472 dma-names = "rx", "tx"; 1473 }; 1474 src2: src-2 { 1475 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1476 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1477 dma-names = "rx", "tx"; 1478 }; 1479 src3: src-3 { 1480 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1482 dma-names = "rx", "tx"; 1483 }; 1484 src4: src-4 { 1485 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1486 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1487 dma-names = "rx", "tx"; 1488 }; 1489 src5: src-5 { 1490 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1491 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1492 dma-names = "rx", "tx"; 1493 }; 1494 src6: src-6 { 1495 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1496 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1497 dma-names = "rx", "tx"; 1498 }; 1499 src7: src-7 { 1500 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1501 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1502 dma-names = "rx", "tx"; 1503 }; 1504 src8: src-8 { 1505 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1506 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1507 dma-names = "rx", "tx"; 1508 }; 1509 src9: src-9 { 1510 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1511 dmas = <&audma0 0x97>, <&audma1 0xba>; 1512 dma-names = "rx", "tx"; 1513 }; 1514 }; 1515 1516 rcar_sound,ssi { 1517 ssi0: ssi-0 { 1518 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1519 dmas = <&audma0 0x01>, <&audma1 0x02>; 1520 dma-names = "rx", "tx"; 1521 }; 1522 ssi1: ssi-1 { 1523 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1524 dmas = <&audma0 0x03>, <&audma1 0x04>; 1525 dma-names = "rx", "tx"; 1526 }; 1527 ssi2: ssi-2 { 1528 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1529 dmas = <&audma0 0x05>, <&audma1 0x06>; 1530 dma-names = "rx", "tx"; 1531 }; 1532 ssi3: ssi-3 { 1533 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1534 dmas = <&audma0 0x07>, <&audma1 0x08>; 1535 dma-names = "rx", "tx"; 1536 }; 1537 ssi4: ssi-4 { 1538 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1539 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1540 dma-names = "rx", "tx"; 1541 }; 1542 ssi5: ssi-5 { 1543 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1544 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1545 dma-names = "rx", "tx"; 1546 }; 1547 ssi6: ssi-6 { 1548 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1549 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1550 dma-names = "rx", "tx"; 1551 }; 1552 ssi7: ssi-7 { 1553 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1554 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1555 dma-names = "rx", "tx"; 1556 }; 1557 ssi8: ssi-8 { 1558 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1559 dmas = <&audma0 0x11>, <&audma1 0x12>; 1560 dma-names = "rx", "tx"; 1561 }; 1562 ssi9: ssi-9 { 1563 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1564 dmas = <&audma0 0x13>, <&audma1 0x14>; 1565 dma-names = "rx", "tx"; 1566 }; 1567 }; 1568 1569 rcar_sound,ssiu { 1570 ssiu00: ssiu-0 { 1571 dmas = <&audma0 0x15>, <&audma1 0x16>; 1572 dma-names = "rx", "tx"; 1573 }; 1574 ssiu01: ssiu-1 { 1575 dmas = <&audma0 0x35>, <&audma1 0x36>; 1576 dma-names = "rx", "tx"; 1577 }; 1578 ssiu02: ssiu-2 { 1579 dmas = <&audma0 0x37>, <&audma1 0x38>; 1580 dma-names = "rx", "tx"; 1581 }; 1582 ssiu03: ssiu-3 { 1583 dmas = <&audma0 0x47>, <&audma1 0x48>; 1584 dma-names = "rx", "tx"; 1585 }; 1586 ssiu04: ssiu-4 { 1587 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1588 dma-names = "rx", "tx"; 1589 }; 1590 ssiu05: ssiu-5 { 1591 dmas = <&audma0 0x43>, <&audma1 0x44>; 1592 dma-names = "rx", "tx"; 1593 }; 1594 ssiu06: ssiu-6 { 1595 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1596 dma-names = "rx", "tx"; 1597 }; 1598 ssiu07: ssiu-7 { 1599 dmas = <&audma0 0x53>, <&audma1 0x54>; 1600 dma-names = "rx", "tx"; 1601 }; 1602 ssiu10: ssiu-8 { 1603 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1604 dma-names = "rx", "tx"; 1605 }; 1606 ssiu11: ssiu-9 { 1607 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1608 dma-names = "rx", "tx"; 1609 }; 1610 ssiu12: ssiu-10 { 1611 dmas = <&audma0 0x57>, <&audma1 0x58>; 1612 dma-names = "rx", "tx"; 1613 }; 1614 ssiu13: ssiu-11 { 1615 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1616 dma-names = "rx", "tx"; 1617 }; 1618 ssiu14: ssiu-12 { 1619 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1620 dma-names = "rx", "tx"; 1621 }; 1622 ssiu15: ssiu-13 { 1623 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1624 dma-names = "rx", "tx"; 1625 }; 1626 ssiu16: ssiu-14 { 1627 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1628 dma-names = "rx", "tx"; 1629 }; 1630 ssiu17: ssiu-15 { 1631 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1632 dma-names = "rx", "tx"; 1633 }; 1634 ssiu20: ssiu-16 { 1635 dmas = <&audma0 0x63>, <&audma1 0x64>; 1636 dma-names = "rx", "tx"; 1637 }; 1638 ssiu21: ssiu-17 { 1639 dmas = <&audma0 0x67>, <&audma1 0x68>; 1640 dma-names = "rx", "tx"; 1641 }; 1642 ssiu22: ssiu-18 { 1643 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1644 dma-names = "rx", "tx"; 1645 }; 1646 ssiu23: ssiu-19 { 1647 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1648 dma-names = "rx", "tx"; 1649 }; 1650 ssiu24: ssiu-20 { 1651 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1652 dma-names = "rx", "tx"; 1653 }; 1654 ssiu25: ssiu-21 { 1655 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1656 dma-names = "rx", "tx"; 1657 }; 1658 ssiu26: ssiu-22 { 1659 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1660 dma-names = "rx", "tx"; 1661 }; 1662 ssiu27: ssiu-23 { 1663 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1664 dma-names = "rx", "tx"; 1665 }; 1666 ssiu30: ssiu-24 { 1667 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1668 dma-names = "rx", "tx"; 1669 }; 1670 ssiu31: ssiu-25 { 1671 dmas = <&audma0 0x21>, <&audma1 0x22>; 1672 dma-names = "rx", "tx"; 1673 }; 1674 ssiu32: ssiu-26 { 1675 dmas = <&audma0 0x23>, <&audma1 0x24>; 1676 dma-names = "rx", "tx"; 1677 }; 1678 ssiu33: ssiu-27 { 1679 dmas = <&audma0 0x25>, <&audma1 0x26>; 1680 dma-names = "rx", "tx"; 1681 }; 1682 ssiu34: ssiu-28 { 1683 dmas = <&audma0 0x27>, <&audma1 0x28>; 1684 dma-names = "rx", "tx"; 1685 }; 1686 ssiu35: ssiu-29 { 1687 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1688 dma-names = "rx", "tx"; 1689 }; 1690 ssiu36: ssiu-30 { 1691 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1692 dma-names = "rx", "tx"; 1693 }; 1694 ssiu37: ssiu-31 { 1695 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1696 dma-names = "rx", "tx"; 1697 }; 1698 ssiu40: ssiu-32 { 1699 dmas = <&audma0 0x71>, <&audma1 0x72>; 1700 dma-names = "rx", "tx"; 1701 }; 1702 ssiu41: ssiu-33 { 1703 dmas = <&audma0 0x17>, <&audma1 0x18>; 1704 dma-names = "rx", "tx"; 1705 }; 1706 ssiu42: ssiu-34 { 1707 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1708 dma-names = "rx", "tx"; 1709 }; 1710 ssiu43: ssiu-35 { 1711 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1712 dma-names = "rx", "tx"; 1713 }; 1714 ssiu44: ssiu-36 { 1715 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1716 dma-names = "rx", "tx"; 1717 }; 1718 ssiu45: ssiu-37 { 1719 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1720 dma-names = "rx", "tx"; 1721 }; 1722 ssiu46: ssiu-38 { 1723 dmas = <&audma0 0x31>, <&audma1 0x32>; 1724 dma-names = "rx", "tx"; 1725 }; 1726 ssiu47: ssiu-39 { 1727 dmas = <&audma0 0x33>, <&audma1 0x34>; 1728 dma-names = "rx", "tx"; 1729 }; 1730 ssiu50: ssiu-40 { 1731 dmas = <&audma0 0x73>, <&audma1 0x74>; 1732 dma-names = "rx", "tx"; 1733 }; 1734 ssiu60: ssiu-41 { 1735 dmas = <&audma0 0x75>, <&audma1 0x76>; 1736 dma-names = "rx", "tx"; 1737 }; 1738 ssiu70: ssiu-42 { 1739 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1740 dma-names = "rx", "tx"; 1741 }; 1742 ssiu80: ssiu-43 { 1743 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1744 dma-names = "rx", "tx"; 1745 }; 1746 ssiu90: ssiu-44 { 1747 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1748 dma-names = "rx", "tx"; 1749 }; 1750 ssiu91: ssiu-45 { 1751 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1752 dma-names = "rx", "tx"; 1753 }; 1754 ssiu92: ssiu-46 { 1755 dmas = <&audma0 0x81>, <&audma1 0x82>; 1756 dma-names = "rx", "tx"; 1757 }; 1758 ssiu93: ssiu-47 { 1759 dmas = <&audma0 0x83>, <&audma1 0x84>; 1760 dma-names = "rx", "tx"; 1761 }; 1762 ssiu94: ssiu-48 { 1763 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1764 dma-names = "rx", "tx"; 1765 }; 1766 ssiu95: ssiu-49 { 1767 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1768 dma-names = "rx", "tx"; 1769 }; 1770 ssiu96: ssiu-50 { 1771 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1772 dma-names = "rx", "tx"; 1773 }; 1774 ssiu97: ssiu-51 { 1775 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1776 dma-names = "rx", "tx"; 1777 }; 1778 }; 1779 }; 1780 1781 audma0: dma-controller@ec700000 { 1782 compatible = "renesas,dmac-r8a77961", 1783 "renesas,rcar-dmac"; 1784 reg = <0 0xec700000 0 0x10000>; 1785 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1802 interrupt-names = "error", 1803 "ch0", "ch1", "ch2", "ch3", 1804 "ch4", "ch5", "ch6", "ch7", 1805 "ch8", "ch9", "ch10", "ch11", 1806 "ch12", "ch13", "ch14", "ch15"; 1807 clocks = <&cpg CPG_MOD 502>; 1808 clock-names = "fck"; 1809 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1810 resets = <&cpg 502>; 1811 #dma-cells = <1>; 1812 dma-channels = <16>; 1813 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1814 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1815 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1816 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1817 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1818 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1819 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1820 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1821 }; 1822 1823 audma1: dma-controller@ec720000 { 1824 compatible = "renesas,dmac-r8a77961", 1825 "renesas,rcar-dmac"; 1826 reg = <0 0xec720000 0 0x10000>; 1827 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1844 interrupt-names = "error", 1845 "ch0", "ch1", "ch2", "ch3", 1846 "ch4", "ch5", "ch6", "ch7", 1847 "ch8", "ch9", "ch10", "ch11", 1848 "ch12", "ch13", "ch14", "ch15"; 1849 clocks = <&cpg CPG_MOD 501>; 1850 clock-names = "fck"; 1851 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1852 resets = <&cpg 501>; 1853 #dma-cells = <1>; 1854 dma-channels = <16>; 1855 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1856 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1857 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1858 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1859 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1860 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1861 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1862 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1863 }; 1864 1865 xhci0: usb@ee000000 { 1866 compatible = "renesas,xhci-r8a77961", 1867 "renesas,rcar-gen3-xhci"; 1868 reg = <0 0xee000000 0 0xc00>; 1869 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1870 clocks = <&cpg CPG_MOD 328>; 1871 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1872 resets = <&cpg 328>; 1873 status = "disabled"; 1874 }; 1875 1876 usb3_peri0: usb@ee020000 { 1877 compatible = "renesas,r8a77961-usb3-peri", 1878 "renesas,rcar-gen3-usb3-peri"; 1879 reg = <0 0xee020000 0 0x400>; 1880 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1881 clocks = <&cpg CPG_MOD 328>; 1882 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1883 resets = <&cpg 328>; 1884 status = "disabled"; 1885 }; 1886 1887 ohci0: usb@ee080000 { 1888 compatible = "generic-ohci"; 1889 reg = <0 0xee080000 0 0x100>; 1890 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1891 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1892 phys = <&usb2_phy0 1>; 1893 phy-names = "usb"; 1894 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1895 resets = <&cpg 703>, <&cpg 704>; 1896 status = "disabled"; 1897 }; 1898 1899 ohci1: usb@ee0a0000 { 1900 compatible = "generic-ohci"; 1901 reg = <0 0xee0a0000 0 0x100>; 1902 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1903 clocks = <&cpg CPG_MOD 702>; 1904 phys = <&usb2_phy1 1>; 1905 phy-names = "usb"; 1906 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1907 resets = <&cpg 702>; 1908 status = "disabled"; 1909 }; 1910 1911 ehci0: usb@ee080100 { 1912 compatible = "generic-ehci"; 1913 reg = <0 0xee080100 0 0x100>; 1914 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1916 phys = <&usb2_phy0 2>; 1917 phy-names = "usb"; 1918 companion = <&ohci0>; 1919 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1920 resets = <&cpg 703>, <&cpg 704>; 1921 status = "disabled"; 1922 }; 1923 1924 ehci1: usb@ee0a0100 { 1925 compatible = "generic-ehci"; 1926 reg = <0 0xee0a0100 0 0x100>; 1927 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&cpg CPG_MOD 702>; 1929 phys = <&usb2_phy1 2>; 1930 phy-names = "usb"; 1931 companion = <&ohci1>; 1932 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1933 resets = <&cpg 702>; 1934 status = "disabled"; 1935 }; 1936 1937 usb2_phy0: usb-phy@ee080200 { 1938 compatible = "renesas,usb2-phy-r8a77961", 1939 "renesas,rcar-gen3-usb2-phy"; 1940 reg = <0 0xee080200 0 0x700>; 1941 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1943 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1944 resets = <&cpg 703>, <&cpg 704>; 1945 #phy-cells = <1>; 1946 status = "disabled"; 1947 }; 1948 1949 usb2_phy1: usb-phy@ee0a0200 { 1950 compatible = "renesas,usb2-phy-r8a77961", 1951 "renesas,rcar-gen3-usb2-phy"; 1952 reg = <0 0xee0a0200 0 0x700>; 1953 clocks = <&cpg CPG_MOD 702>; 1954 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1955 resets = <&cpg 702>; 1956 #phy-cells = <1>; 1957 status = "disabled"; 1958 }; 1959 1960 sdhi0: mmc@ee100000 { 1961 compatible = "renesas,sdhi-r8a77961", 1962 "renesas,rcar-gen3-sdhi"; 1963 reg = <0 0xee100000 0 0x2000>; 1964 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1965 clocks = <&cpg CPG_MOD 314>; 1966 max-frequency = <200000000>; 1967 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1968 resets = <&cpg 314>; 1969 status = "disabled"; 1970 }; 1971 1972 sdhi1: mmc@ee120000 { 1973 compatible = "renesas,sdhi-r8a77961", 1974 "renesas,rcar-gen3-sdhi"; 1975 reg = <0 0xee120000 0 0x2000>; 1976 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1977 clocks = <&cpg CPG_MOD 313>; 1978 max-frequency = <200000000>; 1979 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1980 resets = <&cpg 313>; 1981 status = "disabled"; 1982 }; 1983 1984 sdhi2: mmc@ee140000 { 1985 compatible = "renesas,sdhi-r8a77961", 1986 "renesas,rcar-gen3-sdhi"; 1987 reg = <0 0xee140000 0 0x2000>; 1988 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1989 clocks = <&cpg CPG_MOD 312>; 1990 max-frequency = <200000000>; 1991 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1992 resets = <&cpg 312>; 1993 status = "disabled"; 1994 }; 1995 1996 sdhi3: mmc@ee160000 { 1997 compatible = "renesas,sdhi-r8a77961", 1998 "renesas,rcar-gen3-sdhi"; 1999 reg = <0 0xee160000 0 0x2000>; 2000 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2001 clocks = <&cpg CPG_MOD 311>; 2002 max-frequency = <200000000>; 2003 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2004 resets = <&cpg 311>; 2005 status = "disabled"; 2006 }; 2007 2008 gic: interrupt-controller@f1010000 { 2009 compatible = "arm,gic-400"; 2010 #interrupt-cells = <3>; 2011 #address-cells = <0>; 2012 interrupt-controller; 2013 reg = <0x0 0xf1010000 0 0x1000>, 2014 <0x0 0xf1020000 0 0x20000>, 2015 <0x0 0xf1040000 0 0x20000>, 2016 <0x0 0xf1060000 0 0x20000>; 2017 interrupts = <GIC_PPI 9 2018 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2019 clocks = <&cpg CPG_MOD 408>; 2020 clock-names = "clk"; 2021 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2022 resets = <&cpg 408>; 2023 }; 2024 2025 pciec0: pcie@fe000000 { 2026 compatible = "renesas,pcie-r8a77961", 2027 "renesas,pcie-rcar-gen3"; 2028 reg = <0 0xfe000000 0 0x80000>; 2029 #address-cells = <3>; 2030 #size-cells = <2>; 2031 bus-range = <0x00 0xff>; 2032 device_type = "pci"; 2033 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2034 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2035 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2036 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2037 /* Map all possible DDR as inbound ranges */ 2038 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2039 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2042 #interrupt-cells = <1>; 2043 interrupt-map-mask = <0 0 0 0>; 2044 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2045 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2046 clock-names = "pcie", "pcie_bus"; 2047 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2048 resets = <&cpg 319>; 2049 status = "disabled"; 2050 }; 2051 2052 pciec1: pcie@ee800000 { 2053 compatible = "renesas,pcie-r8a77961", 2054 "renesas,pcie-rcar-gen3"; 2055 reg = <0 0xee800000 0 0x80000>; 2056 #address-cells = <3>; 2057 #size-cells = <2>; 2058 bus-range = <0x00 0xff>; 2059 device_type = "pci"; 2060 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2061 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2062 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2063 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2064 /* Map all possible DDR as inbound ranges */ 2065 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2066 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2069 #interrupt-cells = <1>; 2070 interrupt-map-mask = <0 0 0 0>; 2071 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2072 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2073 clock-names = "pcie", "pcie_bus"; 2074 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2075 resets = <&cpg 318>; 2076 status = "disabled"; 2077 }; 2078 2079 fcpf0: fcp@fe950000 { 2080 compatible = "renesas,fcpf"; 2081 reg = <0 0xfe950000 0 0x200>; 2082 clocks = <&cpg CPG_MOD 615>; 2083 power-domains = <&sysc R8A77961_PD_A3VC>; 2084 resets = <&cpg 615>; 2085 }; 2086 2087 fcpvb0: fcp@fe96f000 { 2088 compatible = "renesas,fcpv"; 2089 reg = <0 0xfe96f000 0 0x200>; 2090 clocks = <&cpg CPG_MOD 607>; 2091 power-domains = <&sysc R8A77961_PD_A3VC>; 2092 resets = <&cpg 607>; 2093 }; 2094 2095 fcpvi0: fcp@fe9af000 { 2096 compatible = "renesas,fcpv"; 2097 reg = <0 0xfe9af000 0 0x200>; 2098 clocks = <&cpg CPG_MOD 611>; 2099 power-domains = <&sysc R8A77961_PD_A3VC>; 2100 resets = <&cpg 611>; 2101 iommus = <&ipmmu_vc0 19>; 2102 }; 2103 2104 fcpvd0: fcp@fea27000 { 2105 compatible = "renesas,fcpv"; 2106 reg = <0 0xfea27000 0 0x200>; 2107 clocks = <&cpg CPG_MOD 603>; 2108 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2109 resets = <&cpg 603>; 2110 iommus = <&ipmmu_vi0 8>; 2111 }; 2112 2113 fcpvd1: fcp@fea2f000 { 2114 compatible = "renesas,fcpv"; 2115 reg = <0 0xfea2f000 0 0x200>; 2116 clocks = <&cpg CPG_MOD 602>; 2117 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2118 resets = <&cpg 602>; 2119 iommus = <&ipmmu_vi0 9>; 2120 }; 2121 2122 fcpvd2: fcp@fea37000 { 2123 compatible = "renesas,fcpv"; 2124 reg = <0 0xfea37000 0 0x200>; 2125 clocks = <&cpg CPG_MOD 601>; 2126 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2127 resets = <&cpg 601>; 2128 iommus = <&ipmmu_vi0 10>; 2129 }; 2130 2131 vspb: vsp@fe960000 { 2132 compatible = "renesas,vsp2"; 2133 reg = <0 0xfe960000 0 0x8000>; 2134 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2135 clocks = <&cpg CPG_MOD 626>; 2136 power-domains = <&sysc R8A77961_PD_A3VC>; 2137 resets = <&cpg 626>; 2138 2139 renesas,fcp = <&fcpvb0>; 2140 }; 2141 2142 vspd0: vsp@fea20000 { 2143 compatible = "renesas,vsp2"; 2144 reg = <0 0xfea20000 0 0x5000>; 2145 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2146 clocks = <&cpg CPG_MOD 623>; 2147 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2148 resets = <&cpg 623>; 2149 2150 renesas,fcp = <&fcpvd0>; 2151 }; 2152 2153 vspd1: vsp@fea28000 { 2154 compatible = "renesas,vsp2"; 2155 reg = <0 0xfea28000 0 0x5000>; 2156 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2157 clocks = <&cpg CPG_MOD 622>; 2158 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2159 resets = <&cpg 622>; 2160 2161 renesas,fcp = <&fcpvd1>; 2162 }; 2163 2164 vspd2: vsp@fea30000 { 2165 compatible = "renesas,vsp2"; 2166 reg = <0 0xfea30000 0 0x5000>; 2167 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2168 clocks = <&cpg CPG_MOD 621>; 2169 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2170 resets = <&cpg 621>; 2171 2172 renesas,fcp = <&fcpvd2>; 2173 }; 2174 2175 vspi0: vsp@fe9a0000 { 2176 compatible = "renesas,vsp2"; 2177 reg = <0 0xfe9a0000 0 0x8000>; 2178 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2179 clocks = <&cpg CPG_MOD 631>; 2180 power-domains = <&sysc R8A77961_PD_A3VC>; 2181 resets = <&cpg 631>; 2182 2183 renesas,fcp = <&fcpvi0>; 2184 }; 2185 2186 csi20: csi2@fea80000 { 2187 reg = <0 0xfea80000 0 0x10000>; 2188 /* placeholder */ 2189 2190 ports { 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 2194 port@1 { 2195 #address-cells = <1>; 2196 #size-cells = <0>; 2197 reg = <1>; 2198 }; 2199 }; 2200 }; 2201 2202 csi40: csi2@feaa0000 { 2203 reg = <0 0xfeaa0000 0 0x10000>; 2204 /* placeholder */ 2205 2206 ports { 2207 #address-cells = <1>; 2208 #size-cells = <0>; 2209 2210 port@1 { 2211 #address-cells = <1>; 2212 #size-cells = <0>; 2213 2214 reg = <1>; 2215 }; 2216 }; 2217 }; 2218 2219 hdmi0: hdmi@fead0000 { 2220 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2221 reg = <0 0xfead0000 0 0x10000>; 2222 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2223 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2224 clock-names = "iahb", "isfr"; 2225 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2226 resets = <&cpg 729>; 2227 status = "disabled"; 2228 2229 ports { 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 port@0 { 2233 reg = <0>; 2234 dw_hdmi0_in: endpoint { 2235 remote-endpoint = <&du_out_hdmi0>; 2236 }; 2237 }; 2238 port@1 { 2239 reg = <1>; 2240 }; 2241 port@2 { 2242 /* HDMI sound */ 2243 reg = <2>; 2244 }; 2245 }; 2246 }; 2247 2248 du: display@feb00000 { 2249 compatible = "renesas,du-r8a77961"; 2250 reg = <0 0xfeb00000 0 0x70000>; 2251 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2254 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2255 <&cpg CPG_MOD 722>; 2256 clock-names = "du.0", "du.1", "du.2"; 2257 resets = <&cpg 724>, <&cpg 722>; 2258 reset-names = "du.0", "du.2"; 2259 2260 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2261 status = "disabled"; 2262 2263 ports { 2264 #address-cells = <1>; 2265 #size-cells = <0>; 2266 2267 port@0 { 2268 reg = <0>; 2269 du_out_rgb: endpoint { 2270 }; 2271 }; 2272 port@1 { 2273 reg = <1>; 2274 du_out_hdmi0: endpoint { 2275 remote-endpoint = <&dw_hdmi0_in>; 2276 }; 2277 }; 2278 port@2 { 2279 reg = <2>; 2280 du_out_lvds0: endpoint { 2281 }; 2282 }; 2283 }; 2284 }; 2285 2286 prr: chipid@fff00044 { 2287 compatible = "renesas,prr"; 2288 reg = <0 0xfff00044 0 4>; 2289 }; 2290 }; 2291 2292 thermal-zones { 2293 sensor_thermal1: sensor-thermal1 { 2294 polling-delay-passive = <250>; 2295 polling-delay = <1000>; 2296 thermal-sensors = <&tsc 0>; 2297 sustainable-power = <3874>; 2298 2299 trips { 2300 sensor1_crit: sensor1-crit { 2301 temperature = <120000>; 2302 hysteresis = <1000>; 2303 type = "critical"; 2304 }; 2305 }; 2306 }; 2307 2308 sensor_thermal2: sensor-thermal2 { 2309 polling-delay-passive = <250>; 2310 polling-delay = <1000>; 2311 thermal-sensors = <&tsc 1>; 2312 sustainable-power = <3874>; 2313 2314 trips { 2315 sensor2_crit: sensor2-crit { 2316 temperature = <120000>; 2317 hysteresis = <1000>; 2318 type = "critical"; 2319 }; 2320 }; 2321 }; 2322 2323 sensor_thermal3: sensor-thermal3 { 2324 polling-delay-passive = <250>; 2325 polling-delay = <1000>; 2326 thermal-sensors = <&tsc 2>; 2327 sustainable-power = <3874>; 2328 2329 cooling-maps { 2330 map0 { 2331 trip = <&target>; 2332 cooling-device = <&a57_0 2 4>; 2333 contribution = <1024>; 2334 }; 2335 map1 { 2336 trip = <&target>; 2337 cooling-device = <&a53_0 0 2>; 2338 contribution = <1024>; 2339 }; 2340 }; 2341 trips { 2342 target: trip-point1 { 2343 temperature = <100000>; 2344 hysteresis = <1000>; 2345 type = "passive"; 2346 }; 2347 2348 sensor3_crit: sensor3-crit { 2349 temperature = <120000>; 2350 hysteresis = <1000>; 2351 type = "critical"; 2352 }; 2353 }; 2354 }; 2355 }; 2356 2357 timer { 2358 compatible = "arm,armv8-timer"; 2359 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2360 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2361 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2362 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2363 }; 2364 2365 /* External USB clocks - can be overridden by the board */ 2366 usb3s0_clk: usb3s0 { 2367 compatible = "fixed-clock"; 2368 #clock-cells = <0>; 2369 clock-frequency = <0>; 2370 }; 2371 2372 usb_extal_clk: usb_extal { 2373 compatible = "fixed-clock"; 2374 #clock-cells = <0>; 2375 clock-frequency = <0>; 2376 }; 2377}; 2378