r8a77961.dtsi (174d0967b3447c118b9cae1e959950fa58d2e6bc) r8a77961.dtsi (76e6c82c53780516adde50a2d02a2412c07ac9b1)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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1318 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1319 clocks = <&cpg CPG_MOD 408>;
1320 clock-names = "clk";
1321 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1322 resets = <&cpg 408>;
1323 };
1324
1325 pciec0: pcie@fe000000 {
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a77961-cpg-mssr.h>

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1318 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1319 clocks = <&cpg CPG_MOD 408>;
1320 clock-names = "clk";
1321 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1322 resets = <&cpg 408>;
1323 };
1324
1325 pciec0: pcie@fe000000 {
1326 compatible = "renesas,pcie-r8a77961",
1327 "renesas,pcie-rcar-gen3";
1326 reg = <0 0xfe000000 0 0x80000>;
1328 reg = <0 0xfe000000 0 0x80000>;
1327 /* placeholder */
1329 #address-cells = <3>;
1330 #size-cells = <2>;
1331 bus-range = <0x00 0xff>;
1332 device_type = "pci";
1333 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1334 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1335 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1336 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1337 /* Map all possible DDR as inbound ranges */
1338 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1339 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1342 #interrupt-cells = <1>;
1343 interrupt-map-mask = <0 0 0 0>;
1344 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1346 clock-names = "pcie", "pcie_bus";
1347 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1348 resets = <&cpg 319>;
1349 status = "disabled";
1328 };
1329
1330 pciec1: pcie@ee800000 {
1350 };
1351
1352 pciec1: pcie@ee800000 {
1353 compatible = "renesas,pcie-r8a77961",
1354 "renesas,pcie-rcar-gen3";
1331 reg = <0 0xee800000 0 0x80000>;
1355 reg = <0 0xee800000 0 0x80000>;
1332 /* placeholder */
1356 #address-cells = <3>;
1357 #size-cells = <2>;
1358 bus-range = <0x00 0xff>;
1359 device_type = "pci";
1360 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
1361 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
1362 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
1363 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
1364 /* Map all possible DDR as inbound ranges */
1365 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1366 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1369 #interrupt-cells = <1>;
1370 interrupt-map-mask = <0 0 0 0>;
1371 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1372 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
1373 clock-names = "pcie", "pcie_bus";
1374 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1375 resets = <&cpg 318>;
1376 status = "disabled";
1333 };
1334
1335 csi20: csi2@fea80000 {
1336 reg = <0 0xfea80000 0 0x10000>;
1337 /* placeholder */
1338
1339 ports {
1340 #address-cells = <1>;

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1378
1379 csi20: csi2@fea80000 {
1380 reg = <0 0xfea80000 0 0x10000>;
1381 /* placeholder */
1382
1383 ports {
1384 #address-cells = <1>;

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