1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pin-controller@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cpg: clock-controller@e6150000 { 457 compatible = "renesas,r8a77961-cpg-mssr"; 458 reg = <0 0xe6150000 0 0x1000>; 459 clocks = <&extal_clk>, <&extalr_clk>; 460 clock-names = "extal", "extalr"; 461 #clock-cells = <2>; 462 #power-domain-cells = <0>; 463 #reset-cells = <1>; 464 }; 465 466 rst: reset-controller@e6160000 { 467 compatible = "renesas,r8a77961-rst"; 468 reg = <0 0xe6160000 0 0x0200>; 469 }; 470 471 sysc: system-controller@e6180000 { 472 compatible = "renesas,r8a77961-sysc"; 473 reg = <0 0xe6180000 0 0x0400>; 474 #power-domain-cells = <1>; 475 }; 476 477 tsc: thermal@e6198000 { 478 compatible = "renesas,r8a77961-thermal"; 479 reg = <0 0xe6198000 0 0x100>, 480 <0 0xe61a0000 0 0x100>, 481 <0 0xe61a8000 0 0x100>; 482 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cpg CPG_MOD 522>; 486 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 487 resets = <&cpg 522>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 intc_ex: interrupt-controller@e61c0000 { 492 #interrupt-cells = <2>; 493 interrupt-controller; 494 reg = <0 0xe61c0000 0 0x200>; 495 /* placeholder */ 496 }; 497 498 i2c0: i2c@e6500000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "renesas,i2c-r8a77961", 502 "renesas,rcar-gen3-i2c"; 503 reg = <0 0xe6500000 0 0x40>; 504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 931>; 506 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 507 resets = <&cpg 931>; 508 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 509 <&dmac2 0x91>, <&dmac2 0x90>; 510 dma-names = "tx", "rx", "tx", "rx"; 511 i2c-scl-internal-delay-ns = <110>; 512 status = "disabled"; 513 }; 514 515 i2c1: i2c@e6508000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "renesas,i2c-r8a77961", 519 "renesas,rcar-gen3-i2c"; 520 reg = <0 0xe6508000 0 0x40>; 521 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 930>; 523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 524 resets = <&cpg 930>; 525 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 526 <&dmac2 0x93>, <&dmac2 0x92>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 i2c-scl-internal-delay-ns = <6>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@e6510000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "renesas,i2c-r8a77961", 536 "renesas,rcar-gen3-i2c"; 537 reg = <0 0xe6510000 0 0x40>; 538 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 929>; 540 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 541 resets = <&cpg 929>; 542 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 543 <&dmac2 0x95>, <&dmac2 0x94>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 i2c-scl-internal-delay-ns = <6>; 546 status = "disabled"; 547 }; 548 549 i2c3: i2c@e66d0000 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 compatible = "renesas,i2c-r8a77961", 553 "renesas,rcar-gen3-i2c"; 554 reg = <0 0xe66d0000 0 0x40>; 555 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 928>; 557 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 558 resets = <&cpg 928>; 559 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 560 dma-names = "tx", "rx"; 561 i2c-scl-internal-delay-ns = <110>; 562 status = "disabled"; 563 }; 564 565 i2c4: i2c@e66d8000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "renesas,i2c-r8a77961", 569 "renesas,rcar-gen3-i2c"; 570 reg = <0 0xe66d8000 0 0x40>; 571 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 927>; 573 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 574 resets = <&cpg 927>; 575 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 576 dma-names = "tx", "rx"; 577 i2c-scl-internal-delay-ns = <110>; 578 status = "disabled"; 579 }; 580 581 i2c5: i2c@e66e0000 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "renesas,i2c-r8a77961", 585 "renesas,rcar-gen3-i2c"; 586 reg = <0 0xe66e0000 0 0x40>; 587 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 919>; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 919>; 591 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 592 dma-names = "tx", "rx"; 593 i2c-scl-internal-delay-ns = <110>; 594 status = "disabled"; 595 }; 596 597 i2c6: i2c@e66e8000 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 compatible = "renesas,i2c-r8a77961", 601 "renesas,rcar-gen3-i2c"; 602 reg = <0 0xe66e8000 0 0x40>; 603 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 918>; 605 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 606 resets = <&cpg 918>; 607 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 608 dma-names = "tx", "rx"; 609 i2c-scl-internal-delay-ns = <6>; 610 status = "disabled"; 611 }; 612 613 i2c_dvfs: i2c@e60b0000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "renesas,iic-r8a77961", 617 "renesas,rcar-gen3-iic", 618 "renesas,rmobile-iic"; 619 reg = <0 0xe60b0000 0 0x425>; 620 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 926>; 622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 623 resets = <&cpg 926>; 624 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 625 dma-names = "tx", "rx"; 626 status = "disabled"; 627 }; 628 629 hscif0: serial@e6540000 { 630 compatible = "renesas,hscif-r8a77961", 631 "renesas,rcar-gen3-hscif", 632 "renesas,hscif"; 633 reg = <0 0xe6540000 0 0x60>; 634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 520>, 636 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 637 <&scif_clk>; 638 clock-names = "fck", "brg_int", "scif_clk"; 639 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 640 <&dmac2 0x31>, <&dmac2 0x30>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 643 resets = <&cpg 520>; 644 status = "disabled"; 645 }; 646 647 hscif1: serial@e6550000 { 648 compatible = "renesas,hscif-r8a77961", 649 "renesas,rcar-gen3-hscif", 650 "renesas,hscif"; 651 reg = <0 0xe6550000 0 0x60>; 652 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 519>, 654 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 655 <&scif_clk>; 656 clock-names = "fck", "brg_int", "scif_clk"; 657 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 658 <&dmac2 0x33>, <&dmac2 0x32>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 661 resets = <&cpg 519>; 662 status = "disabled"; 663 }; 664 665 hscif2: serial@e6560000 { 666 compatible = "renesas,hscif-r8a77961", 667 "renesas,rcar-gen3-hscif", 668 "renesas,hscif"; 669 reg = <0 0xe6560000 0 0x60>; 670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 518>, 672 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 676 <&dmac2 0x35>, <&dmac2 0x34>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 679 resets = <&cpg 518>; 680 status = "disabled"; 681 }; 682 683 hscif3: serial@e66a0000 { 684 compatible = "renesas,hscif-r8a77961", 685 "renesas,rcar-gen3-hscif", 686 "renesas,hscif"; 687 reg = <0 0xe66a0000 0 0x60>; 688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cpg CPG_MOD 517>, 690 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 691 <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 694 dma-names = "tx", "rx"; 695 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 696 resets = <&cpg 517>; 697 status = "disabled"; 698 }; 699 700 hscif4: serial@e66b0000 { 701 compatible = "renesas,hscif-r8a77961", 702 "renesas,rcar-gen3-hscif", 703 "renesas,hscif"; 704 reg = <0 0xe66b0000 0 0x60>; 705 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 516>, 707 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 708 <&scif_clk>; 709 clock-names = "fck", "brg_int", "scif_clk"; 710 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 711 dma-names = "tx", "rx"; 712 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 713 resets = <&cpg 516>; 714 status = "disabled"; 715 }; 716 717 hsusb: usb@e6590000 { 718 compatible = "renesas,usbhs-r8a77961", 719 "renesas,rcar-gen3-usbhs"; 720 reg = <0 0xe6590000 0 0x200>; 721 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 723 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 724 <&usb_dmac1 0>, <&usb_dmac1 1>; 725 dma-names = "ch0", "ch1", "ch2", "ch3"; 726 renesas,buswait = <11>; 727 phys = <&usb2_phy0 3>; 728 phy-names = "usb"; 729 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 730 resets = <&cpg 704>, <&cpg 703>; 731 status = "disabled"; 732 }; 733 734 usb_dmac0: dma-controller@e65a0000 { 735 compatible = "renesas,r8a77961-usb-dmac", 736 "renesas,usb-dmac"; 737 reg = <0 0xe65a0000 0 0x100>; 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "ch0", "ch1"; 741 clocks = <&cpg CPG_MOD 330>; 742 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 743 resets = <&cpg 330>; 744 #dma-cells = <1>; 745 dma-channels = <2>; 746 }; 747 748 usb_dmac1: dma-controller@e65b0000 { 749 compatible = "renesas,r8a77961-usb-dmac", 750 "renesas,usb-dmac"; 751 reg = <0 0xe65b0000 0 0x100>; 752 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0", "ch1"; 755 clocks = <&cpg CPG_MOD 331>; 756 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 757 resets = <&cpg 331>; 758 #dma-cells = <1>; 759 dma-channels = <2>; 760 }; 761 762 usb3_phy0: usb-phy@e65ee000 { 763 compatible = "renesas,r8a77961-usb3-phy", 764 "renesas,rcar-gen3-usb3-phy"; 765 reg = <0 0xe65ee000 0 0x90>; 766 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 767 <&usb_extal_clk>; 768 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 769 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 770 resets = <&cpg 328>; 771 #phy-cells = <0>; 772 status = "disabled"; 773 }; 774 775 arm_cc630p: crypto@e6601000 { 776 compatible = "arm,cryptocell-630p-ree"; 777 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x0 0xe6601000 0 0x1000>; 779 clocks = <&cpg CPG_MOD 229>; 780 resets = <&cpg 229>; 781 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 782 }; 783 784 dmac0: dma-controller@e6700000 { 785 compatible = "renesas,dmac-r8a77961", 786 "renesas,rcar-dmac"; 787 reg = <0 0xe6700000 0 0x10000>; 788 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-names = "error", 806 "ch0", "ch1", "ch2", "ch3", 807 "ch4", "ch5", "ch6", "ch7", 808 "ch8", "ch9", "ch10", "ch11", 809 "ch12", "ch13", "ch14", "ch15"; 810 clocks = <&cpg CPG_MOD 219>; 811 clock-names = "fck"; 812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 813 resets = <&cpg 219>; 814 #dma-cells = <1>; 815 dma-channels = <16>; 816 }; 817 818 dmac1: dma-controller@e7300000 { 819 compatible = "renesas,dmac-r8a77961", 820 "renesas,rcar-dmac"; 821 reg = <0 0xe7300000 0 0x10000>; 822 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "error", 840 "ch0", "ch1", "ch2", "ch3", 841 "ch4", "ch5", "ch6", "ch7", 842 "ch8", "ch9", "ch10", "ch11", 843 "ch12", "ch13", "ch14", "ch15"; 844 clocks = <&cpg CPG_MOD 218>; 845 clock-names = "fck"; 846 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 847 resets = <&cpg 218>; 848 #dma-cells = <1>; 849 dma-channels = <16>; 850 }; 851 852 dmac2: dma-controller@e7310000 { 853 compatible = "renesas,dmac-r8a77961", 854 "renesas,rcar-dmac"; 855 reg = <0 0xe7310000 0 0x10000>; 856 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "error", 874 "ch0", "ch1", "ch2", "ch3", 875 "ch4", "ch5", "ch6", "ch7", 876 "ch8", "ch9", "ch10", "ch11", 877 "ch12", "ch13", "ch14", "ch15"; 878 clocks = <&cpg CPG_MOD 217>; 879 clock-names = "fck"; 880 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 881 resets = <&cpg 217>; 882 #dma-cells = <1>; 883 dma-channels = <16>; 884 }; 885 886 avb: ethernet@e6800000 { 887 compatible = "renesas,etheravb-r8a77961", 888 "renesas,etheravb-rcar-gen3"; 889 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 890 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "ch0", "ch1", "ch2", "ch3", 916 "ch4", "ch5", "ch6", "ch7", 917 "ch8", "ch9", "ch10", "ch11", 918 "ch12", "ch13", "ch14", "ch15", 919 "ch16", "ch17", "ch18", "ch19", 920 "ch20", "ch21", "ch22", "ch23", 921 "ch24"; 922 clocks = <&cpg CPG_MOD 812>; 923 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 924 resets = <&cpg 812>; 925 phy-mode = "rgmii"; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 pwm0: pwm@e6e30000 { 932 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 933 reg = <0 0xe6e30000 0 8>; 934 #pwm-cells = <2>; 935 clocks = <&cpg CPG_MOD 523>; 936 resets = <&cpg 523>; 937 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 938 status = "disabled"; 939 }; 940 941 pwm1: pwm@e6e31000 { 942 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 943 reg = <0 0xe6e31000 0 8>; 944 #pwm-cells = <2>; 945 clocks = <&cpg CPG_MOD 523>; 946 resets = <&cpg 523>; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 status = "disabled"; 949 }; 950 951 pwm2: pwm@e6e32000 { 952 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 953 reg = <0 0xe6e32000 0 8>; 954 #pwm-cells = <2>; 955 clocks = <&cpg CPG_MOD 523>; 956 resets = <&cpg 523>; 957 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 958 status = "disabled"; 959 }; 960 961 pwm3: pwm@e6e33000 { 962 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 963 reg = <0 0xe6e33000 0 8>; 964 #pwm-cells = <2>; 965 clocks = <&cpg CPG_MOD 523>; 966 resets = <&cpg 523>; 967 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 968 status = "disabled"; 969 }; 970 971 pwm4: pwm@e6e34000 { 972 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 973 reg = <0 0xe6e34000 0 8>; 974 #pwm-cells = <2>; 975 clocks = <&cpg CPG_MOD 523>; 976 resets = <&cpg 523>; 977 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 978 status = "disabled"; 979 }; 980 981 pwm5: pwm@e6e35000 { 982 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 983 reg = <0 0xe6e35000 0 8>; 984 #pwm-cells = <2>; 985 clocks = <&cpg CPG_MOD 523>; 986 resets = <&cpg 523>; 987 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 988 status = "disabled"; 989 }; 990 991 pwm6: pwm@e6e36000 { 992 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 993 reg = <0 0xe6e36000 0 8>; 994 #pwm-cells = <2>; 995 clocks = <&cpg CPG_MOD 523>; 996 resets = <&cpg 523>; 997 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 998 status = "disabled"; 999 }; 1000 1001 scif0: serial@e6e60000 { 1002 compatible = "renesas,scif-r8a77961", 1003 "renesas,rcar-gen3-scif", "renesas,scif"; 1004 reg = <0 0xe6e60000 0 64>; 1005 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cpg CPG_MOD 207>, 1007 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1008 <&scif_clk>; 1009 clock-names = "fck", "brg_int", "scif_clk"; 1010 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1011 <&dmac2 0x51>, <&dmac2 0x50>; 1012 dma-names = "tx", "rx", "tx", "rx"; 1013 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1014 resets = <&cpg 207>; 1015 status = "disabled"; 1016 }; 1017 1018 scif1: serial@e6e68000 { 1019 compatible = "renesas,scif-r8a77961", 1020 "renesas,rcar-gen3-scif", "renesas,scif"; 1021 reg = <0 0xe6e68000 0 64>; 1022 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 206>, 1024 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1025 <&scif_clk>; 1026 clock-names = "fck", "brg_int", "scif_clk"; 1027 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1028 <&dmac2 0x53>, <&dmac2 0x52>; 1029 dma-names = "tx", "rx", "tx", "rx"; 1030 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1031 resets = <&cpg 206>; 1032 status = "disabled"; 1033 }; 1034 1035 scif2: serial@e6e88000 { 1036 compatible = "renesas,scif-r8a77961", 1037 "renesas,rcar-gen3-scif", "renesas,scif"; 1038 reg = <0 0xe6e88000 0 64>; 1039 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cpg CPG_MOD 310>, 1041 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1042 <&scif_clk>; 1043 clock-names = "fck", "brg_int", "scif_clk"; 1044 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1045 <&dmac2 0x13>, <&dmac2 0x12>; 1046 dma-names = "tx", "rx", "tx", "rx"; 1047 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1048 resets = <&cpg 310>; 1049 status = "disabled"; 1050 }; 1051 1052 scif3: serial@e6c50000 { 1053 compatible = "renesas,scif-r8a77961", 1054 "renesas,rcar-gen3-scif", "renesas,scif"; 1055 reg = <0 0xe6c50000 0 64>; 1056 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&cpg CPG_MOD 204>, 1058 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1059 <&scif_clk>; 1060 clock-names = "fck", "brg_int", "scif_clk"; 1061 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1062 dma-names = "tx", "rx"; 1063 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1064 resets = <&cpg 204>; 1065 status = "disabled"; 1066 }; 1067 1068 scif4: serial@e6c40000 { 1069 compatible = "renesas,scif-r8a77961", 1070 "renesas,rcar-gen3-scif", "renesas,scif"; 1071 reg = <0 0xe6c40000 0 64>; 1072 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&cpg CPG_MOD 203>, 1074 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1075 <&scif_clk>; 1076 clock-names = "fck", "brg_int", "scif_clk"; 1077 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1078 dma-names = "tx", "rx"; 1079 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1080 resets = <&cpg 203>; 1081 status = "disabled"; 1082 }; 1083 1084 scif5: serial@e6f30000 { 1085 compatible = "renesas,scif-r8a77961", 1086 "renesas,rcar-gen3-scif", "renesas,scif"; 1087 reg = <0 0xe6f30000 0 64>; 1088 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&cpg CPG_MOD 202>, 1090 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1091 <&scif_clk>; 1092 clock-names = "fck", "brg_int", "scif_clk"; 1093 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1094 <&dmac2 0x5b>, <&dmac2 0x5a>; 1095 dma-names = "tx", "rx", "tx", "rx"; 1096 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1097 resets = <&cpg 202>; 1098 status = "disabled"; 1099 }; 1100 1101 vin0: video@e6ef0000 { 1102 reg = <0 0xe6ef0000 0 0x1000>; 1103 /* placeholder */ 1104 }; 1105 1106 vin1: video@e6ef1000 { 1107 reg = <0 0xe6ef1000 0 0x1000>; 1108 /* placeholder */ 1109 }; 1110 1111 vin2: video@e6ef2000 { 1112 reg = <0 0xe6ef2000 0 0x1000>; 1113 /* placeholder */ 1114 }; 1115 1116 vin3: video@e6ef3000 { 1117 reg = <0 0xe6ef3000 0 0x1000>; 1118 /* placeholder */ 1119 }; 1120 1121 vin4: video@e6ef4000 { 1122 reg = <0 0xe6ef4000 0 0x1000>; 1123 /* placeholder */ 1124 }; 1125 1126 vin5: video@e6ef5000 { 1127 reg = <0 0xe6ef5000 0 0x1000>; 1128 /* placeholder */ 1129 }; 1130 1131 vin6: video@e6ef6000 { 1132 reg = <0 0xe6ef6000 0 0x1000>; 1133 /* placeholder */ 1134 }; 1135 1136 vin7: video@e6ef7000 { 1137 reg = <0 0xe6ef7000 0 0x1000>; 1138 /* placeholder */ 1139 }; 1140 1141 rcar_sound: sound@ec500000 { 1142 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1143 <0 0xec5a0000 0 0x100>, /* ADG */ 1144 <0 0xec540000 0 0x1000>, /* SSIU */ 1145 <0 0xec541000 0 0x280>, /* SSI */ 1146 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1147 /* placeholder */ 1148 rcar_sound,dvc { 1149 dvc0: dvc-0 { }; 1150 dvc1: dvc-1 { }; 1151 }; 1152 1153 rcar_sound,src { 1154 src0: src-0 { }; 1155 src1: src-1 { }; 1156 }; 1157 1158 rcar_sound,ssi { 1159 ssi0: ssi-0 { }; 1160 ssi1: ssi-1 { }; 1161 ssi2: ssi-2 { }; 1162 }; 1163 }; 1164 1165 xhci0: usb@ee000000 { 1166 compatible = "renesas,xhci-r8a77961", 1167 "renesas,rcar-gen3-xhci"; 1168 reg = <0 0xee000000 0 0xc00>; 1169 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&cpg CPG_MOD 328>; 1171 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1172 resets = <&cpg 328>; 1173 status = "disabled"; 1174 }; 1175 1176 usb3_peri0: usb@ee020000 { 1177 compatible = "renesas,r8a77961-usb3-peri", 1178 "renesas,rcar-gen3-usb3-peri"; 1179 reg = <0 0xee020000 0 0x400>; 1180 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&cpg CPG_MOD 328>; 1182 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1183 resets = <&cpg 328>; 1184 status = "disabled"; 1185 }; 1186 1187 ohci0: usb@ee080000 { 1188 compatible = "generic-ohci"; 1189 reg = <0 0xee080000 0 0x100>; 1190 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1191 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1192 phys = <&usb2_phy0 1>; 1193 phy-names = "usb"; 1194 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1195 resets = <&cpg 703>, <&cpg 704>; 1196 status = "disabled"; 1197 }; 1198 1199 ohci1: usb@ee0a0000 { 1200 compatible = "generic-ohci"; 1201 reg = <0 0xee0a0000 0 0x100>; 1202 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&cpg CPG_MOD 702>; 1204 phys = <&usb2_phy1 1>; 1205 phy-names = "usb"; 1206 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1207 resets = <&cpg 702>; 1208 status = "disabled"; 1209 }; 1210 1211 ehci0: usb@ee080100 { 1212 compatible = "generic-ehci"; 1213 reg = <0 0xee080100 0 0x100>; 1214 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1216 phys = <&usb2_phy0 2>; 1217 phy-names = "usb"; 1218 companion = <&ohci0>; 1219 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1220 resets = <&cpg 703>, <&cpg 704>; 1221 status = "disabled"; 1222 }; 1223 1224 ehci1: usb@ee0a0100 { 1225 compatible = "generic-ehci"; 1226 reg = <0 0xee0a0100 0 0x100>; 1227 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cpg CPG_MOD 702>; 1229 phys = <&usb2_phy1 2>; 1230 phy-names = "usb"; 1231 companion = <&ohci1>; 1232 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1233 resets = <&cpg 702>; 1234 status = "disabled"; 1235 }; 1236 1237 usb2_phy0: usb-phy@ee080200 { 1238 compatible = "renesas,usb2-phy-r8a77961", 1239 "renesas,rcar-gen3-usb2-phy"; 1240 reg = <0 0xee080200 0 0x700>; 1241 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1243 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1244 resets = <&cpg 703>, <&cpg 704>; 1245 #phy-cells = <1>; 1246 status = "disabled"; 1247 }; 1248 1249 usb2_phy1: usb-phy@ee0a0200 { 1250 compatible = "renesas,usb2-phy-r8a77961", 1251 "renesas,rcar-gen3-usb2-phy"; 1252 reg = <0 0xee0a0200 0 0x700>; 1253 clocks = <&cpg CPG_MOD 702>; 1254 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1255 resets = <&cpg 702>; 1256 #phy-cells = <1>; 1257 status = "disabled"; 1258 }; 1259 1260 sdhi0: sd@ee100000 { 1261 compatible = "renesas,sdhi-r8a77961", 1262 "renesas,rcar-gen3-sdhi"; 1263 reg = <0 0xee100000 0 0x2000>; 1264 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cpg CPG_MOD 314>; 1266 max-frequency = <200000000>; 1267 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1268 resets = <&cpg 314>; 1269 status = "disabled"; 1270 }; 1271 1272 sdhi1: sd@ee120000 { 1273 compatible = "renesas,sdhi-r8a77961", 1274 "renesas,rcar-gen3-sdhi"; 1275 reg = <0 0xee120000 0 0x2000>; 1276 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1277 clocks = <&cpg CPG_MOD 313>; 1278 max-frequency = <200000000>; 1279 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1280 resets = <&cpg 313>; 1281 status = "disabled"; 1282 }; 1283 1284 sdhi2: sd@ee140000 { 1285 compatible = "renesas,sdhi-r8a77961", 1286 "renesas,rcar-gen3-sdhi"; 1287 reg = <0 0xee140000 0 0x2000>; 1288 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cpg CPG_MOD 312>; 1290 max-frequency = <200000000>; 1291 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1292 resets = <&cpg 312>; 1293 status = "disabled"; 1294 }; 1295 1296 sdhi3: sd@ee160000 { 1297 compatible = "renesas,sdhi-r8a77961", 1298 "renesas,rcar-gen3-sdhi"; 1299 reg = <0 0xee160000 0 0x2000>; 1300 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1301 clocks = <&cpg CPG_MOD 311>; 1302 max-frequency = <200000000>; 1303 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1304 resets = <&cpg 311>; 1305 status = "disabled"; 1306 }; 1307 1308 gic: interrupt-controller@f1010000 { 1309 compatible = "arm,gic-400"; 1310 #interrupt-cells = <3>; 1311 #address-cells = <0>; 1312 interrupt-controller; 1313 reg = <0x0 0xf1010000 0 0x1000>, 1314 <0x0 0xf1020000 0 0x20000>, 1315 <0x0 0xf1040000 0 0x20000>, 1316 <0x0 0xf1060000 0 0x20000>; 1317 interrupts = <GIC_PPI 9 1318 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1319 clocks = <&cpg CPG_MOD 408>; 1320 clock-names = "clk"; 1321 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1322 resets = <&cpg 408>; 1323 }; 1324 1325 pciec0: pcie@fe000000 { 1326 reg = <0 0xfe000000 0 0x80000>; 1327 /* placeholder */ 1328 }; 1329 1330 pciec1: pcie@ee800000 { 1331 reg = <0 0xee800000 0 0x80000>; 1332 /* placeholder */ 1333 }; 1334 1335 csi20: csi2@fea80000 { 1336 reg = <0 0xfea80000 0 0x10000>; 1337 /* placeholder */ 1338 1339 ports { 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 1343 port@1 { 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 reg = <1>; 1347 }; 1348 }; 1349 }; 1350 1351 csi40: csi2@feaa0000 { 1352 reg = <0 0xfeaa0000 0 0x10000>; 1353 /* placeholder */ 1354 1355 ports { 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 1359 port@1 { 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 1363 reg = <1>; 1364 }; 1365 }; 1366 }; 1367 1368 hdmi0: hdmi@fead0000 { 1369 reg = <0 0xfead0000 0 0x10000>; 1370 /* placeholder */ 1371 1372 ports { 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 port@0 { 1376 reg = <0>; 1377 }; 1378 port@1 { 1379 reg = <1>; 1380 }; 1381 port@2 { 1382 /* HDMI sound */ 1383 reg = <2>; 1384 }; 1385 }; 1386 }; 1387 1388 du: display@feb00000 { 1389 reg = <0 0xfeb00000 0 0x70000>; 1390 /* placeholder */ 1391 1392 ports { 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 1396 port@0 { 1397 reg = <0>; 1398 du_out_rgb: endpoint { 1399 }; 1400 }; 1401 port@1 { 1402 reg = <1>; 1403 du_out_hdmi0: endpoint { 1404 }; 1405 }; 1406 port@2 { 1407 reg = <2>; 1408 du_out_lvds0: endpoint { 1409 }; 1410 }; 1411 }; 1412 }; 1413 1414 prr: chipid@fff00044 { 1415 compatible = "renesas,prr"; 1416 reg = <0 0xfff00044 0 4>; 1417 }; 1418 }; 1419 1420 thermal-zones { 1421 sensor_thermal1: sensor-thermal1 { 1422 polling-delay-passive = <250>; 1423 polling-delay = <1000>; 1424 thermal-sensors = <&tsc 0>; 1425 sustainable-power = <3874>; 1426 1427 trips { 1428 sensor1_crit: sensor1-crit { 1429 temperature = <120000>; 1430 hysteresis = <1000>; 1431 type = "critical"; 1432 }; 1433 }; 1434 }; 1435 1436 sensor_thermal2: sensor-thermal2 { 1437 polling-delay-passive = <250>; 1438 polling-delay = <1000>; 1439 thermal-sensors = <&tsc 1>; 1440 sustainable-power = <3874>; 1441 1442 trips { 1443 sensor2_crit: sensor2-crit { 1444 temperature = <120000>; 1445 hysteresis = <1000>; 1446 type = "critical"; 1447 }; 1448 }; 1449 }; 1450 1451 sensor_thermal3: sensor-thermal3 { 1452 polling-delay-passive = <250>; 1453 polling-delay = <1000>; 1454 thermal-sensors = <&tsc 2>; 1455 sustainable-power = <3874>; 1456 1457 cooling-maps { 1458 map0 { 1459 trip = <&target>; 1460 cooling-device = <&a57_0 2 4>; 1461 contribution = <1024>; 1462 }; 1463 map1 { 1464 trip = <&target>; 1465 cooling-device = <&a53_0 0 2>; 1466 contribution = <1024>; 1467 }; 1468 }; 1469 trips { 1470 target: trip-point1 { 1471 temperature = <100000>; 1472 hysteresis = <1000>; 1473 type = "passive"; 1474 }; 1475 1476 sensor3_crit: sensor3-crit { 1477 temperature = <120000>; 1478 hysteresis = <1000>; 1479 type = "critical"; 1480 }; 1481 }; 1482 }; 1483 }; 1484 1485 timer { 1486 compatible = "arm,armv8-timer"; 1487 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 1488 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 1489 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 1490 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 1491 }; 1492 1493 /* External USB clocks - can be overridden by the board */ 1494 usb3s0_clk: usb3s0 { 1495 compatible = "fixed-clock"; 1496 #clock-cells = <0>; 1497 clock-frequency = <0>; 1498 }; 1499 1500 usb_extal_clk: usb_extal { 1501 compatible = "fixed-clock"; 1502 #clock-cells = <0>; 1503 clock-frequency = <0>; 1504 }; 1505}; 1506