r8a774e1.dtsi (8d54886cbb4efb6e7a35ee1c7d0e9d91b4c73ca9) r8a774e1.dtsi (d18dbce4e8c02634866dc80c7873e6121fcae970)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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29 };
30
31 audio_clk_c: audio_clk_c {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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29 };
30
31 audio_clk_c: audio_clk_c {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
37 cluster0_opp: opp_table0 {
38 compatible = "operating-points-v2";
39 opp-shared;
40
41 opp-500000000 {
42 opp-hz = /bits/ 64 <500000000>;
43 opp-microvolt = <820000>;
44 clock-latency-ns = <300000>;
45 };
46 opp-1000000000 {
47 opp-hz = /bits/ 64 <1000000000>;
48 opp-microvolt = <820000>;
49 clock-latency-ns = <300000>;
50 };
51 opp-1500000000 {
52 opp-hz = /bits/ 64 <1500000000>;
53 opp-microvolt = <820000>;
54 clock-latency-ns = <300000>;
55 opp-suspend;
56 };
57 };
58
59 cluster1_opp: opp_table1 {
60 compatible = "operating-points-v2";
61 opp-shared;
62
63 opp-800000000 {
64 opp-hz = /bits/ 64 <800000000>;
65 opp-microvolt = <820000>;
66 clock-latency-ns = <300000>;
67 };
68 opp-1000000000 {
69 opp-hz = /bits/ 64 <1000000000>;
70 opp-microvolt = <820000>;
71 clock-latency-ns = <300000>;
72 };
73 opp-1200000000 {
74 opp-hz = /bits/ 64 <1200000000>;
75 opp-microvolt = <820000>;
76 clock-latency-ns = <300000>;
77 };
78 };
79
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu-map {
42 cluster0 {
43 core0 {
44 cpu = <&a57_0>;

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74 compatible = "arm,cortex-a57";
75 reg = <0x0>;
76 device_type = "cpu";
77 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
78 next-level-cache = <&L2_CA57>;
79 enable-method = "psci";
80 dynamic-power-coefficient = <854>;
81 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu-map {
85 cluster0 {
86 core0 {
87 cpu = <&a57_0>;

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117 compatible = "arm,cortex-a57";
118 reg = <0x0>;
119 device_type = "cpu";
120 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
121 next-level-cache = <&L2_CA57>;
122 enable-method = "psci";
123 dynamic-power-coefficient = <854>;
124 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
125 operating-points-v2 = <&cluster0_opp>;
82 capacity-dmips-mhz = <1024>;
83 #cooling-cells = <2>;
84 };
85
86 a57_1: cpu@1 {
87 compatible = "arm,cortex-a57";
88 reg = <0x1>;
89 device_type = "cpu";
90 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
91 next-level-cache = <&L2_CA57>;
92 enable-method = "psci";
93 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
126 capacity-dmips-mhz = <1024>;
127 #cooling-cells = <2>;
128 };
129
130 a57_1: cpu@1 {
131 compatible = "arm,cortex-a57";
132 reg = <0x1>;
133 device_type = "cpu";
134 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
135 next-level-cache = <&L2_CA57>;
136 enable-method = "psci";
137 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
138 operating-points-v2 = <&cluster0_opp>;
94 capacity-dmips-mhz = <1024>;
95 #cooling-cells = <2>;
96 };
97
98 a57_2: cpu@2 {
99 compatible = "arm,cortex-a57";
100 reg = <0x2>;
101 device_type = "cpu";
102 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
103 next-level-cache = <&L2_CA57>;
104 enable-method = "psci";
105 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
139 capacity-dmips-mhz = <1024>;
140 #cooling-cells = <2>;
141 };
142
143 a57_2: cpu@2 {
144 compatible = "arm,cortex-a57";
145 reg = <0x2>;
146 device_type = "cpu";
147 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
148 next-level-cache = <&L2_CA57>;
149 enable-method = "psci";
150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
151 operating-points-v2 = <&cluster0_opp>;
106 capacity-dmips-mhz = <1024>;
107 #cooling-cells = <2>;
108 };
109
110 a57_3: cpu@3 {
111 compatible = "arm,cortex-a57";
112 reg = <0x3>;
113 device_type = "cpu";
114 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
115 next-level-cache = <&L2_CA57>;
116 enable-method = "psci";
117 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
154 };
155
156 a57_3: cpu@3 {
157 compatible = "arm,cortex-a57";
158 reg = <0x3>;
159 device_type = "cpu";
160 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
161 next-level-cache = <&L2_CA57>;
162 enable-method = "psci";
163 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
164 operating-points-v2 = <&cluster0_opp>;
118 capacity-dmips-mhz = <1024>;
119 #cooling-cells = <2>;
120 };
121
122 a53_0: cpu@100 {
123 compatible = "arm,cortex-a53";
124 reg = <0x100>;
125 device_type = "cpu";
126 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
127 next-level-cache = <&L2_CA53>;
128 enable-method = "psci";
129 #cooling-cells = <2>;
130 dynamic-power-coefficient = <277>;
131 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
165 capacity-dmips-mhz = <1024>;
166 #cooling-cells = <2>;
167 };
168
169 a53_0: cpu@100 {
170 compatible = "arm,cortex-a53";
171 reg = <0x100>;
172 device_type = "cpu";
173 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
174 next-level-cache = <&L2_CA53>;
175 enable-method = "psci";
176 #cooling-cells = <2>;
177 dynamic-power-coefficient = <277>;
178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
179 operating-points-v2 = <&cluster1_opp>;
132 capacity-dmips-mhz = <535>;
133 };
134
135 a53_1: cpu@101 {
136 compatible = "arm,cortex-a53";
137 reg = <0x101>;
138 device_type = "cpu";
139 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
140 next-level-cache = <&L2_CA53>;
141 enable-method = "psci";
142 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
180 capacity-dmips-mhz = <535>;
181 };
182
183 a53_1: cpu@101 {
184 compatible = "arm,cortex-a53";
185 reg = <0x101>;
186 device_type = "cpu";
187 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
188 next-level-cache = <&L2_CA53>;
189 enable-method = "psci";
190 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
191 operating-points-v2 = <&cluster1_opp>;
143 capacity-dmips-mhz = <535>;
144 };
145
146 a53_2: cpu@102 {
147 compatible = "arm,cortex-a53";
148 reg = <0x102>;
149 device_type = "cpu";
150 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
151 next-level-cache = <&L2_CA53>;
152 enable-method = "psci";
153 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
192 capacity-dmips-mhz = <535>;
193 };
194
195 a53_2: cpu@102 {
196 compatible = "arm,cortex-a53";
197 reg = <0x102>;
198 device_type = "cpu";
199 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
200 next-level-cache = <&L2_CA53>;
201 enable-method = "psci";
202 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
203 operating-points-v2 = <&cluster1_opp>;
154 capacity-dmips-mhz = <535>;
155 };
156
157 a53_3: cpu@103 {
158 compatible = "arm,cortex-a53";
159 reg = <0x103>;
160 device_type = "cpu";
161 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
162 next-level-cache = <&L2_CA53>;
163 enable-method = "psci";
164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
204 capacity-dmips-mhz = <535>;
205 };
206
207 a53_3: cpu@103 {
208 compatible = "arm,cortex-a53";
209 reg = <0x103>;
210 device_type = "cpu";
211 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
212 next-level-cache = <&L2_CA53>;
213 enable-method = "psci";
214 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
215 operating-points-v2 = <&cluster1_opp>;
165 capacity-dmips-mhz = <535>;
166 };
167
168 L2_CA57: cache-controller-0 {
169 compatible = "cache";
170 power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
171 cache-unified;
172 cache-level = <2>;

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217 };
218
219 L2_CA57: cache-controller-0 {
220 compatible = "cache";
221 power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
222 cache-unified;
223 cache-level = <2>;

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