1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 cluster0_opp: opp_table0 { 38 compatible = "operating-points-v2"; 39 opp-shared; 40 41 opp-500000000 { 42 opp-hz = /bits/ 64 <500000000>; 43 opp-microvolt = <820000>; 44 clock-latency-ns = <300000>; 45 }; 46 opp-1000000000 { 47 opp-hz = /bits/ 64 <1000000000>; 48 opp-microvolt = <820000>; 49 clock-latency-ns = <300000>; 50 }; 51 opp-1500000000 { 52 opp-hz = /bits/ 64 <1500000000>; 53 opp-microvolt = <820000>; 54 clock-latency-ns = <300000>; 55 opp-suspend; 56 }; 57 }; 58 59 cluster1_opp: opp_table1 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-800000000 { 64 opp-hz = /bits/ 64 <800000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1200000000 { 74 opp-hz = /bits/ 64 <1200000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 cpu-map { 85 cluster0 { 86 core0 { 87 cpu = <&a57_0>; 88 }; 89 core1 { 90 cpu = <&a57_1>; 91 }; 92 core2 { 93 cpu = <&a57_2>; 94 }; 95 core3 { 96 cpu = <&a57_3>; 97 }; 98 }; 99 100 cluster1 { 101 core0 { 102 cpu = <&a53_0>; 103 }; 104 core1 { 105 cpu = <&a53_1>; 106 }; 107 core2 { 108 cpu = <&a53_2>; 109 }; 110 core3 { 111 cpu = <&a53_3>; 112 }; 113 }; 114 }; 115 116 a57_0: cpu@0 { 117 compatible = "arm,cortex-a57"; 118 reg = <0x0>; 119 device_type = "cpu"; 120 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 121 next-level-cache = <&L2_CA57>; 122 enable-method = "psci"; 123 dynamic-power-coefficient = <854>; 124 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 125 operating-points-v2 = <&cluster0_opp>; 126 capacity-dmips-mhz = <1024>; 127 #cooling-cells = <2>; 128 }; 129 130 a57_1: cpu@1 { 131 compatible = "arm,cortex-a57"; 132 reg = <0x1>; 133 device_type = "cpu"; 134 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 135 next-level-cache = <&L2_CA57>; 136 enable-method = "psci"; 137 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 138 operating-points-v2 = <&cluster0_opp>; 139 capacity-dmips-mhz = <1024>; 140 #cooling-cells = <2>; 141 }; 142 143 a57_2: cpu@2 { 144 compatible = "arm,cortex-a57"; 145 reg = <0x2>; 146 device_type = "cpu"; 147 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 148 next-level-cache = <&L2_CA57>; 149 enable-method = "psci"; 150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 151 operating-points-v2 = <&cluster0_opp>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 }; 155 156 a57_3: cpu@3 { 157 compatible = "arm,cortex-a57"; 158 reg = <0x3>; 159 device_type = "cpu"; 160 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 161 next-level-cache = <&L2_CA57>; 162 enable-method = "psci"; 163 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 164 operating-points-v2 = <&cluster0_opp>; 165 capacity-dmips-mhz = <1024>; 166 #cooling-cells = <2>; 167 }; 168 169 a53_0: cpu@100 { 170 compatible = "arm,cortex-a53"; 171 reg = <0x100>; 172 device_type = "cpu"; 173 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 174 next-level-cache = <&L2_CA53>; 175 enable-method = "psci"; 176 #cooling-cells = <2>; 177 dynamic-power-coefficient = <277>; 178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 179 operating-points-v2 = <&cluster1_opp>; 180 capacity-dmips-mhz = <535>; 181 }; 182 183 a53_1: cpu@101 { 184 compatible = "arm,cortex-a53"; 185 reg = <0x101>; 186 device_type = "cpu"; 187 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 188 next-level-cache = <&L2_CA53>; 189 enable-method = "psci"; 190 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 191 operating-points-v2 = <&cluster1_opp>; 192 capacity-dmips-mhz = <535>; 193 }; 194 195 a53_2: cpu@102 { 196 compatible = "arm,cortex-a53"; 197 reg = <0x102>; 198 device_type = "cpu"; 199 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 200 next-level-cache = <&L2_CA53>; 201 enable-method = "psci"; 202 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 203 operating-points-v2 = <&cluster1_opp>; 204 capacity-dmips-mhz = <535>; 205 }; 206 207 a53_3: cpu@103 { 208 compatible = "arm,cortex-a53"; 209 reg = <0x103>; 210 device_type = "cpu"; 211 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 212 next-level-cache = <&L2_CA53>; 213 enable-method = "psci"; 214 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 215 operating-points-v2 = <&cluster1_opp>; 216 capacity-dmips-mhz = <535>; 217 }; 218 219 L2_CA57: cache-controller-0 { 220 compatible = "cache"; 221 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 222 cache-unified; 223 cache-level = <2>; 224 }; 225 226 L2_CA53: cache-controller-1 { 227 compatible = "cache"; 228 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 229 cache-unified; 230 cache-level = <2>; 231 }; 232 }; 233 234 extal_clk: extal { 235 compatible = "fixed-clock"; 236 #clock-cells = <0>; 237 /* This value must be overridden by the board */ 238 clock-frequency = <0>; 239 }; 240 241 extalr_clk: extalr { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 /* This value must be overridden by the board */ 245 clock-frequency = <0>; 246 }; 247 248 /* External PCIe clock - can be overridden by the board */ 249 pcie_bus_clk: pcie_bus { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <0>; 253 }; 254 255 pmu_a53 { 256 compatible = "arm,cortex-a53-pmu"; 257 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 258 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 260 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 262 }; 263 264 pmu_a57 { 265 compatible = "arm,cortex-a57-pmu"; 266 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 267 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 268 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 269 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 271 }; 272 273 psci { 274 compatible = "arm,psci-1.0", "arm,psci-0.2"; 275 method = "smc"; 276 }; 277 278 /* External SCIF clock - to be overridden by boards that provide it */ 279 scif_clk: scif { 280 compatible = "fixed-clock"; 281 #clock-cells = <0>; 282 clock-frequency = <0>; 283 }; 284 285 soc { 286 compatible = "simple-bus"; 287 interrupt-parent = <&gic>; 288 #address-cells = <2>; 289 #size-cells = <2>; 290 ranges; 291 292 rwdt: watchdog@e6020000 { 293 reg = <0 0xe6020000 0 0x0c>; 294 status = "disabled"; 295 296 /* placeholder */ 297 }; 298 299 gpio0: gpio@e6050000 { 300 compatible = "renesas,gpio-r8a774e1", 301 "renesas,rcar-gen3-gpio"; 302 reg = <0 0xe6050000 0 0x50>; 303 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 304 #gpio-cells = <2>; 305 gpio-controller; 306 gpio-ranges = <&pfc 0 0 16>; 307 #interrupt-cells = <2>; 308 interrupt-controller; 309 clocks = <&cpg CPG_MOD 912>; 310 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 311 resets = <&cpg 912>; 312 }; 313 314 gpio1: gpio@e6051000 { 315 compatible = "renesas,gpio-r8a774e1", 316 "renesas,rcar-gen3-gpio"; 317 reg = <0 0xe6051000 0 0x50>; 318 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 319 #gpio-cells = <2>; 320 gpio-controller; 321 gpio-ranges = <&pfc 0 32 29>; 322 #interrupt-cells = <2>; 323 interrupt-controller; 324 clocks = <&cpg CPG_MOD 911>; 325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 326 resets = <&cpg 911>; 327 }; 328 329 gpio2: gpio@e6052000 { 330 compatible = "renesas,gpio-r8a774e1", 331 "renesas,rcar-gen3-gpio"; 332 reg = <0 0xe6052000 0 0x50>; 333 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 #gpio-cells = <2>; 335 gpio-controller; 336 gpio-ranges = <&pfc 0 64 15>; 337 #interrupt-cells = <2>; 338 interrupt-controller; 339 clocks = <&cpg CPG_MOD 910>; 340 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 341 resets = <&cpg 910>; 342 }; 343 344 gpio3: gpio@e6053000 { 345 compatible = "renesas,gpio-r8a774e1", 346 "renesas,rcar-gen3-gpio"; 347 reg = <0 0xe6053000 0 0x50>; 348 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 349 #gpio-cells = <2>; 350 gpio-controller; 351 gpio-ranges = <&pfc 0 96 16>; 352 #interrupt-cells = <2>; 353 interrupt-controller; 354 clocks = <&cpg CPG_MOD 909>; 355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 356 resets = <&cpg 909>; 357 }; 358 359 gpio4: gpio@e6054000 { 360 compatible = "renesas,gpio-r8a774e1", 361 "renesas,rcar-gen3-gpio"; 362 reg = <0 0xe6054000 0 0x50>; 363 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 364 #gpio-cells = <2>; 365 gpio-controller; 366 gpio-ranges = <&pfc 0 128 18>; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 clocks = <&cpg CPG_MOD 908>; 370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 371 resets = <&cpg 908>; 372 }; 373 374 gpio5: gpio@e6055000 { 375 compatible = "renesas,gpio-r8a774e1", 376 "renesas,rcar-gen3-gpio"; 377 reg = <0 0xe6055000 0 0x50>; 378 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 379 #gpio-cells = <2>; 380 gpio-controller; 381 gpio-ranges = <&pfc 0 160 26>; 382 #interrupt-cells = <2>; 383 interrupt-controller; 384 clocks = <&cpg CPG_MOD 907>; 385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 386 resets = <&cpg 907>; 387 }; 388 389 gpio6: gpio@e6055400 { 390 compatible = "renesas,gpio-r8a774e1", 391 "renesas,rcar-gen3-gpio"; 392 reg = <0 0xe6055400 0 0x50>; 393 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 394 #gpio-cells = <2>; 395 gpio-controller; 396 gpio-ranges = <&pfc 0 192 32>; 397 #interrupt-cells = <2>; 398 interrupt-controller; 399 clocks = <&cpg CPG_MOD 906>; 400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 401 resets = <&cpg 906>; 402 }; 403 404 gpio7: gpio@e6055800 { 405 compatible = "renesas,gpio-r8a774e1", 406 "renesas,rcar-gen3-gpio"; 407 reg = <0 0xe6055800 0 0x50>; 408 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 409 #gpio-cells = <2>; 410 gpio-controller; 411 gpio-ranges = <&pfc 0 224 4>; 412 #interrupt-cells = <2>; 413 interrupt-controller; 414 clocks = <&cpg CPG_MOD 905>; 415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 416 resets = <&cpg 905>; 417 }; 418 419 pfc: pin-controller@e6060000 { 420 compatible = "renesas,pfc-r8a774e1"; 421 reg = <0 0xe6060000 0 0x50c>; 422 }; 423 424 cpg: clock-controller@e6150000 { 425 compatible = "renesas,r8a774e1-cpg-mssr"; 426 reg = <0 0xe6150000 0 0x1000>; 427 clocks = <&extal_clk>, <&extalr_clk>; 428 clock-names = "extal", "extalr"; 429 #clock-cells = <2>; 430 #power-domain-cells = <0>; 431 #reset-cells = <1>; 432 }; 433 434 rst: reset-controller@e6160000 { 435 compatible = "renesas,r8a774e1-rst"; 436 reg = <0 0xe6160000 0 0x0200>; 437 }; 438 439 sysc: system-controller@e6180000 { 440 compatible = "renesas,r8a774e1-sysc"; 441 reg = <0 0xe6180000 0 0x0400>; 442 #power-domain-cells = <1>; 443 }; 444 445 intc_ex: interrupt-controller@e61c0000 { 446 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 447 #interrupt-cells = <2>; 448 interrupt-controller; 449 reg = <0 0xe61c0000 0 0x200>; 450 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 407>; 457 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 458 resets = <&cpg 407>; 459 }; 460 461 i2c2: i2c@e6510000 { 462 reg = <0 0xe6510000 0 0x40>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 467 /* placeholder */ 468 }; 469 470 i2c4: i2c@e66d8000 { 471 #address-cells = <1>; 472 #size-cells = <0>; 473 reg = <0 0xe66d8000 0 0x40>; 474 status = "disabled"; 475 476 /* placeholder */ 477 }; 478 479 hscif0: serial@e6540000 { 480 reg = <0 0xe6540000 0 0x60>; 481 status = "disabled"; 482 483 /* placeholder */ 484 }; 485 486 hsusb: usb@e6590000 { 487 reg = <0 0xe6590000 0 0x200>; 488 status = "disabled"; 489 490 /* placeholder */ 491 }; 492 493 usb3_phy0: usb-phy@e65ee000 { 494 reg = <0 0xe65ee000 0 0x90>; 495 #phy-cells = <0>; 496 status = "disabled"; 497 498 /* placeholder */ 499 }; 500 501 dmac0: dma-controller@e6700000 { 502 compatible = "renesas,dmac-r8a774e1", 503 "renesas,rcar-dmac"; 504 reg = <0 0xe6700000 0 0x10000>; 505 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "error", 523 "ch0", "ch1", "ch2", "ch3", 524 "ch4", "ch5", "ch6", "ch7", 525 "ch8", "ch9", "ch10", "ch11", 526 "ch12", "ch13", "ch14", "ch15"; 527 clocks = <&cpg CPG_MOD 219>; 528 clock-names = "fck"; 529 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 530 resets = <&cpg 219>; 531 #dma-cells = <1>; 532 dma-channels = <16>; 533 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 534 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 535 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 536 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 537 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 538 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 539 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 540 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 541 }; 542 543 dmac1: dma-controller@e7300000 { 544 compatible = "renesas,dmac-r8a774e1", 545 "renesas,rcar-dmac"; 546 reg = <0 0xe7300000 0 0x10000>; 547 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "error", 565 "ch0", "ch1", "ch2", "ch3", 566 "ch4", "ch5", "ch6", "ch7", 567 "ch8", "ch9", "ch10", "ch11", 568 "ch12", "ch13", "ch14", "ch15"; 569 clocks = <&cpg CPG_MOD 218>; 570 clock-names = "fck"; 571 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 572 resets = <&cpg 218>; 573 #dma-cells = <1>; 574 dma-channels = <16>; 575 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 576 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 577 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 578 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 579 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 580 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 581 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 582 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 583 }; 584 585 dmac2: dma-controller@e7310000 { 586 compatible = "renesas,dmac-r8a774e1", 587 "renesas,rcar-dmac"; 588 reg = <0 0xe7310000 0 0x10000>; 589 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 606 interrupt-names = "error", 607 "ch0", "ch1", "ch2", "ch3", 608 "ch4", "ch5", "ch6", "ch7", 609 "ch8", "ch9", "ch10", "ch11", 610 "ch12", "ch13", "ch14", "ch15"; 611 clocks = <&cpg CPG_MOD 217>; 612 clock-names = "fck"; 613 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 614 resets = <&cpg 217>; 615 #dma-cells = <1>; 616 dma-channels = <16>; 617 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 618 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 619 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 620 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 621 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 622 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 623 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 624 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 625 }; 626 627 ipmmu_ds0: iommu@e6740000 { 628 compatible = "renesas,ipmmu-r8a774e1"; 629 reg = <0 0xe6740000 0 0x1000>; 630 renesas,ipmmu-main = <&ipmmu_mm 0>; 631 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 632 #iommu-cells = <1>; 633 }; 634 635 ipmmu_ds1: iommu@e7740000 { 636 compatible = "renesas,ipmmu-r8a774e1"; 637 reg = <0 0xe7740000 0 0x1000>; 638 renesas,ipmmu-main = <&ipmmu_mm 1>; 639 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 640 #iommu-cells = <1>; 641 }; 642 643 ipmmu_hc: iommu@e6570000 { 644 compatible = "renesas,ipmmu-r8a774e1"; 645 reg = <0 0xe6570000 0 0x1000>; 646 renesas,ipmmu-main = <&ipmmu_mm 2>; 647 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 648 #iommu-cells = <1>; 649 }; 650 651 ipmmu_mm: iommu@e67b0000 { 652 compatible = "renesas,ipmmu-r8a774e1"; 653 reg = <0 0xe67b0000 0 0x1000>; 654 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 656 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 657 #iommu-cells = <1>; 658 }; 659 660 ipmmu_mp0: iommu@ec670000 { 661 compatible = "renesas,ipmmu-r8a774e1"; 662 reg = <0 0xec670000 0 0x1000>; 663 renesas,ipmmu-main = <&ipmmu_mm 4>; 664 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 665 #iommu-cells = <1>; 666 }; 667 668 ipmmu_pv0: iommu@fd800000 { 669 compatible = "renesas,ipmmu-r8a774e1"; 670 reg = <0 0xfd800000 0 0x1000>; 671 renesas,ipmmu-main = <&ipmmu_mm 6>; 672 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 673 #iommu-cells = <1>; 674 }; 675 676 ipmmu_pv1: iommu@fd950000 { 677 compatible = "renesas,ipmmu-r8a774e1"; 678 reg = <0 0xfd950000 0 0x1000>; 679 renesas,ipmmu-main = <&ipmmu_mm 7>; 680 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 681 #iommu-cells = <1>; 682 }; 683 684 ipmmu_pv2: iommu@fd960000 { 685 compatible = "renesas,ipmmu-r8a774e1"; 686 reg = <0 0xfd960000 0 0x1000>; 687 renesas,ipmmu-main = <&ipmmu_mm 8>; 688 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 689 #iommu-cells = <1>; 690 }; 691 692 ipmmu_pv3: iommu@fd970000 { 693 compatible = "renesas,ipmmu-r8a774e1"; 694 reg = <0 0xfd970000 0 0x1000>; 695 renesas,ipmmu-main = <&ipmmu_mm 9>; 696 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 697 #iommu-cells = <1>; 698 }; 699 700 ipmmu_vc0: iommu@fe6b0000 { 701 compatible = "renesas,ipmmu-r8a774e1"; 702 reg = <0 0xfe6b0000 0 0x1000>; 703 renesas,ipmmu-main = <&ipmmu_mm 12>; 704 power-domains = <&sysc R8A774E1_PD_A3VC>; 705 #iommu-cells = <1>; 706 }; 707 708 ipmmu_vc1: iommu@fe6f0000 { 709 compatible = "renesas,ipmmu-r8a774e1"; 710 reg = <0 0xfe6f0000 0 0x1000>; 711 renesas,ipmmu-main = <&ipmmu_mm 13>; 712 power-domains = <&sysc R8A774E1_PD_A3VC>; 713 #iommu-cells = <1>; 714 }; 715 716 ipmmu_vi0: iommu@febd0000 { 717 compatible = "renesas,ipmmu-r8a774e1"; 718 reg = <0 0xfebd0000 0 0x1000>; 719 renesas,ipmmu-main = <&ipmmu_mm 14>; 720 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 721 #iommu-cells = <1>; 722 }; 723 724 ipmmu_vi1: iommu@febe0000 { 725 compatible = "renesas,ipmmu-r8a774e1"; 726 reg = <0 0xfebe0000 0 0x1000>; 727 renesas,ipmmu-main = <&ipmmu_mm 15>; 728 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 729 #iommu-cells = <1>; 730 }; 731 732 ipmmu_vp0: iommu@fe990000 { 733 compatible = "renesas,ipmmu-r8a774e1"; 734 reg = <0 0xfe990000 0 0x1000>; 735 renesas,ipmmu-main = <&ipmmu_mm 16>; 736 power-domains = <&sysc R8A774E1_PD_A3VP>; 737 #iommu-cells = <1>; 738 }; 739 740 ipmmu_vp1: iommu@fe980000 { 741 compatible = "renesas,ipmmu-r8a774e1"; 742 reg = <0 0xfe980000 0 0x1000>; 743 renesas,ipmmu-main = <&ipmmu_mm 17>; 744 power-domains = <&sysc R8A774E1_PD_A3VP>; 745 #iommu-cells = <1>; 746 }; 747 748 avb: ethernet@e6800000 { 749 compatible = "renesas,etheravb-r8a774e1", 750 "renesas,etheravb-rcar-gen3"; 751 reg = <0 0xe6800000 0 0x800>; 752 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "ch0", "ch1", "ch2", "ch3", 778 "ch4", "ch5", "ch6", "ch7", 779 "ch8", "ch9", "ch10", "ch11", 780 "ch12", "ch13", "ch14", "ch15", 781 "ch16", "ch17", "ch18", "ch19", 782 "ch20", "ch21", "ch22", "ch23", 783 "ch24"; 784 clocks = <&cpg CPG_MOD 812>; 785 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 786 resets = <&cpg 812>; 787 phy-mode = "rgmii"; 788 iommus = <&ipmmu_ds0 16>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 can0: can@e6c30000 { 795 reg = <0 0xe6c30000 0 0x1000>; 796 status = "disabled"; 797 798 /* placeholder */ 799 }; 800 801 can1: can@e6c38000 { 802 reg = <0 0xe6c38000 0 0x1000>; 803 status = "disabled"; 804 805 /* placeholder */ 806 }; 807 808 pwm0: pwm@e6e30000 { 809 reg = <0 0xe6e30000 0 0x8>; 810 #pwm-cells = <2>; 811 status = "disabled"; 812 813 /* placeholder */ 814 }; 815 816 scif2: serial@e6e88000 { 817 compatible = "renesas,scif-r8a774e1", 818 "renesas,rcar-gen3-scif", "renesas,scif"; 819 reg = <0 0xe6e88000 0 0x40>; 820 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&cpg CPG_MOD 310>, 822 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 823 <&scif_clk>; 824 clock-names = "fck", "brg_int", "scif_clk"; 825 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 826 resets = <&cpg 310>; 827 status = "disabled"; 828 }; 829 830 rcar_sound: sound@ec500000 { 831 reg = <0 0xec500000 0 0x1000>, /* SCU */ 832 <0 0xec5a0000 0 0x100>, /* ADG */ 833 <0 0xec540000 0 0x1000>, /* SSIU */ 834 <0 0xec541000 0 0x280>, /* SSI */ 835 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 836 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 837 838 status = "disabled"; 839 840 /* placeholder */ 841 842 rcar_sound,ssi { 843 ssi2: ssi-2 { 844 /* placeholder */ 845 }; 846 }; 847 }; 848 849 xhci0: usb@ee000000 { 850 reg = <0 0xee000000 0 0xc00>; 851 status = "disabled"; 852 853 /* placeholder */ 854 }; 855 856 usb3_peri0: usb@ee020000 { 857 reg = <0 0xee020000 0 0x400>; 858 status = "disabled"; 859 860 /* placeholder */ 861 }; 862 863 ohci0: usb@ee080000 { 864 reg = <0 0xee080000 0 0x100>; 865 status = "disabled"; 866 867 /* placeholder */ 868 }; 869 870 ohci1: usb@ee0a0000 { 871 reg = <0 0xee0a0000 0 0x100>; 872 status = "disabled"; 873 874 /* placeholder */ 875 }; 876 877 ehci0: usb@ee080100 { 878 reg = <0 0xee080100 0 0x100>; 879 status = "disabled"; 880 881 /* placeholder */ 882 }; 883 884 ehci1: usb@ee0a0100 { 885 reg = <0 0xee0a0100 0 0x100>; 886 status = "disabled"; 887 888 /* placeholder */ 889 }; 890 891 usb2_phy0: usb-phy@ee080200 { 892 reg = <0 0xee080200 0 0x700>; 893 status = "disabled"; 894 895 /* placeholder */ 896 }; 897 898 usb2_phy1: usb-phy@ee0a0200 { 899 reg = <0 0xee0a0200 0 0x700>; 900 status = "disabled"; 901 902 /* placeholder */ 903 }; 904 905 sdhi0: mmc@ee100000 { 906 reg = <0 0xee100000 0 0x2000>; 907 status = "disabled"; 908 909 /* placeholder */ 910 }; 911 912 sdhi2: mmc@ee140000 { 913 reg = <0 0xee140000 0 0x2000>; 914 status = "disabled"; 915 916 /* placeholder */ 917 }; 918 919 sdhi3: mmc@ee160000 { 920 compatible = "renesas,sdhi-r8a774e1", 921 "renesas,rcar-gen3-sdhi"; 922 reg = <0 0xee160000 0 0x2000>; 923 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cpg CPG_MOD 311>; 925 max-frequency = <200000000>; 926 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 927 resets = <&cpg 311>; 928 status = "disabled"; 929 }; 930 931 gic: interrupt-controller@f1010000 { 932 compatible = "arm,gic-400"; 933 #interrupt-cells = <3>; 934 #address-cells = <0>; 935 interrupt-controller; 936 reg = <0x0 0xf1010000 0 0x1000>, 937 <0x0 0xf1020000 0 0x20000>, 938 <0x0 0xf1040000 0 0x20000>, 939 <0x0 0xf1060000 0 0x20000>; 940 interrupts = <GIC_PPI 9 941 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 942 clocks = <&cpg CPG_MOD 408>; 943 clock-names = "clk"; 944 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 945 resets = <&cpg 408>; 946 }; 947 948 pciec0: pcie@fe000000 { 949 reg = <0 0xfe000000 0 0x80000>; 950 #address-cells = <3>; 951 #size-cells = <2>; 952 status = "disabled"; 953 954 /* placeholder */ 955 }; 956 957 hdmi0: hdmi@fead0000 { 958 reg = <0 0xfead0000 0 0x10000>; 959 status = "disabled"; 960 961 /* placeholder */ 962 963 ports { 964 #address-cells = <1>; 965 #size-cells = <0>; 966 967 port@0 { 968 reg = <0>; 969 }; 970 port@1 { 971 reg = <1>; 972 }; 973 port@2 { 974 reg = <2>; 975 }; 976 }; 977 }; 978 979 du: display@feb00000 { 980 reg = <0 0xfeb00000 0 0x80000>; 981 status = "disabled"; 982 983 /* placeholder */ 984 ports { 985 #address-cells = <1>; 986 #size-cells = <0>; 987 988 port@0 { 989 reg = <0>; 990 }; 991 port@1 { 992 reg = <1>; 993 }; 994 port@2 { 995 reg = <2>; 996 }; 997 }; 998 }; 999 1000 prr: chipid@fff00044 { 1001 compatible = "renesas,prr"; 1002 reg = <0 0xfff00044 0 4>; 1003 }; 1004 }; 1005 1006 timer { 1007 compatible = "arm,armv8-timer"; 1008 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1009 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1010 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1011 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1012 }; 1013 1014 /* External USB clocks - can be overridden by the board */ 1015 usb3s0_clk: usb3s0 { 1016 compatible = "fixed-clock"; 1017 #clock-cells = <0>; 1018 clock-frequency = <0>; 1019 }; 1020 1021 usb_extal_clk: usb_extal { 1022 compatible = "fixed-clock"; 1023 #clock-cells = <0>; 1024 clock-frequency = <0>; 1025 }; 1026}; 1027