r8a774a1.dtsi (e2f04248fcd47bdc037b4bfe7864ebd0a807e30c) r8a774a1.dtsi (282419526ad7ba3d0ff5e53c20a5f4f5a273197f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1380 interrupts = <GIC_PPI 9
1381 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1382 clocks = <&cpg CPG_MOD 408>;
1383 clock-names = "clk";
1384 power-domains = <&sysc 32>;
1385 resets = <&cpg 408>;
1386 };
1387
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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1380 interrupts = <GIC_PPI 9
1381 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
1382 clocks = <&cpg CPG_MOD 408>;
1383 clock-names = "clk";
1384 power-domains = <&sysc 32>;
1385 resets = <&cpg 408>;
1386 };
1387
1388 fcpf0: fcp@fe950000 {
1389 compatible = "renesas,fcpf";
1390 reg = <0 0xfe950000 0 0x200>;
1391 clocks = <&cpg CPG_MOD 615>;
1392 power-domains = <&sysc 14>;
1393 resets = <&cpg 615>;
1394 };
1395
1396 fcpvb0: fcp@fe96f000 {
1397 compatible = "renesas,fcpv";
1398 reg = <0 0xfe96f000 0 0x200>;
1399 clocks = <&cpg CPG_MOD 607>;
1400 power-domains = <&sysc 14>;
1401 resets = <&cpg 607>;
1402 };
1403
1404 fcpvd0: fcp@fea27000 {
1405 compatible = "renesas,fcpv";
1406 reg = <0 0xfea27000 0 0x200>;
1407 clocks = <&cpg CPG_MOD 603>;
1408 power-domains = <&sysc 32>;
1409 resets = <&cpg 603>;
1410 iommus = <&ipmmu_vi0 8>;
1411 };
1412
1413 fcpvd1: fcp@fea2f000 {
1414 compatible = "renesas,fcpv";
1415 reg = <0 0xfea2f000 0 0x200>;
1416 clocks = <&cpg CPG_MOD 602>;
1417 power-domains = <&sysc 32>;
1418 resets = <&cpg 602>;
1419 iommus = <&ipmmu_vi0 9>;
1420 };
1421
1422 fcpvd2: fcp@fea37000 {
1423 compatible = "renesas,fcpv";
1424 reg = <0 0xfea37000 0 0x200>;
1425 clocks = <&cpg CPG_MOD 601>;
1426 power-domains = <&sysc 32>;
1427 resets = <&cpg 601>;
1428 iommus = <&ipmmu_vi0 10>;
1429 };
1430
1431 fcpvi0: fcp@fe9af000 {
1432 compatible = "renesas,fcpv";
1433 reg = <0 0xfe9af000 0 0x200>;
1434 clocks = <&cpg CPG_MOD 611>;
1435 power-domains = <&sysc 14>;
1436 resets = <&cpg 611>;
1437 iommus = <&ipmmu_vc0 19>;
1438 };
1439
1388 prr: chipid@fff00044 {
1389 compatible = "renesas,prr";
1390 reg = <0 0xfff00044 0 4>;
1391 };
1392 };
1393
1394 thermal-zones {
1395 sensor_thermal1: sensor-thermal1 {

--- 64 unchanged lines hidden --- 		1440 prr: chipid@fff00044 {
1441 compatible = "renesas,prr";
1442 reg = <0 0xfff00044 0 4>;
1443 };
1444 };
1445
1446 thermal-zones {
1447 sensor_thermal1: sensor-thermal1 {

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