1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 i2c7 = &i2c_dvfs; 26 }; 27 28 /* 29 * The external audio clocks are configured as 0 Hz fixed frequency 30 * clocks by default. 31 * Boards that provide audio clocks should override them. 32 */ 33 audio_clk_a: audio_clk_a { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 37 }; 38 39 audio_clk_b: audio_clk_b { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <0>; 43 }; 44 45 audio_clk_c: audio_clk_c { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <0>; 49 }; 50 51 /* External CAN clock - to be overridden by boards that provide it */ 52 can_clk: can { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 56 }; 57 58 cpus { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 a57_0: cpu@0 { 63 compatible = "arm,cortex-a57", "arm,armv8"; 64 reg = <0x0>; 65 device_type = "cpu"; 66 power-domains = <&sysc 0>; 67 next-level-cache = <&L2_CA57>; 68 enable-method = "psci"; 69 clocks =<&cpg CPG_CORE 0>; 70 }; 71 72 a57_1: cpu@1 { 73 compatible = "arm,cortex-a57", "arm,armv8"; 74 reg = <0x1>; 75 device_type = "cpu"; 76 power-domains = <&sysc 1>; 77 next-level-cache = <&L2_CA57>; 78 enable-method = "psci"; 79 clocks =<&cpg CPG_CORE 0>; 80 }; 81 82 a53_0: cpu@100 { 83 compatible = "arm,cortex-a53", "arm,armv8"; 84 reg = <0x100>; 85 device_type = "cpu"; 86 power-domains = <&sysc 5>; 87 next-level-cache = <&L2_CA53>; 88 enable-method = "psci"; 89 clocks =<&cpg CPG_CORE 1>; 90 }; 91 92 a53_1: cpu@101 { 93 compatible = "arm,cortex-a53", "arm,armv8"; 94 reg = <0x101>; 95 device_type = "cpu"; 96 power-domains = <&sysc 6>; 97 next-level-cache = <&L2_CA53>; 98 enable-method = "psci"; 99 clocks =<&cpg CPG_CORE 1>; 100 }; 101 102 a53_2: cpu@102 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 reg = <0x102>; 105 device_type = "cpu"; 106 power-domains = <&sysc 7>; 107 next-level-cache = <&L2_CA53>; 108 enable-method = "psci"; 109 clocks =<&cpg CPG_CORE 1>; 110 }; 111 112 a53_3: cpu@103 { 113 compatible = "arm,cortex-a53", "arm,armv8"; 114 reg = <0x103>; 115 device_type = "cpu"; 116 power-domains = <&sysc 8>; 117 next-level-cache = <&L2_CA53>; 118 enable-method = "psci"; 119 clocks =<&cpg CPG_CORE 1>; 120 }; 121 122 L2_CA57: cache-controller-0 { 123 compatible = "cache"; 124 power-domains = <&sysc 12>; 125 cache-unified; 126 cache-level = <2>; 127 }; 128 129 L2_CA53: cache-controller-1 { 130 compatible = "cache"; 131 power-domains = <&sysc 21>; 132 cache-unified; 133 cache-level = <2>; 134 }; 135 }; 136 137 extal_clk: extal { 138 compatible = "fixed-clock"; 139 #clock-cells = <0>; 140 /* This value must be overridden by the board */ 141 clock-frequency = <0>; 142 }; 143 144 extalr_clk: extalr { 145 compatible = "fixed-clock"; 146 #clock-cells = <0>; 147 /* This value must be overridden by the board */ 148 clock-frequency = <0>; 149 }; 150 151 /* External PCIe clock - can be overridden by the board */ 152 pcie_bus_clk: pcie_bus { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <0>; 156 }; 157 158 pmu_a53 { 159 compatible = "arm,cortex-a53-pmu"; 160 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 161 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 162 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 163 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 165 }; 166 167 pmu_a57 { 168 compatible = "arm,cortex-a57-pmu"; 169 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 170 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-affinity = <&a57_0>, <&a57_1>; 172 }; 173 174 psci { 175 compatible = "arm,psci-1.0", "arm,psci-0.2"; 176 method = "smc"; 177 }; 178 179 /* External SCIF clock - to be overridden by boards that provide it */ 180 scif_clk: scif { 181 compatible = "fixed-clock"; 182 #clock-cells = <0>; 183 clock-frequency = <0>; 184 }; 185 186 soc { 187 compatible = "simple-bus"; 188 interrupt-parent = <&gic>; 189 #address-cells = <2>; 190 #size-cells = <2>; 191 ranges; 192 193 rwdt: watchdog@e6020000 { 194 compatible = "renesas,r8a774a1-wdt", 195 "renesas,rcar-gen3-wdt"; 196 reg = <0 0xe6020000 0 0x0c>; 197 clocks = <&cpg CPG_MOD 402>; 198 power-domains = <&sysc 32>; 199 resets = <&cpg 402>; 200 status = "disabled"; 201 }; 202 203 gpio0: gpio@e6050000 { 204 compatible = "renesas,gpio-r8a774a1", 205 "renesas,rcar-gen3-gpio"; 206 reg = <0 0xe6050000 0 0x50>; 207 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 208 #gpio-cells = <2>; 209 gpio-controller; 210 gpio-ranges = <&pfc 0 0 16>; 211 #interrupt-cells = <2>; 212 interrupt-controller; 213 clocks = <&cpg CPG_MOD 912>; 214 power-domains = <&sysc 32>; 215 resets = <&cpg 912>; 216 }; 217 218 gpio1: gpio@e6051000 { 219 compatible = "renesas,gpio-r8a774a1", 220 "renesas,rcar-gen3-gpio"; 221 reg = <0 0xe6051000 0 0x50>; 222 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 223 #gpio-cells = <2>; 224 gpio-controller; 225 gpio-ranges = <&pfc 0 32 29>; 226 #interrupt-cells = <2>; 227 interrupt-controller; 228 clocks = <&cpg CPG_MOD 911>; 229 power-domains = <&sysc 32>; 230 resets = <&cpg 911>; 231 }; 232 233 gpio2: gpio@e6052000 { 234 compatible = "renesas,gpio-r8a774a1", 235 "renesas,rcar-gen3-gpio"; 236 reg = <0 0xe6052000 0 0x50>; 237 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 238 #gpio-cells = <2>; 239 gpio-controller; 240 gpio-ranges = <&pfc 0 64 15>; 241 #interrupt-cells = <2>; 242 interrupt-controller; 243 clocks = <&cpg CPG_MOD 910>; 244 power-domains = <&sysc 32>; 245 resets = <&cpg 910>; 246 }; 247 248 gpio3: gpio@e6053000 { 249 compatible = "renesas,gpio-r8a774a1", 250 "renesas,rcar-gen3-gpio"; 251 reg = <0 0xe6053000 0 0x50>; 252 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 253 #gpio-cells = <2>; 254 gpio-controller; 255 gpio-ranges = <&pfc 0 96 16>; 256 #interrupt-cells = <2>; 257 interrupt-controller; 258 clocks = <&cpg CPG_MOD 909>; 259 power-domains = <&sysc 32>; 260 resets = <&cpg 909>; 261 }; 262 263 gpio4: gpio@e6054000 { 264 compatible = "renesas,gpio-r8a774a1", 265 "renesas,rcar-gen3-gpio"; 266 reg = <0 0xe6054000 0 0x50>; 267 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 268 #gpio-cells = <2>; 269 gpio-controller; 270 gpio-ranges = <&pfc 0 128 18>; 271 #interrupt-cells = <2>; 272 interrupt-controller; 273 clocks = <&cpg CPG_MOD 908>; 274 power-domains = <&sysc 32>; 275 resets = <&cpg 908>; 276 }; 277 278 gpio5: gpio@e6055000 { 279 compatible = "renesas,gpio-r8a774a1", 280 "renesas,rcar-gen3-gpio"; 281 reg = <0 0xe6055000 0 0x50>; 282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 283 #gpio-cells = <2>; 284 gpio-controller; 285 gpio-ranges = <&pfc 0 160 26>; 286 #interrupt-cells = <2>; 287 interrupt-controller; 288 clocks = <&cpg CPG_MOD 907>; 289 power-domains = <&sysc 32>; 290 resets = <&cpg 907>; 291 }; 292 293 gpio6: gpio@e6055400 { 294 compatible = "renesas,gpio-r8a774a1", 295 "renesas,rcar-gen3-gpio"; 296 reg = <0 0xe6055400 0 0x50>; 297 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 298 #gpio-cells = <2>; 299 gpio-controller; 300 gpio-ranges = <&pfc 0 192 32>; 301 #interrupt-cells = <2>; 302 interrupt-controller; 303 clocks = <&cpg CPG_MOD 906>; 304 power-domains = <&sysc 32>; 305 resets = <&cpg 906>; 306 }; 307 308 gpio7: gpio@e6055800 { 309 compatible = "renesas,gpio-r8a774a1", 310 "renesas,rcar-gen3-gpio"; 311 reg = <0 0xe6055800 0 0x50>; 312 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 313 #gpio-cells = <2>; 314 gpio-controller; 315 gpio-ranges = <&pfc 0 224 4>; 316 #interrupt-cells = <2>; 317 interrupt-controller; 318 clocks = <&cpg CPG_MOD 905>; 319 power-domains = <&sysc 32>; 320 resets = <&cpg 905>; 321 }; 322 323 pfc: pin-controller@e6060000 { 324 compatible = "renesas,pfc-r8a774a1"; 325 reg = <0 0xe6060000 0 0x50c>; 326 }; 327 328 cpg: clock-controller@e6150000 { 329 compatible = "renesas,r8a774a1-cpg-mssr"; 330 reg = <0 0xe6150000 0 0x0bb0>; 331 clocks = <&extal_clk>, <&extalr_clk>; 332 clock-names = "extal", "extalr"; 333 #clock-cells = <2>; 334 #power-domain-cells = <0>; 335 #reset-cells = <1>; 336 }; 337 338 rst: reset-controller@e6160000 { 339 compatible = "renesas,r8a774a1-rst"; 340 reg = <0 0xe6160000 0 0x018c>; 341 }; 342 343 sysc: system-controller@e6180000 { 344 compatible = "renesas,r8a774a1-sysc"; 345 reg = <0 0xe6180000 0 0x0400>; 346 #power-domain-cells = <1>; 347 }; 348 349 tsc: thermal@e6198000 { 350 compatible = "renesas,r8a774a1-thermal"; 351 reg = <0 0xe6198000 0 0x100>, 352 <0 0xe61a0000 0 0x100>, 353 <0 0xe61a8000 0 0x100>; 354 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&cpg CPG_MOD 522>; 358 power-domains = <&sysc 32>; 359 resets = <&cpg 522>; 360 #thermal-sensor-cells = <1>; 361 status = "okay"; 362 }; 363 364 intc_ex: interrupt-controller@e61c0000 { 365 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 366 #interrupt-cells = <2>; 367 interrupt-controller; 368 reg = <0 0xe61c0000 0 0x200>; 369 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 407>; 376 power-domains = <&sysc 32>; 377 resets = <&cpg 407>; 378 }; 379 380 i2c0: i2c@e6500000 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 compatible = "renesas,i2c-r8a774a1", 384 "renesas,rcar-gen3-i2c"; 385 reg = <0 0xe6500000 0 0x40>; 386 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 931>; 388 power-domains = <&sysc 32>; 389 resets = <&cpg 931>; 390 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 391 <&dmac2 0x91>, <&dmac2 0x90>; 392 dma-names = "tx", "rx", "tx", "rx"; 393 i2c-scl-internal-delay-ns = <110>; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@e6508000 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 compatible = "renesas,i2c-r8a774a1", 401 "renesas,rcar-gen3-i2c"; 402 reg = <0 0xe6508000 0 0x40>; 403 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cpg CPG_MOD 930>; 405 power-domains = <&sysc 32>; 406 resets = <&cpg 930>; 407 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 408 <&dmac2 0x93>, <&dmac2 0x92>; 409 dma-names = "tx", "rx", "tx", "rx"; 410 i2c-scl-internal-delay-ns = <6>; 411 status = "disabled"; 412 }; 413 414 i2c2: i2c@e6510000 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 compatible = "renesas,i2c-r8a774a1", 418 "renesas,rcar-gen3-i2c"; 419 reg = <0 0xe6510000 0 0x40>; 420 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 929>; 422 power-domains = <&sysc 32>; 423 resets = <&cpg 929>; 424 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 425 <&dmac2 0x95>, <&dmac2 0x94>; 426 dma-names = "tx", "rx", "tx", "rx"; 427 i2c-scl-internal-delay-ns = <6>; 428 status = "disabled"; 429 }; 430 431 i2c3: i2c@e66d0000 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 compatible = "renesas,i2c-r8a774a1", 435 "renesas,rcar-gen3-i2c"; 436 reg = <0 0xe66d0000 0 0x40>; 437 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 928>; 439 power-domains = <&sysc 32>; 440 resets = <&cpg 928>; 441 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 442 dma-names = "tx", "rx"; 443 i2c-scl-internal-delay-ns = <110>; 444 status = "disabled"; 445 }; 446 447 i2c4: i2c@e66d8000 { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 compatible = "renesas,i2c-r8a774a1", 451 "renesas,rcar-gen3-i2c"; 452 reg = <0 0xe66d8000 0 0x40>; 453 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cpg CPG_MOD 927>; 455 power-domains = <&sysc 32>; 456 resets = <&cpg 927>; 457 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 458 dma-names = "tx", "rx"; 459 i2c-scl-internal-delay-ns = <110>; 460 status = "disabled"; 461 }; 462 463 i2c5: i2c@e66e0000 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 compatible = "renesas,i2c-r8a774a1", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe66e0000 0 0x40>; 469 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 919>; 471 power-domains = <&sysc 32>; 472 resets = <&cpg 919>; 473 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 474 dma-names = "tx", "rx"; 475 i2c-scl-internal-delay-ns = <110>; 476 status = "disabled"; 477 }; 478 479 i2c6: i2c@e66e8000 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "renesas,i2c-r8a774a1", 483 "renesas,rcar-gen3-i2c"; 484 reg = <0 0xe66e8000 0 0x40>; 485 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cpg CPG_MOD 918>; 487 power-domains = <&sysc 32>; 488 resets = <&cpg 918>; 489 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 490 dma-names = "tx", "rx"; 491 i2c-scl-internal-delay-ns = <6>; 492 status = "disabled"; 493 }; 494 495 i2c_dvfs: i2c@e60b0000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "renesas,iic-r8a774a1", 499 "renesas,rcar-gen3-iic", 500 "renesas,rmobile-iic"; 501 reg = <0 0xe60b0000 0 0x425>; 502 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD 926>; 504 power-domains = <&sysc 32>; 505 resets = <&cpg 926>; 506 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 507 dma-names = "tx", "rx"; 508 status = "disabled"; 509 }; 510 511 hscif0: serial@e6540000 { 512 compatible = "renesas,hscif-r8a774a1", 513 "renesas,rcar-gen3-hscif", 514 "renesas,hscif"; 515 reg = <0 0xe6540000 0 0x60>; 516 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cpg CPG_MOD 520>, 518 <&cpg CPG_CORE 19>, 519 <&scif_clk>; 520 clock-names = "fck", "brg_int", "scif_clk"; 521 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 522 <&dmac2 0x31>, <&dmac2 0x30>; 523 dma-names = "tx", "rx", "tx", "rx"; 524 power-domains = <&sysc 32>; 525 resets = <&cpg 520>; 526 status = "disabled"; 527 }; 528 529 hscif1: serial@e6550000 { 530 compatible = "renesas,hscif-r8a774a1", 531 "renesas,rcar-gen3-hscif", 532 "renesas,hscif"; 533 reg = <0 0xe6550000 0 0x60>; 534 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cpg CPG_MOD 519>, 536 <&cpg CPG_CORE 19>, 537 <&scif_clk>; 538 clock-names = "fck", "brg_int", "scif_clk"; 539 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 540 <&dmac2 0x33>, <&dmac2 0x32>; 541 dma-names = "tx", "rx", "tx", "rx"; 542 power-domains = <&sysc 32>; 543 resets = <&cpg 519>; 544 status = "disabled"; 545 }; 546 547 hscif2: serial@e6560000 { 548 compatible = "renesas,hscif-r8a774a1", 549 "renesas,rcar-gen3-hscif", 550 "renesas,hscif"; 551 reg = <0 0xe6560000 0 0x60>; 552 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&cpg CPG_MOD 518>, 554 <&cpg CPG_CORE 19>, 555 <&scif_clk>; 556 clock-names = "fck", "brg_int", "scif_clk"; 557 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 558 <&dmac2 0x35>, <&dmac2 0x34>; 559 dma-names = "tx", "rx", "tx", "rx"; 560 power-domains = <&sysc 32>; 561 resets = <&cpg 518>; 562 status = "disabled"; 563 }; 564 565 hscif3: serial@e66a0000 { 566 compatible = "renesas,hscif-r8a774a1", 567 "renesas,rcar-gen3-hscif", 568 "renesas,hscif"; 569 reg = <0 0xe66a0000 0 0x60>; 570 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&cpg CPG_MOD 517>, 572 <&cpg CPG_CORE 19>, 573 <&scif_clk>; 574 clock-names = "fck", "brg_int", "scif_clk"; 575 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 576 dma-names = "tx", "rx"; 577 power-domains = <&sysc 32>; 578 resets = <&cpg 517>; 579 status = "disabled"; 580 }; 581 582 hscif4: serial@e66b0000 { 583 compatible = "renesas,hscif-r8a774a1", 584 "renesas,rcar-gen3-hscif", 585 "renesas,hscif"; 586 reg = <0 0xe66b0000 0 0x60>; 587 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 516>, 589 <&cpg CPG_CORE 19>, 590 <&scif_clk>; 591 clock-names = "fck", "brg_int", "scif_clk"; 592 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 593 dma-names = "tx", "rx"; 594 power-domains = <&sysc 32>; 595 resets = <&cpg 516>; 596 status = "disabled"; 597 }; 598 599 dmac0: dma-controller@e6700000 { 600 compatible = "renesas,dmac-r8a774a1", 601 "renesas,rcar-dmac"; 602 reg = <0 0xe6700000 0 0x10000>; 603 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 604 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 605 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 606 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 607 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 608 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 609 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 610 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 611 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 612 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 613 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 614 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 615 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 616 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 617 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 618 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 619 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 620 interrupt-names = "error", 621 "ch0", "ch1", "ch2", "ch3", 622 "ch4", "ch5", "ch6", "ch7", 623 "ch8", "ch9", "ch10", "ch11", 624 "ch12", "ch13", "ch14", "ch15"; 625 clocks = <&cpg CPG_MOD 219>; 626 clock-names = "fck"; 627 power-domains = <&sysc 32>; 628 resets = <&cpg 219>; 629 #dma-cells = <1>; 630 dma-channels = <16>; 631 }; 632 633 dmac1: dma-controller@e7300000 { 634 compatible = "renesas,dmac-r8a774a1", 635 "renesas,rcar-dmac"; 636 reg = <0 0xe7300000 0 0x10000>; 637 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 638 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 639 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 640 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 641 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 642 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 643 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 644 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 645 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 646 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 647 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 648 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 649 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 650 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 651 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 652 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 653 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "error", 655 "ch0", "ch1", "ch2", "ch3", 656 "ch4", "ch5", "ch6", "ch7", 657 "ch8", "ch9", "ch10", "ch11", 658 "ch12", "ch13", "ch14", "ch15"; 659 clocks = <&cpg CPG_MOD 218>; 660 clock-names = "fck"; 661 power-domains = <&sysc 32>; 662 resets = <&cpg 218>; 663 #dma-cells = <1>; 664 dma-channels = <16>; 665 }; 666 667 dmac2: dma-controller@e7310000 { 668 compatible = "renesas,dmac-r8a774a1", 669 "renesas,rcar-dmac"; 670 reg = <0 0xe7310000 0 0x10000>; 671 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 672 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 673 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 674 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 675 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 676 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 677 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 678 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 679 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 680 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 681 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 682 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 683 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 684 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 685 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 686 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 687 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "error", 689 "ch0", "ch1", "ch2", "ch3", 690 "ch4", "ch5", "ch6", "ch7", 691 "ch8", "ch9", "ch10", "ch11", 692 "ch12", "ch13", "ch14", "ch15"; 693 clocks = <&cpg CPG_MOD 217>; 694 clock-names = "fck"; 695 power-domains = <&sysc 32>; 696 resets = <&cpg 217>; 697 #dma-cells = <1>; 698 dma-channels = <16>; 699 }; 700 701 ipmmu_ds0: mmu@e6740000 { 702 compatible = "renesas,ipmmu-r8a774a1"; 703 reg = <0 0xe6740000 0 0x1000>; 704 renesas,ipmmu-main = <&ipmmu_mm 0>; 705 power-domains = <&sysc 32>; 706 #iommu-cells = <1>; 707 }; 708 709 ipmmu_ds1: mmu@e7740000 { 710 compatible = "renesas,ipmmu-r8a774a1"; 711 reg = <0 0xe7740000 0 0x1000>; 712 renesas,ipmmu-main = <&ipmmu_mm 1>; 713 power-domains = <&sysc 32>; 714 #iommu-cells = <1>; 715 }; 716 717 ipmmu_hc: mmu@e6570000 { 718 compatible = "renesas,ipmmu-r8a774a1"; 719 reg = <0 0xe6570000 0 0x1000>; 720 renesas,ipmmu-main = <&ipmmu_mm 2>; 721 power-domains = <&sysc 32>; 722 #iommu-cells = <1>; 723 }; 724 725 ipmmu_mm: mmu@e67b0000 { 726 compatible = "renesas,ipmmu-r8a774a1"; 727 reg = <0 0xe67b0000 0 0x1000>; 728 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 730 power-domains = <&sysc 32>; 731 #iommu-cells = <1>; 732 }; 733 734 ipmmu_mp: mmu@ec670000 { 735 compatible = "renesas,ipmmu-r8a774a1"; 736 reg = <0 0xec670000 0 0x1000>; 737 renesas,ipmmu-main = <&ipmmu_mm 4>; 738 power-domains = <&sysc 32>; 739 #iommu-cells = <1>; 740 }; 741 742 ipmmu_pv0: mmu@fd800000 { 743 compatible = "renesas,ipmmu-r8a774a1"; 744 reg = <0 0xfd800000 0 0x1000>; 745 renesas,ipmmu-main = <&ipmmu_mm 5>; 746 power-domains = <&sysc 32>; 747 #iommu-cells = <1>; 748 }; 749 750 ipmmu_pv1: mmu@fd950000 { 751 compatible = "renesas,ipmmu-r8a774a1"; 752 reg = <0 0xfd950000 0 0x1000>; 753 renesas,ipmmu-main = <&ipmmu_mm 6>; 754 power-domains = <&sysc 32>; 755 #iommu-cells = <1>; 756 }; 757 758 ipmmu_vc0: mmu@fe6b0000 { 759 compatible = "renesas,ipmmu-r8a774a1"; 760 reg = <0 0xfe6b0000 0 0x1000>; 761 renesas,ipmmu-main = <&ipmmu_mm 8>; 762 power-domains = <&sysc 14>; 763 #iommu-cells = <1>; 764 }; 765 766 ipmmu_vi0: mmu@febd0000 { 767 compatible = "renesas,ipmmu-r8a774a1"; 768 reg = <0 0xfebd0000 0 0x1000>; 769 renesas,ipmmu-main = <&ipmmu_mm 9>; 770 power-domains = <&sysc 32>; 771 #iommu-cells = <1>; 772 }; 773 774 avb: ethernet@e6800000 { 775 compatible = "renesas,etheravb-r8a774a1", 776 "renesas,etheravb-rcar-gen3"; 777 reg = <0 0xe6800000 0 0x800>; 778 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-names = "ch0", "ch1", "ch2", "ch3", 804 "ch4", "ch5", "ch6", "ch7", 805 "ch8", "ch9", "ch10", "ch11", 806 "ch12", "ch13", "ch14", "ch15", 807 "ch16", "ch17", "ch18", "ch19", 808 "ch20", "ch21", "ch22", "ch23", 809 "ch24"; 810 clocks = <&cpg CPG_MOD 812>; 811 power-domains = <&sysc 32>; 812 resets = <&cpg 812>; 813 phy-mode = "rgmii"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 pwm0: pwm@e6e30000 { 820 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 821 reg = <0 0xe6e30000 0 0x8>; 822 #pwm-cells = <2>; 823 clocks = <&cpg CPG_MOD 523>; 824 resets = <&cpg 523>; 825 power-domains = <&sysc 32>; 826 status = "disabled"; 827 }; 828 829 pwm1: pwm@e6e31000 { 830 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 831 reg = <0 0xe6e31000 0 0x8>; 832 #pwm-cells = <2>; 833 clocks = <&cpg CPG_MOD 523>; 834 resets = <&cpg 523>; 835 power-domains = <&sysc 32>; 836 status = "disabled"; 837 }; 838 839 pwm2: pwm@e6e32000 { 840 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 841 reg = <0 0xe6e32000 0 0x8>; 842 #pwm-cells = <2>; 843 clocks = <&cpg CPG_MOD 523>; 844 resets = <&cpg 523>; 845 power-domains = <&sysc 32>; 846 status = "disabled"; 847 }; 848 849 pwm3: pwm@e6e33000 { 850 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 851 reg = <0 0xe6e33000 0 0x8>; 852 #pwm-cells = <2>; 853 clocks = <&cpg CPG_MOD 523>; 854 resets = <&cpg 523>; 855 power-domains = <&sysc 32>; 856 status = "disabled"; 857 }; 858 859 pwm4: pwm@e6e34000 { 860 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 861 reg = <0 0xe6e34000 0 0x8>; 862 #pwm-cells = <2>; 863 clocks = <&cpg CPG_MOD 523>; 864 resets = <&cpg 523>; 865 power-domains = <&sysc 32>; 866 status = "disabled"; 867 }; 868 869 pwm5: pwm@e6e35000 { 870 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 871 reg = <0 0xe6e35000 0 0x8>; 872 #pwm-cells = <2>; 873 clocks = <&cpg CPG_MOD 523>; 874 resets = <&cpg 523>; 875 power-domains = <&sysc 32>; 876 status = "disabled"; 877 }; 878 879 pwm6: pwm@e6e36000 { 880 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 881 reg = <0 0xe6e36000 0 0x8>; 882 #pwm-cells = <2>; 883 clocks = <&cpg CPG_MOD 523>; 884 resets = <&cpg 523>; 885 power-domains = <&sysc 32>; 886 status = "disabled"; 887 }; 888 889 scif0: serial@e6e60000 { 890 compatible = "renesas,scif-r8a774a1", 891 "renesas,rcar-gen3-scif", "renesas,scif"; 892 reg = <0 0xe6e60000 0 0x40>; 893 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&cpg CPG_MOD 207>, 895 <&cpg CPG_CORE 19>, 896 <&scif_clk>; 897 clock-names = "fck", "brg_int", "scif_clk"; 898 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 899 <&dmac2 0x51>, <&dmac2 0x50>; 900 dma-names = "tx", "rx", "tx", "rx"; 901 power-domains = <&sysc 32>; 902 resets = <&cpg 207>; 903 status = "disabled"; 904 }; 905 906 scif1: serial@e6e68000 { 907 compatible = "renesas,scif-r8a774a1", 908 "renesas,rcar-gen3-scif", "renesas,scif"; 909 reg = <0 0xe6e68000 0 0x40>; 910 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&cpg CPG_MOD 206>, 912 <&cpg CPG_CORE 19>, 913 <&scif_clk>; 914 clock-names = "fck", "brg_int", "scif_clk"; 915 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 916 <&dmac2 0x53>, <&dmac2 0x52>; 917 dma-names = "tx", "rx", "tx", "rx"; 918 power-domains = <&sysc 32>; 919 resets = <&cpg 206>; 920 status = "disabled"; 921 }; 922 923 scif2: serial@e6e88000 { 924 compatible = "renesas,scif-r8a774a1", 925 "renesas,rcar-gen3-scif", "renesas,scif"; 926 reg = <0 0xe6e88000 0 0x40>; 927 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&cpg CPG_MOD 310>, 929 <&cpg CPG_CORE 19>, 930 <&scif_clk>; 931 clock-names = "fck", "brg_int", "scif_clk"; 932 power-domains = <&sysc 32>; 933 resets = <&cpg 310>; 934 status = "disabled"; 935 }; 936 937 scif3: serial@e6c50000 { 938 compatible = "renesas,scif-r8a774a1", 939 "renesas,rcar-gen3-scif", "renesas,scif"; 940 reg = <0 0xe6c50000 0 0x40>; 941 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&cpg CPG_MOD 204>, 943 <&cpg CPG_CORE 19>, 944 <&scif_clk>; 945 clock-names = "fck", "brg_int", "scif_clk"; 946 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 947 dma-names = "tx", "rx"; 948 power-domains = <&sysc 32>; 949 resets = <&cpg 204>; 950 status = "disabled"; 951 }; 952 953 scif4: serial@e6c40000 { 954 compatible = "renesas,scif-r8a774a1", 955 "renesas,rcar-gen3-scif", "renesas,scif"; 956 reg = <0 0xe6c40000 0 0x40>; 957 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&cpg CPG_MOD 203>, 959 <&cpg CPG_CORE 19>, 960 <&scif_clk>; 961 clock-names = "fck", "brg_int", "scif_clk"; 962 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 963 dma-names = "tx", "rx"; 964 power-domains = <&sysc 32>; 965 resets = <&cpg 203>; 966 status = "disabled"; 967 }; 968 969 scif5: serial@e6f30000 { 970 compatible = "renesas,scif-r8a774a1", 971 "renesas,rcar-gen3-scif", "renesas,scif"; 972 reg = <0 0xe6f30000 0 0x40>; 973 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cpg CPG_MOD 202>, 975 <&cpg CPG_CORE 19>, 976 <&scif_clk>; 977 clock-names = "fck", "brg_int", "scif_clk"; 978 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 979 <&dmac2 0x5b>, <&dmac2 0x5a>; 980 dma-names = "tx", "rx", "tx", "rx"; 981 power-domains = <&sysc 32>; 982 resets = <&cpg 202>; 983 status = "disabled"; 984 }; 985 986 msiof0: spi@e6e90000 { 987 compatible = "renesas,msiof-r8a774a1", 988 "renesas,rcar-gen3-msiof"; 989 reg = <0 0xe6e90000 0 0x0064>; 990 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cpg CPG_MOD 211>; 992 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 993 <&dmac2 0x41>, <&dmac2 0x40>; 994 dma-names = "tx", "rx", "tx", "rx"; 995 power-domains = <&sysc 32>; 996 resets = <&cpg 211>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 msiof1: spi@e6ea0000 { 1003 compatible = "renesas,msiof-r8a774a1", 1004 "renesas,rcar-gen3-msiof"; 1005 reg = <0 0xe6ea0000 0 0x0064>; 1006 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&cpg CPG_MOD 210>; 1008 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1009 <&dmac2 0x43>, <&dmac2 0x42>; 1010 dma-names = "tx", "rx", "tx", "rx"; 1011 power-domains = <&sysc 32>; 1012 resets = <&cpg 210>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 msiof2: spi@e6c00000 { 1019 compatible = "renesas,msiof-r8a774a1", 1020 "renesas,rcar-gen3-msiof"; 1021 reg = <0 0xe6c00000 0 0x0064>; 1022 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 209>; 1024 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1025 dma-names = "tx", "rx"; 1026 power-domains = <&sysc 32>; 1027 resets = <&cpg 209>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 status = "disabled"; 1031 }; 1032 1033 msiof3: spi@e6c10000 { 1034 compatible = "renesas,msiof-r8a774a1", 1035 "renesas,rcar-gen3-msiof"; 1036 reg = <0 0xe6c10000 0 0x0064>; 1037 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cpg CPG_MOD 208>; 1039 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1040 dma-names = "tx", "rx"; 1041 power-domains = <&sysc 32>; 1042 resets = <&cpg 208>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 rcar_sound: sound@ec500000 { 1049 /* 1050 * #sound-dai-cells is required 1051 * 1052 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1053 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1054 */ 1055 /* 1056 * #clock-cells is required for audio_clkout0/1/2/3 1057 * 1058 * clkout : #clock-cells = <0>; <&rcar_sound>; 1059 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1060 */ 1061 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1062 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1063 <0 0xec5a0000 0 0x100>, /* ADG */ 1064 <0 0xec540000 0 0x1000>, /* SSIU */ 1065 <0 0xec541000 0 0x280>, /* SSI */ 1066 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1067 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1068 1069 clocks = <&cpg CPG_MOD 1005>, 1070 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1071 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1072 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1073 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1074 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1075 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1076 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1077 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1078 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1079 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1080 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1081 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1082 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1083 <&audio_clk_a>, <&audio_clk_b>, 1084 <&audio_clk_c>, 1085 <&cpg CPG_CORE 10>; 1086 clock-names = "ssi-all", 1087 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1088 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1089 "ssi.1", "ssi.0", 1090 "src.9", "src.8", "src.7", "src.6", 1091 "src.5", "src.4", "src.3", "src.2", 1092 "src.1", "src.0", 1093 "mix.1", "mix.0", 1094 "ctu.1", "ctu.0", 1095 "dvc.0", "dvc.1", 1096 "clk_a", "clk_b", "clk_c", "clk_i"; 1097 power-domains = <&sysc 32>; 1098 resets = <&cpg 1005>, 1099 <&cpg 1006>, <&cpg 1007>, 1100 <&cpg 1008>, <&cpg 1009>, 1101 <&cpg 1010>, <&cpg 1011>, 1102 <&cpg 1012>, <&cpg 1013>, 1103 <&cpg 1014>, <&cpg 1015>; 1104 reset-names = "ssi-all", 1105 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1106 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1107 "ssi.1", "ssi.0"; 1108 status = "disabled"; 1109 1110 rcar_sound,dvc { 1111 dvc0: dvc-0 { 1112 dmas = <&audma1 0xbc>; 1113 dma-names = "tx"; 1114 }; 1115 dvc1: dvc-1 { 1116 dmas = <&audma1 0xbe>; 1117 dma-names = "tx"; 1118 }; 1119 }; 1120 1121 rcar_sound,mix { 1122 mix0: mix-0 { }; 1123 mix1: mix-1 { }; 1124 }; 1125 1126 rcar_sound,ctu { 1127 ctu00: ctu-0 { }; 1128 ctu01: ctu-1 { }; 1129 ctu02: ctu-2 { }; 1130 ctu03: ctu-3 { }; 1131 ctu10: ctu-4 { }; 1132 ctu11: ctu-5 { }; 1133 ctu12: ctu-6 { }; 1134 ctu13: ctu-7 { }; 1135 }; 1136 1137 rcar_sound,src { 1138 src0: src-0 { 1139 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1140 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1141 dma-names = "rx", "tx"; 1142 }; 1143 src1: src-1 { 1144 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1145 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1146 dma-names = "rx", "tx"; 1147 }; 1148 src2: src-2 { 1149 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1150 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1151 dma-names = "rx", "tx"; 1152 }; 1153 src3: src-3 { 1154 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1155 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1156 dma-names = "rx", "tx"; 1157 }; 1158 src4: src-4 { 1159 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1160 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1161 dma-names = "rx", "tx"; 1162 }; 1163 src5: src-5 { 1164 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1166 dma-names = "rx", "tx"; 1167 }; 1168 src6: src-6 { 1169 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1170 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1171 dma-names = "rx", "tx"; 1172 }; 1173 src7: src-7 { 1174 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1175 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1176 dma-names = "rx", "tx"; 1177 }; 1178 src8: src-8 { 1179 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1180 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1181 dma-names = "rx", "tx"; 1182 }; 1183 src9: src-9 { 1184 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1185 dmas = <&audma0 0x97>, <&audma1 0xba>; 1186 dma-names = "rx", "tx"; 1187 }; 1188 }; 1189 1190 rcar_sound,ssi { 1191 ssi0: ssi-0 { 1192 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1193 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1194 dma-names = "rx", "tx", "rxu", "txu"; 1195 }; 1196 ssi1: ssi-1 { 1197 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1198 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1199 dma-names = "rx", "tx", "rxu", "txu"; 1200 }; 1201 ssi2: ssi-2 { 1202 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1203 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1204 dma-names = "rx", "tx", "rxu", "txu"; 1205 }; 1206 ssi3: ssi-3 { 1207 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1208 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1209 dma-names = "rx", "tx", "rxu", "txu"; 1210 }; 1211 ssi4: ssi-4 { 1212 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1213 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1214 dma-names = "rx", "tx", "rxu", "txu"; 1215 }; 1216 ssi5: ssi-5 { 1217 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1218 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1219 dma-names = "rx", "tx", "rxu", "txu"; 1220 }; 1221 ssi6: ssi-6 { 1222 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1223 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1224 dma-names = "rx", "tx", "rxu", "txu"; 1225 }; 1226 ssi7: ssi-7 { 1227 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1228 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1229 dma-names = "rx", "tx", "rxu", "txu"; 1230 }; 1231 ssi8: ssi-8 { 1232 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1233 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1234 dma-names = "rx", "tx", "rxu", "txu"; 1235 }; 1236 ssi9: ssi-9 { 1237 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1238 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1239 dma-names = "rx", "tx", "rxu", "txu"; 1240 }; 1241 }; 1242 1243 ports { 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 port@0 { 1247 reg = <0>; 1248 }; 1249 port@1 { 1250 reg = <1>; 1251 }; 1252 }; 1253 }; 1254 1255 audma0: dma-controller@ec700000 { 1256 compatible = "renesas,dmac-r8a774a1", 1257 "renesas,rcar-dmac"; 1258 reg = <0 0xec700000 0 0x10000>; 1259 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1260 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1261 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1262 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1263 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1264 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1265 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1266 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1267 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1268 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1269 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1270 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1271 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1272 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1273 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1274 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1275 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1276 interrupt-names = "error", 1277 "ch0", "ch1", "ch2", "ch3", 1278 "ch4", "ch5", "ch6", "ch7", 1279 "ch8", "ch9", "ch10", "ch11", 1280 "ch12", "ch13", "ch14", "ch15"; 1281 clocks = <&cpg CPG_MOD 502>; 1282 clock-names = "fck"; 1283 power-domains = <&sysc 32>; 1284 resets = <&cpg 502>; 1285 #dma-cells = <1>; 1286 dma-channels = <16>; 1287 }; 1288 1289 audma1: dma-controller@ec720000 { 1290 compatible = "renesas,dmac-r8a774a1", 1291 "renesas,rcar-dmac"; 1292 reg = <0 0xec720000 0 0x10000>; 1293 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1294 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1295 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1296 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1297 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1298 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1299 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1300 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1301 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1302 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1303 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1304 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1305 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1306 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1307 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1308 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1309 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-names = "error", 1311 "ch0", "ch1", "ch2", "ch3", 1312 "ch4", "ch5", "ch6", "ch7", 1313 "ch8", "ch9", "ch10", "ch11", 1314 "ch12", "ch13", "ch14", "ch15"; 1315 clocks = <&cpg CPG_MOD 501>; 1316 clock-names = "fck"; 1317 power-domains = <&sysc 32>; 1318 resets = <&cpg 501>; 1319 #dma-cells = <1>; 1320 dma-channels = <16>; 1321 }; 1322 1323 sdhi0: sd@ee100000 { 1324 compatible = "renesas,sdhi-r8a774a1", 1325 "renesas,rcar-gen3-sdhi"; 1326 reg = <0 0xee100000 0 0x2000>; 1327 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1328 clocks = <&cpg CPG_MOD 314>; 1329 max-frequency = <200000000>; 1330 power-domains = <&sysc 32>; 1331 resets = <&cpg 314>; 1332 status = "disabled"; 1333 }; 1334 1335 sdhi1: sd@ee120000 { 1336 compatible = "renesas,sdhi-r8a774a1", 1337 "renesas,rcar-gen3-sdhi"; 1338 reg = <0 0xee120000 0 0x2000>; 1339 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&cpg CPG_MOD 313>; 1341 max-frequency = <200000000>; 1342 power-domains = <&sysc 32>; 1343 resets = <&cpg 313>; 1344 status = "disabled"; 1345 }; 1346 1347 sdhi2: sd@ee140000 { 1348 compatible = "renesas,sdhi-r8a774a1", 1349 "renesas,rcar-gen3-sdhi"; 1350 reg = <0 0xee140000 0 0x2000>; 1351 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&cpg CPG_MOD 312>; 1353 max-frequency = <200000000>; 1354 power-domains = <&sysc 32>; 1355 resets = <&cpg 312>; 1356 status = "disabled"; 1357 }; 1358 1359 sdhi3: sd@ee160000 { 1360 compatible = "renesas,sdhi-r8a774a1", 1361 "renesas,rcar-gen3-sdhi"; 1362 reg = <0 0xee160000 0 0x2000>; 1363 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&cpg CPG_MOD 311>; 1365 max-frequency = <200000000>; 1366 power-domains = <&sysc 32>; 1367 resets = <&cpg 311>; 1368 status = "disabled"; 1369 }; 1370 1371 gic: interrupt-controller@f1010000 { 1372 compatible = "arm,gic-400"; 1373 #interrupt-cells = <3>; 1374 #address-cells = <0>; 1375 interrupt-controller; 1376 reg = <0x0 0xf1010000 0 0x1000>, 1377 <0x0 0xf1020000 0 0x20000>, 1378 <0x0 0xf1040000 0 0x20000>, 1379 <0x0 0xf1060000 0 0x20000>; 1380 interrupts = <GIC_PPI 9 1381 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1382 clocks = <&cpg CPG_MOD 408>; 1383 clock-names = "clk"; 1384 power-domains = <&sysc 32>; 1385 resets = <&cpg 408>; 1386 }; 1387 1388 fcpf0: fcp@fe950000 { 1389 compatible = "renesas,fcpf"; 1390 reg = <0 0xfe950000 0 0x200>; 1391 clocks = <&cpg CPG_MOD 615>; 1392 power-domains = <&sysc 14>; 1393 resets = <&cpg 615>; 1394 }; 1395 1396 fcpvb0: fcp@fe96f000 { 1397 compatible = "renesas,fcpv"; 1398 reg = <0 0xfe96f000 0 0x200>; 1399 clocks = <&cpg CPG_MOD 607>; 1400 power-domains = <&sysc 14>; 1401 resets = <&cpg 607>; 1402 }; 1403 1404 fcpvd0: fcp@fea27000 { 1405 compatible = "renesas,fcpv"; 1406 reg = <0 0xfea27000 0 0x200>; 1407 clocks = <&cpg CPG_MOD 603>; 1408 power-domains = <&sysc 32>; 1409 resets = <&cpg 603>; 1410 iommus = <&ipmmu_vi0 8>; 1411 }; 1412 1413 fcpvd1: fcp@fea2f000 { 1414 compatible = "renesas,fcpv"; 1415 reg = <0 0xfea2f000 0 0x200>; 1416 clocks = <&cpg CPG_MOD 602>; 1417 power-domains = <&sysc 32>; 1418 resets = <&cpg 602>; 1419 iommus = <&ipmmu_vi0 9>; 1420 }; 1421 1422 fcpvd2: fcp@fea37000 { 1423 compatible = "renesas,fcpv"; 1424 reg = <0 0xfea37000 0 0x200>; 1425 clocks = <&cpg CPG_MOD 601>; 1426 power-domains = <&sysc 32>; 1427 resets = <&cpg 601>; 1428 iommus = <&ipmmu_vi0 10>; 1429 }; 1430 1431 fcpvi0: fcp@fe9af000 { 1432 compatible = "renesas,fcpv"; 1433 reg = <0 0xfe9af000 0 0x200>; 1434 clocks = <&cpg CPG_MOD 611>; 1435 power-domains = <&sysc 14>; 1436 resets = <&cpg 611>; 1437 iommus = <&ipmmu_vc0 19>; 1438 }; 1439 1440 prr: chipid@fff00044 { 1441 compatible = "renesas,prr"; 1442 reg = <0 0xfff00044 0 4>; 1443 }; 1444 }; 1445 1446 thermal-zones { 1447 sensor_thermal1: sensor-thermal1 { 1448 polling-delay-passive = <250>; 1449 polling-delay = <1000>; 1450 thermal-sensors = <&tsc 0>; 1451 1452 trips { 1453 sensor1_crit: sensor1-crit { 1454 temperature = <120000>; 1455 hysteresis = <1000>; 1456 type = "critical"; 1457 }; 1458 }; 1459 }; 1460 1461 sensor_thermal2: sensor-thermal2 { 1462 polling-delay-passive = <250>; 1463 polling-delay = <1000>; 1464 thermal-sensors = <&tsc 1>; 1465 1466 trips { 1467 sensor2_crit: sensor2-crit { 1468 temperature = <120000>; 1469 hysteresis = <1000>; 1470 type = "critical"; 1471 }; 1472 }; 1473 1474 }; 1475 1476 sensor_thermal3: sensor-thermal3 { 1477 polling-delay-passive = <250>; 1478 polling-delay = <1000>; 1479 thermal-sensors = <&tsc 2>; 1480 1481 trips { 1482 sensor3_crit: sensor3-crit { 1483 temperature = <120000>; 1484 hysteresis = <1000>; 1485 type = "critical"; 1486 }; 1487 }; 1488 }; 1489 }; 1490 1491 timer { 1492 compatible = "arm,armv8-timer"; 1493 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 1494 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 1495 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 1496 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 1497 }; 1498 1499 /* External USB clocks - can be overridden by the board */ 1500 usb3s0_clk: usb3s0 { 1501 compatible = "fixed-clock"; 1502 #clock-cells = <0>; 1503 clock-frequency = <0>; 1504 }; 1505 1506 usb_extal_clk: usb_extal { 1507 compatible = "fixed-clock"; 1508 #clock-cells = <0>; 1509 clock-frequency = <0>; 1510 }; 1511}; 1512