r8a774a1.dtsi (a5a41d50ffe77d250655f767eb192dbbc387edd7) r8a774a1.dtsi (aa85b3cac7d87cb28f27c8bf8f1737290879ad57)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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369 resets = <&cpg 905>;
370 };
371
372 pfc: pin-controller@e6060000 {
373 compatible = "renesas,pfc-r8a774a1";
374 reg = <0 0xe6060000 0 0x50c>;
375 };
376
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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369 resets = <&cpg 905>;
370 };
371
372 pfc: pin-controller@e6060000 {
373 compatible = "renesas,pfc-r8a774a1";
374 reg = <0 0xe6060000 0 0x50c>;
375 };
376
377 cmt0: timer@e60f0000 {
378 compatible = "renesas,r8a774a1-cmt0",
379 "renesas,rcar-gen3-cmt0";
380 reg = <0 0xe60f0000 0 0x1004>;
381 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cpg CPG_MOD 303>;
384 clock-names = "fck";
385 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
386 resets = <&cpg 303>;
387 status = "disabled";
388 };
389
390 cmt1: timer@e6130000 {
391 compatible = "renesas,r8a774a1-cmt1",
392 "renesas,rcar-gen3-cmt1";
393 reg = <0 0xe6130000 0 0x1004>;
394 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cpg CPG_MOD 302>;
403 clock-names = "fck";
404 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
405 resets = <&cpg 302>;
406 status = "disabled";
407 };
408
409 cmt2: timer@e6140000 {
410 compatible = "renesas,r8a774a1-cmt1",
411 "renesas,rcar-gen3-cmt1";
412 reg = <0 0xe6140000 0 0x1004>;
413 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cpg CPG_MOD 301>;
422 clock-names = "fck";
423 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
424 resets = <&cpg 301>;
425 status = "disabled";
426 };
427
428 cmt3: timer@e6148000 {
429 compatible = "renesas,r8a774a1-cmt1",
430 "renesas,rcar-gen3-cmt1";
431 reg = <0 0xe6148000 0 0x1004>;
432 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cpg CPG_MOD 300>;
441 clock-names = "fck";
442 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
443 resets = <&cpg 300>;
444 status = "disabled";
445 };
446
377 cpg: clock-controller@e6150000 {
378 compatible = "renesas,r8a774a1-cpg-mssr";
379 reg = <0 0xe6150000 0 0x0bb0>;
380 clocks = <&extal_clk>, <&extalr_clk>;
381 clock-names = "extal", "extalr";
382 #clock-cells = <2>;
383 #power-domain-cells = <0>;
384 #reset-cells = <1>;

--- 1949 unchanged lines hidden --- 		447 cpg: clock-controller@e6150000 {
448 compatible = "renesas,r8a774a1-cpg-mssr";
449 reg = <0 0xe6150000 0 0x0bb0>;
450 clocks = <&extal_clk>, <&extalr_clk>;
451 clock-names = "extal", "extalr";
452 #clock-cells = <2>;
453 #power-domain-cells = <0>;
454 #reset-cells = <1>;

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