1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774a1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c_dvfs; 27 }; 28 29 /* 30 * The external audio clocks are configured as 0 Hz fixed frequency 31 * clocks by default. 32 * Boards that provide audio clocks should override them. 33 */ 34 audio_clk_a: audio_clk_a { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 audio_clk_b: audio_clk_b { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 }; 45 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock - to be overridden by boards that provide it */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 }; 58 59 cluster0_opp: opp_table0 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-500000000 { 64 opp-hz = /bits/ 64 <500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1500000000 { 74 opp-hz = /bits/ 64 <1500000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cluster1_opp: opp_table1 { 81 compatible = "operating-points-v2"; 82 opp-shared; 83 84 opp-800000000 { 85 opp-hz = /bits/ 64 <800000000>; 86 opp-microvolt = <820000>; 87 clock-latency-ns = <300000>; 88 }; 89 opp-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = <820000>; 92 clock-latency-ns = <300000>; 93 }; 94 opp-1200000000 { 95 opp-hz = /bits/ 64 <1200000000>; 96 opp-microvolt = <820000>; 97 clock-latency-ns = <300000>; 98 }; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 a57_0: cpu@0 { 106 compatible = "arm,cortex-a57"; 107 reg = <0x0>; 108 device_type = "cpu"; 109 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 110 next-level-cache = <&L2_CA57>; 111 enable-method = "psci"; 112 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 113 operating-points-v2 = <&cluster0_opp>; 114 }; 115 116 a57_1: cpu@1 { 117 compatible = "arm,cortex-a57"; 118 reg = <0x1>; 119 device_type = "cpu"; 120 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 121 next-level-cache = <&L2_CA57>; 122 enable-method = "psci"; 123 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 124 operating-points-v2 = <&cluster0_opp>; 125 }; 126 127 a53_0: cpu@100 { 128 compatible = "arm,cortex-a53"; 129 reg = <0x100>; 130 device_type = "cpu"; 131 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 132 next-level-cache = <&L2_CA53>; 133 enable-method = "psci"; 134 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 135 operating-points-v2 = <&cluster1_opp>; 136 }; 137 138 a53_1: cpu@101 { 139 compatible = "arm,cortex-a53"; 140 reg = <0x101>; 141 device_type = "cpu"; 142 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 143 next-level-cache = <&L2_CA53>; 144 enable-method = "psci"; 145 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 146 operating-points-v2 = <&cluster1_opp>; 147 }; 148 149 a53_2: cpu@102 { 150 compatible = "arm,cortex-a53"; 151 reg = <0x102>; 152 device_type = "cpu"; 153 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 154 next-level-cache = <&L2_CA53>; 155 enable-method = "psci"; 156 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 157 operating-points-v2 = <&cluster1_opp>; 158 }; 159 160 a53_3: cpu@103 { 161 compatible = "arm,cortex-a53"; 162 reg = <0x103>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 165 next-level-cache = <&L2_CA53>; 166 enable-method = "psci"; 167 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 168 operating-points-v2 = <&cluster1_opp>; 169 }; 170 171 L2_CA57: cache-controller-0 { 172 compatible = "cache"; 173 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 174 cache-unified; 175 cache-level = <2>; 176 }; 177 178 L2_CA53: cache-controller-1 { 179 compatible = "cache"; 180 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 181 cache-unified; 182 cache-level = <2>; 183 }; 184 }; 185 186 extal_clk: extal { 187 compatible = "fixed-clock"; 188 #clock-cells = <0>; 189 /* This value must be overridden by the board */ 190 clock-frequency = <0>; 191 }; 192 193 extalr_clk: extalr { 194 compatible = "fixed-clock"; 195 #clock-cells = <0>; 196 /* This value must be overridden by the board */ 197 clock-frequency = <0>; 198 }; 199 200 /* External PCIe clock - can be overridden by the board */ 201 pcie_bus_clk: pcie_bus { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <0>; 205 }; 206 207 pmu_a53 { 208 compatible = "arm,cortex-a53-pmu"; 209 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 210 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 211 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 212 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 214 }; 215 216 pmu_a57 { 217 compatible = "arm,cortex-a57-pmu"; 218 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 219 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-affinity = <&a57_0>, <&a57_1>; 221 }; 222 223 psci { 224 compatible = "arm,psci-1.0", "arm,psci-0.2"; 225 method = "smc"; 226 }; 227 228 /* External SCIF clock - to be overridden by boards that provide it */ 229 scif_clk: scif { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <0>; 233 }; 234 235 soc { 236 compatible = "simple-bus"; 237 interrupt-parent = <&gic>; 238 #address-cells = <2>; 239 #size-cells = <2>; 240 ranges; 241 242 rwdt: watchdog@e6020000 { 243 compatible = "renesas,r8a774a1-wdt", 244 "renesas,rcar-gen3-wdt"; 245 reg = <0 0xe6020000 0 0x0c>; 246 clocks = <&cpg CPG_MOD 402>; 247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 248 resets = <&cpg 402>; 249 status = "disabled"; 250 }; 251 252 gpio0: gpio@e6050000 { 253 compatible = "renesas,gpio-r8a774a1", 254 "renesas,rcar-gen3-gpio"; 255 reg = <0 0xe6050000 0 0x50>; 256 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 257 #gpio-cells = <2>; 258 gpio-controller; 259 gpio-ranges = <&pfc 0 0 16>; 260 #interrupt-cells = <2>; 261 interrupt-controller; 262 clocks = <&cpg CPG_MOD 912>; 263 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 264 resets = <&cpg 912>; 265 }; 266 267 gpio1: gpio@e6051000 { 268 compatible = "renesas,gpio-r8a774a1", 269 "renesas,rcar-gen3-gpio"; 270 reg = <0 0xe6051000 0 0x50>; 271 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 272 #gpio-cells = <2>; 273 gpio-controller; 274 gpio-ranges = <&pfc 0 32 29>; 275 #interrupt-cells = <2>; 276 interrupt-controller; 277 clocks = <&cpg CPG_MOD 911>; 278 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 279 resets = <&cpg 911>; 280 }; 281 282 gpio2: gpio@e6052000 { 283 compatible = "renesas,gpio-r8a774a1", 284 "renesas,rcar-gen3-gpio"; 285 reg = <0 0xe6052000 0 0x50>; 286 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 287 #gpio-cells = <2>; 288 gpio-controller; 289 gpio-ranges = <&pfc 0 64 15>; 290 #interrupt-cells = <2>; 291 interrupt-controller; 292 clocks = <&cpg CPG_MOD 910>; 293 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 294 resets = <&cpg 910>; 295 }; 296 297 gpio3: gpio@e6053000 { 298 compatible = "renesas,gpio-r8a774a1", 299 "renesas,rcar-gen3-gpio"; 300 reg = <0 0xe6053000 0 0x50>; 301 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 302 #gpio-cells = <2>; 303 gpio-controller; 304 gpio-ranges = <&pfc 0 96 16>; 305 #interrupt-cells = <2>; 306 interrupt-controller; 307 clocks = <&cpg CPG_MOD 909>; 308 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 309 resets = <&cpg 909>; 310 }; 311 312 gpio4: gpio@e6054000 { 313 compatible = "renesas,gpio-r8a774a1", 314 "renesas,rcar-gen3-gpio"; 315 reg = <0 0xe6054000 0 0x50>; 316 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 317 #gpio-cells = <2>; 318 gpio-controller; 319 gpio-ranges = <&pfc 0 128 18>; 320 #interrupt-cells = <2>; 321 interrupt-controller; 322 clocks = <&cpg CPG_MOD 908>; 323 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 324 resets = <&cpg 908>; 325 }; 326 327 gpio5: gpio@e6055000 { 328 compatible = "renesas,gpio-r8a774a1", 329 "renesas,rcar-gen3-gpio"; 330 reg = <0 0xe6055000 0 0x50>; 331 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 332 #gpio-cells = <2>; 333 gpio-controller; 334 gpio-ranges = <&pfc 0 160 26>; 335 #interrupt-cells = <2>; 336 interrupt-controller; 337 clocks = <&cpg CPG_MOD 907>; 338 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 339 resets = <&cpg 907>; 340 }; 341 342 gpio6: gpio@e6055400 { 343 compatible = "renesas,gpio-r8a774a1", 344 "renesas,rcar-gen3-gpio"; 345 reg = <0 0xe6055400 0 0x50>; 346 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 347 #gpio-cells = <2>; 348 gpio-controller; 349 gpio-ranges = <&pfc 0 192 32>; 350 #interrupt-cells = <2>; 351 interrupt-controller; 352 clocks = <&cpg CPG_MOD 906>; 353 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 354 resets = <&cpg 906>; 355 }; 356 357 gpio7: gpio@e6055800 { 358 compatible = "renesas,gpio-r8a774a1", 359 "renesas,rcar-gen3-gpio"; 360 reg = <0 0xe6055800 0 0x50>; 361 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 362 #gpio-cells = <2>; 363 gpio-controller; 364 gpio-ranges = <&pfc 0 224 4>; 365 #interrupt-cells = <2>; 366 interrupt-controller; 367 clocks = <&cpg CPG_MOD 905>; 368 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 369 resets = <&cpg 905>; 370 }; 371 372 pfc: pin-controller@e6060000 { 373 compatible = "renesas,pfc-r8a774a1"; 374 reg = <0 0xe6060000 0 0x50c>; 375 }; 376 377 cmt0: timer@e60f0000 { 378 compatible = "renesas,r8a774a1-cmt0", 379 "renesas,rcar-gen3-cmt0"; 380 reg = <0 0xe60f0000 0 0x1004>; 381 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cpg CPG_MOD 303>; 384 clock-names = "fck"; 385 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 386 resets = <&cpg 303>; 387 status = "disabled"; 388 }; 389 390 cmt1: timer@e6130000 { 391 compatible = "renesas,r8a774a1-cmt1", 392 "renesas,rcar-gen3-cmt1"; 393 reg = <0 0xe6130000 0 0x1004>; 394 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cpg CPG_MOD 302>; 403 clock-names = "fck"; 404 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 405 resets = <&cpg 302>; 406 status = "disabled"; 407 }; 408 409 cmt2: timer@e6140000 { 410 compatible = "renesas,r8a774a1-cmt1", 411 "renesas,rcar-gen3-cmt1"; 412 reg = <0 0xe6140000 0 0x1004>; 413 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 301>; 422 clock-names = "fck"; 423 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 424 resets = <&cpg 301>; 425 status = "disabled"; 426 }; 427 428 cmt3: timer@e6148000 { 429 compatible = "renesas,r8a774a1-cmt1", 430 "renesas,rcar-gen3-cmt1"; 431 reg = <0 0xe6148000 0 0x1004>; 432 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cpg CPG_MOD 300>; 441 clock-names = "fck"; 442 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 443 resets = <&cpg 300>; 444 status = "disabled"; 445 }; 446 447 cpg: clock-controller@e6150000 { 448 compatible = "renesas,r8a774a1-cpg-mssr"; 449 reg = <0 0xe6150000 0 0x0bb0>; 450 clocks = <&extal_clk>, <&extalr_clk>; 451 clock-names = "extal", "extalr"; 452 #clock-cells = <2>; 453 #power-domain-cells = <0>; 454 #reset-cells = <1>; 455 }; 456 457 rst: reset-controller@e6160000 { 458 compatible = "renesas,r8a774a1-rst"; 459 reg = <0 0xe6160000 0 0x018c>; 460 }; 461 462 sysc: system-controller@e6180000 { 463 compatible = "renesas,r8a774a1-sysc"; 464 reg = <0 0xe6180000 0 0x0400>; 465 #power-domain-cells = <1>; 466 }; 467 468 tsc: thermal@e6198000 { 469 compatible = "renesas,r8a774a1-thermal"; 470 reg = <0 0xe6198000 0 0x100>, 471 <0 0xe61a0000 0 0x100>, 472 <0 0xe61a8000 0 0x100>; 473 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cpg CPG_MOD 522>; 477 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 478 resets = <&cpg 522>; 479 #thermal-sensor-cells = <1>; 480 }; 481 482 intc_ex: interrupt-controller@e61c0000 { 483 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 484 #interrupt-cells = <2>; 485 interrupt-controller; 486 reg = <0 0xe61c0000 0 0x200>; 487 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 488 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 489 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 490 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 491 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 492 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&cpg CPG_MOD 407>; 494 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 495 resets = <&cpg 407>; 496 }; 497 498 i2c0: i2c@e6500000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "renesas,i2c-r8a774a1", 502 "renesas,rcar-gen3-i2c"; 503 reg = <0 0xe6500000 0 0x40>; 504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 931>; 506 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 507 resets = <&cpg 931>; 508 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 509 <&dmac2 0x91>, <&dmac2 0x90>; 510 dma-names = "tx", "rx", "tx", "rx"; 511 i2c-scl-internal-delay-ns = <110>; 512 status = "disabled"; 513 }; 514 515 i2c1: i2c@e6508000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "renesas,i2c-r8a774a1", 519 "renesas,rcar-gen3-i2c"; 520 reg = <0 0xe6508000 0 0x40>; 521 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 930>; 523 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 524 resets = <&cpg 930>; 525 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 526 <&dmac2 0x93>, <&dmac2 0x92>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 i2c-scl-internal-delay-ns = <6>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@e6510000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "renesas,i2c-r8a774a1", 536 "renesas,rcar-gen3-i2c"; 537 reg = <0 0xe6510000 0 0x40>; 538 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 929>; 540 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 541 resets = <&cpg 929>; 542 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 543 <&dmac2 0x95>, <&dmac2 0x94>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 i2c-scl-internal-delay-ns = <6>; 546 status = "disabled"; 547 }; 548 549 i2c3: i2c@e66d0000 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 compatible = "renesas,i2c-r8a774a1", 553 "renesas,rcar-gen3-i2c"; 554 reg = <0 0xe66d0000 0 0x40>; 555 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 928>; 557 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 558 resets = <&cpg 928>; 559 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 560 dma-names = "tx", "rx"; 561 i2c-scl-internal-delay-ns = <110>; 562 status = "disabled"; 563 }; 564 565 i2c4: i2c@e66d8000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "renesas,i2c-r8a774a1", 569 "renesas,rcar-gen3-i2c"; 570 reg = <0 0xe66d8000 0 0x40>; 571 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 927>; 573 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 574 resets = <&cpg 927>; 575 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 576 dma-names = "tx", "rx"; 577 i2c-scl-internal-delay-ns = <110>; 578 status = "disabled"; 579 }; 580 581 i2c5: i2c@e66e0000 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "renesas,i2c-r8a774a1", 585 "renesas,rcar-gen3-i2c"; 586 reg = <0 0xe66e0000 0 0x40>; 587 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 919>; 589 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 590 resets = <&cpg 919>; 591 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 592 dma-names = "tx", "rx"; 593 i2c-scl-internal-delay-ns = <110>; 594 status = "disabled"; 595 }; 596 597 i2c6: i2c@e66e8000 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 compatible = "renesas,i2c-r8a774a1", 601 "renesas,rcar-gen3-i2c"; 602 reg = <0 0xe66e8000 0 0x40>; 603 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 918>; 605 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 606 resets = <&cpg 918>; 607 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 608 dma-names = "tx", "rx"; 609 i2c-scl-internal-delay-ns = <6>; 610 status = "disabled"; 611 }; 612 613 i2c_dvfs: i2c@e60b0000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "renesas,iic-r8a774a1", 617 "renesas,rcar-gen3-iic", 618 "renesas,rmobile-iic"; 619 reg = <0 0xe60b0000 0 0x425>; 620 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 926>; 622 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 623 resets = <&cpg 926>; 624 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 625 dma-names = "tx", "rx"; 626 status = "disabled"; 627 }; 628 629 hscif0: serial@e6540000 { 630 compatible = "renesas,hscif-r8a774a1", 631 "renesas,rcar-gen3-hscif", 632 "renesas,hscif"; 633 reg = <0 0xe6540000 0 0x60>; 634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 520>, 636 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 637 <&scif_clk>; 638 clock-names = "fck", "brg_int", "scif_clk"; 639 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 640 <&dmac2 0x31>, <&dmac2 0x30>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 643 resets = <&cpg 520>; 644 status = "disabled"; 645 }; 646 647 hscif1: serial@e6550000 { 648 compatible = "renesas,hscif-r8a774a1", 649 "renesas,rcar-gen3-hscif", 650 "renesas,hscif"; 651 reg = <0 0xe6550000 0 0x60>; 652 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 519>, 654 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 655 <&scif_clk>; 656 clock-names = "fck", "brg_int", "scif_clk"; 657 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 658 <&dmac2 0x33>, <&dmac2 0x32>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 661 resets = <&cpg 519>; 662 status = "disabled"; 663 }; 664 665 hscif2: serial@e6560000 { 666 compatible = "renesas,hscif-r8a774a1", 667 "renesas,rcar-gen3-hscif", 668 "renesas,hscif"; 669 reg = <0 0xe6560000 0 0x60>; 670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 518>, 672 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 676 <&dmac2 0x35>, <&dmac2 0x34>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 679 resets = <&cpg 518>; 680 status = "disabled"; 681 }; 682 683 hscif3: serial@e66a0000 { 684 compatible = "renesas,hscif-r8a774a1", 685 "renesas,rcar-gen3-hscif", 686 "renesas,hscif"; 687 reg = <0 0xe66a0000 0 0x60>; 688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cpg CPG_MOD 517>, 690 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 691 <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 694 dma-names = "tx", "rx"; 695 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 696 resets = <&cpg 517>; 697 status = "disabled"; 698 }; 699 700 hscif4: serial@e66b0000 { 701 compatible = "renesas,hscif-r8a774a1", 702 "renesas,rcar-gen3-hscif", 703 "renesas,hscif"; 704 reg = <0 0xe66b0000 0 0x60>; 705 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 516>, 707 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 708 <&scif_clk>; 709 clock-names = "fck", "brg_int", "scif_clk"; 710 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 711 dma-names = "tx", "rx"; 712 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 713 resets = <&cpg 516>; 714 status = "disabled"; 715 }; 716 717 hsusb: usb@e6590000 { 718 compatible = "renesas,usbhs-r8a774a1", 719 "renesas,rcar-gen3-usbhs"; 720 reg = <0 0xe6590000 0 0x200>; 721 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 704>; 723 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 724 <&usb_dmac1 0>, <&usb_dmac1 1>; 725 dma-names = "ch0", "ch1", "ch2", "ch3"; 726 renesas,buswait = <11>; 727 phys = <&usb2_phy0 3>; 728 phy-names = "usb"; 729 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 730 resets = <&cpg 704>; 731 status = "disabled"; 732 }; 733 734 usb_dmac0: dma-controller@e65a0000 { 735 compatible = "renesas,r8a774a1-usb-dmac", 736 "renesas,usb-dmac"; 737 reg = <0 0xe65a0000 0 0x100>; 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "ch0", "ch1"; 741 clocks = <&cpg CPG_MOD 330>; 742 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 743 resets = <&cpg 330>; 744 #dma-cells = <1>; 745 dma-channels = <2>; 746 }; 747 748 usb_dmac1: dma-controller@e65b0000 { 749 compatible = "renesas,r8a774a1-usb-dmac", 750 "renesas,usb-dmac"; 751 reg = <0 0xe65b0000 0 0x100>; 752 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 753 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0", "ch1"; 755 clocks = <&cpg CPG_MOD 331>; 756 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 757 resets = <&cpg 331>; 758 #dma-cells = <1>; 759 dma-channels = <2>; 760 }; 761 762 usb3_phy0: usb-phy@e65ee000 { 763 compatible = "renesas,r8a774a1-usb3-phy", 764 "renesas,rcar-gen3-usb3-phy"; 765 reg = <0 0xe65ee000 0 0x90>; 766 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 767 <&usb_extal_clk>; 768 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 769 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 770 resets = <&cpg 328>; 771 #phy-cells = <0>; 772 status = "disabled"; 773 }; 774 775 dmac0: dma-controller@e6700000 { 776 compatible = "renesas,dmac-r8a774a1", 777 "renesas,rcar-dmac"; 778 reg = <0 0xe6700000 0 0x10000>; 779 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 780 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 781 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 782 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 783 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 784 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 785 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 786 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 787 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 788 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 789 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 790 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 791 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 792 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 793 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 794 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 795 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 796 interrupt-names = "error", 797 "ch0", "ch1", "ch2", "ch3", 798 "ch4", "ch5", "ch6", "ch7", 799 "ch8", "ch9", "ch10", "ch11", 800 "ch12", "ch13", "ch14", "ch15"; 801 clocks = <&cpg CPG_MOD 219>; 802 clock-names = "fck"; 803 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 804 resets = <&cpg 219>; 805 #dma-cells = <1>; 806 dma-channels = <16>; 807 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 808 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 809 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 810 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 811 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 812 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 813 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 814 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 815 }; 816 817 dmac1: dma-controller@e7300000 { 818 compatible = "renesas,dmac-r8a774a1", 819 "renesas,rcar-dmac"; 820 reg = <0 0xe7300000 0 0x10000>; 821 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 822 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 823 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 824 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 825 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 826 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 827 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 828 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 829 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 830 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 831 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 832 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 833 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 834 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 835 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 836 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 837 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "error", 839 "ch0", "ch1", "ch2", "ch3", 840 "ch4", "ch5", "ch6", "ch7", 841 "ch8", "ch9", "ch10", "ch11", 842 "ch12", "ch13", "ch14", "ch15"; 843 clocks = <&cpg CPG_MOD 218>; 844 clock-names = "fck"; 845 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 846 resets = <&cpg 218>; 847 #dma-cells = <1>; 848 dma-channels = <16>; 849 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 850 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 851 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 852 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 853 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 854 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 855 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 856 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 857 }; 858 859 dmac2: dma-controller@e7310000 { 860 compatible = "renesas,dmac-r8a774a1", 861 "renesas,rcar-dmac"; 862 reg = <0 0xe7310000 0 0x10000>; 863 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 864 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 865 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 866 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 867 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 868 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 869 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 870 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 871 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 872 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 873 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 874 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 875 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 876 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 877 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 878 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 879 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "error", 881 "ch0", "ch1", "ch2", "ch3", 882 "ch4", "ch5", "ch6", "ch7", 883 "ch8", "ch9", "ch10", "ch11", 884 "ch12", "ch13", "ch14", "ch15"; 885 clocks = <&cpg CPG_MOD 217>; 886 clock-names = "fck"; 887 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 888 resets = <&cpg 217>; 889 #dma-cells = <1>; 890 dma-channels = <16>; 891 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 892 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 893 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 894 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 895 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 896 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 897 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 898 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 899 }; 900 901 ipmmu_ds0: mmu@e6740000 { 902 compatible = "renesas,ipmmu-r8a774a1"; 903 reg = <0 0xe6740000 0 0x1000>; 904 renesas,ipmmu-main = <&ipmmu_mm 0>; 905 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 906 #iommu-cells = <1>; 907 }; 908 909 ipmmu_ds1: mmu@e7740000 { 910 compatible = "renesas,ipmmu-r8a774a1"; 911 reg = <0 0xe7740000 0 0x1000>; 912 renesas,ipmmu-main = <&ipmmu_mm 1>; 913 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 914 #iommu-cells = <1>; 915 }; 916 917 ipmmu_hc: mmu@e6570000 { 918 compatible = "renesas,ipmmu-r8a774a1"; 919 reg = <0 0xe6570000 0 0x1000>; 920 renesas,ipmmu-main = <&ipmmu_mm 2>; 921 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 922 #iommu-cells = <1>; 923 }; 924 925 ipmmu_mm: mmu@e67b0000 { 926 compatible = "renesas,ipmmu-r8a774a1"; 927 reg = <0 0xe67b0000 0 0x1000>; 928 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 930 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 931 #iommu-cells = <1>; 932 }; 933 934 ipmmu_mp: mmu@ec670000 { 935 compatible = "renesas,ipmmu-r8a774a1"; 936 reg = <0 0xec670000 0 0x1000>; 937 renesas,ipmmu-main = <&ipmmu_mm 4>; 938 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 939 #iommu-cells = <1>; 940 }; 941 942 ipmmu_pv0: mmu@fd800000 { 943 compatible = "renesas,ipmmu-r8a774a1"; 944 reg = <0 0xfd800000 0 0x1000>; 945 renesas,ipmmu-main = <&ipmmu_mm 5>; 946 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 947 #iommu-cells = <1>; 948 }; 949 950 ipmmu_pv1: mmu@fd950000 { 951 compatible = "renesas,ipmmu-r8a774a1"; 952 reg = <0 0xfd950000 0 0x1000>; 953 renesas,ipmmu-main = <&ipmmu_mm 6>; 954 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 955 #iommu-cells = <1>; 956 }; 957 958 ipmmu_vc0: mmu@fe6b0000 { 959 compatible = "renesas,ipmmu-r8a774a1"; 960 reg = <0 0xfe6b0000 0 0x1000>; 961 renesas,ipmmu-main = <&ipmmu_mm 8>; 962 power-domains = <&sysc R8A774A1_PD_A3VC>; 963 #iommu-cells = <1>; 964 }; 965 966 ipmmu_vi0: mmu@febd0000 { 967 compatible = "renesas,ipmmu-r8a774a1"; 968 reg = <0 0xfebd0000 0 0x1000>; 969 renesas,ipmmu-main = <&ipmmu_mm 9>; 970 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 971 #iommu-cells = <1>; 972 }; 973 974 avb: ethernet@e6800000 { 975 compatible = "renesas,etheravb-r8a774a1", 976 "renesas,etheravb-rcar-gen3"; 977 reg = <0 0xe6800000 0 0x800>; 978 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1003 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1004 "ch4", "ch5", "ch6", "ch7", 1005 "ch8", "ch9", "ch10", "ch11", 1006 "ch12", "ch13", "ch14", "ch15", 1007 "ch16", "ch17", "ch18", "ch19", 1008 "ch20", "ch21", "ch22", "ch23", 1009 "ch24"; 1010 clocks = <&cpg CPG_MOD 812>; 1011 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1012 resets = <&cpg 812>; 1013 phy-mode = "rgmii"; 1014 iommus = <&ipmmu_ds0 16>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 can0: can@e6c30000 { 1021 compatible = "renesas,can-r8a774a1", 1022 "renesas,rcar-gen3-can"; 1023 reg = <0 0xe6c30000 0 0x1000>; 1024 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&cpg CPG_MOD 916>, 1026 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1027 <&can_clk>; 1028 clock-names = "clkp1", "clkp2", "can_clk"; 1029 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1030 resets = <&cpg 916>; 1031 status = "disabled"; 1032 }; 1033 1034 can1: can@e6c38000 { 1035 compatible = "renesas,can-r8a774a1", 1036 "renesas,rcar-gen3-can"; 1037 reg = <0 0xe6c38000 0 0x1000>; 1038 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cpg CPG_MOD 915>, 1040 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1041 <&can_clk>; 1042 clock-names = "clkp1", "clkp2", "can_clk"; 1043 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1044 resets = <&cpg 915>; 1045 status = "disabled"; 1046 }; 1047 1048 pwm0: pwm@e6e30000 { 1049 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1050 reg = <0 0xe6e30000 0 0x8>; 1051 #pwm-cells = <2>; 1052 clocks = <&cpg CPG_MOD 523>; 1053 resets = <&cpg 523>; 1054 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1055 status = "disabled"; 1056 }; 1057 1058 pwm1: pwm@e6e31000 { 1059 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1060 reg = <0 0xe6e31000 0 0x8>; 1061 #pwm-cells = <2>; 1062 clocks = <&cpg CPG_MOD 523>; 1063 resets = <&cpg 523>; 1064 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1065 status = "disabled"; 1066 }; 1067 1068 pwm2: pwm@e6e32000 { 1069 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1070 reg = <0 0xe6e32000 0 0x8>; 1071 #pwm-cells = <2>; 1072 clocks = <&cpg CPG_MOD 523>; 1073 resets = <&cpg 523>; 1074 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1075 status = "disabled"; 1076 }; 1077 1078 pwm3: pwm@e6e33000 { 1079 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1080 reg = <0 0xe6e33000 0 0x8>; 1081 #pwm-cells = <2>; 1082 clocks = <&cpg CPG_MOD 523>; 1083 resets = <&cpg 523>; 1084 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1085 status = "disabled"; 1086 }; 1087 1088 pwm4: pwm@e6e34000 { 1089 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1090 reg = <0 0xe6e34000 0 0x8>; 1091 #pwm-cells = <2>; 1092 clocks = <&cpg CPG_MOD 523>; 1093 resets = <&cpg 523>; 1094 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1095 status = "disabled"; 1096 }; 1097 1098 pwm5: pwm@e6e35000 { 1099 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1100 reg = <0 0xe6e35000 0 0x8>; 1101 #pwm-cells = <2>; 1102 clocks = <&cpg CPG_MOD 523>; 1103 resets = <&cpg 523>; 1104 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1105 status = "disabled"; 1106 }; 1107 1108 pwm6: pwm@e6e36000 { 1109 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1110 reg = <0 0xe6e36000 0 0x8>; 1111 #pwm-cells = <2>; 1112 clocks = <&cpg CPG_MOD 523>; 1113 resets = <&cpg 523>; 1114 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1115 status = "disabled"; 1116 }; 1117 1118 scif0: serial@e6e60000 { 1119 compatible = "renesas,scif-r8a774a1", 1120 "renesas,rcar-gen3-scif", "renesas,scif"; 1121 reg = <0 0xe6e60000 0 0x40>; 1122 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&cpg CPG_MOD 207>, 1124 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1125 <&scif_clk>; 1126 clock-names = "fck", "brg_int", "scif_clk"; 1127 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1128 <&dmac2 0x51>, <&dmac2 0x50>; 1129 dma-names = "tx", "rx", "tx", "rx"; 1130 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1131 resets = <&cpg 207>; 1132 status = "disabled"; 1133 }; 1134 1135 scif1: serial@e6e68000 { 1136 compatible = "renesas,scif-r8a774a1", 1137 "renesas,rcar-gen3-scif", "renesas,scif"; 1138 reg = <0 0xe6e68000 0 0x40>; 1139 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&cpg CPG_MOD 206>, 1141 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1142 <&scif_clk>; 1143 clock-names = "fck", "brg_int", "scif_clk"; 1144 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1145 <&dmac2 0x53>, <&dmac2 0x52>; 1146 dma-names = "tx", "rx", "tx", "rx"; 1147 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1148 resets = <&cpg 206>; 1149 status = "disabled"; 1150 }; 1151 1152 scif2: serial@e6e88000 { 1153 compatible = "renesas,scif-r8a774a1", 1154 "renesas,rcar-gen3-scif", "renesas,scif"; 1155 reg = <0 0xe6e88000 0 0x40>; 1156 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&cpg CPG_MOD 310>, 1158 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1159 <&scif_clk>; 1160 clock-names = "fck", "brg_int", "scif_clk"; 1161 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1162 <&dmac2 0x13>, <&dmac2 0x12>; 1163 dma-names = "tx", "rx", "tx", "rx"; 1164 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1165 resets = <&cpg 310>; 1166 status = "disabled"; 1167 }; 1168 1169 scif3: serial@e6c50000 { 1170 compatible = "renesas,scif-r8a774a1", 1171 "renesas,rcar-gen3-scif", "renesas,scif"; 1172 reg = <0 0xe6c50000 0 0x40>; 1173 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&cpg CPG_MOD 204>, 1175 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1176 <&scif_clk>; 1177 clock-names = "fck", "brg_int", "scif_clk"; 1178 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1181 resets = <&cpg 204>; 1182 status = "disabled"; 1183 }; 1184 1185 scif4: serial@e6c40000 { 1186 compatible = "renesas,scif-r8a774a1", 1187 "renesas,rcar-gen3-scif", "renesas,scif"; 1188 reg = <0 0xe6c40000 0 0x40>; 1189 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&cpg CPG_MOD 203>, 1191 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1192 <&scif_clk>; 1193 clock-names = "fck", "brg_int", "scif_clk"; 1194 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1195 dma-names = "tx", "rx"; 1196 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1197 resets = <&cpg 203>; 1198 status = "disabled"; 1199 }; 1200 1201 scif5: serial@e6f30000 { 1202 compatible = "renesas,scif-r8a774a1", 1203 "renesas,rcar-gen3-scif", "renesas,scif"; 1204 reg = <0 0xe6f30000 0 0x40>; 1205 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&cpg CPG_MOD 202>, 1207 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1208 <&scif_clk>; 1209 clock-names = "fck", "brg_int", "scif_clk"; 1210 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1211 <&dmac2 0x5b>, <&dmac2 0x5a>; 1212 dma-names = "tx", "rx", "tx", "rx"; 1213 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1214 resets = <&cpg 202>; 1215 status = "disabled"; 1216 }; 1217 1218 msiof0: spi@e6e90000 { 1219 compatible = "renesas,msiof-r8a774a1", 1220 "renesas,rcar-gen3-msiof"; 1221 reg = <0 0xe6e90000 0 0x0064>; 1222 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&cpg CPG_MOD 211>; 1224 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1225 <&dmac2 0x41>, <&dmac2 0x40>; 1226 dma-names = "tx", "rx", "tx", "rx"; 1227 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1228 resets = <&cpg 211>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 status = "disabled"; 1232 }; 1233 1234 msiof1: spi@e6ea0000 { 1235 compatible = "renesas,msiof-r8a774a1", 1236 "renesas,rcar-gen3-msiof"; 1237 reg = <0 0xe6ea0000 0 0x0064>; 1238 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&cpg CPG_MOD 210>; 1240 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1241 <&dmac2 0x43>, <&dmac2 0x42>; 1242 dma-names = "tx", "rx", "tx", "rx"; 1243 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1244 resets = <&cpg 210>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 msiof2: spi@e6c00000 { 1251 compatible = "renesas,msiof-r8a774a1", 1252 "renesas,rcar-gen3-msiof"; 1253 reg = <0 0xe6c00000 0 0x0064>; 1254 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&cpg CPG_MOD 209>; 1256 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1257 dma-names = "tx", "rx"; 1258 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1259 resets = <&cpg 209>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 status = "disabled"; 1263 }; 1264 1265 msiof3: spi@e6c10000 { 1266 compatible = "renesas,msiof-r8a774a1", 1267 "renesas,rcar-gen3-msiof"; 1268 reg = <0 0xe6c10000 0 0x0064>; 1269 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&cpg CPG_MOD 208>; 1271 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1272 dma-names = "tx", "rx"; 1273 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1274 resets = <&cpg 208>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 vin0: video@e6ef0000 { 1281 compatible = "renesas,vin-r8a774a1"; 1282 reg = <0 0xe6ef0000 0 0x1000>; 1283 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&cpg CPG_MOD 811>; 1285 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1286 resets = <&cpg 811>; 1287 renesas,id = <0>; 1288 status = "disabled"; 1289 1290 ports { 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 1294 port@1 { 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 1298 reg = <1>; 1299 1300 vin0csi20: endpoint@0 { 1301 reg = <0>; 1302 remote-endpoint = <&csi20vin0>; 1303 }; 1304 vin0csi40: endpoint@2 { 1305 reg = <2>; 1306 remote-endpoint = <&csi40vin0>; 1307 }; 1308 }; 1309 }; 1310 }; 1311 1312 vin1: video@e6ef1000 { 1313 compatible = "renesas,vin-r8a774a1"; 1314 reg = <0 0xe6ef1000 0 0x1000>; 1315 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&cpg CPG_MOD 810>; 1317 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1318 resets = <&cpg 810>; 1319 renesas,id = <1>; 1320 status = "disabled"; 1321 1322 ports { 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 1326 port@1 { 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 1330 reg = <1>; 1331 1332 vin1csi20: endpoint@0 { 1333 reg = <0>; 1334 remote-endpoint = <&csi20vin1>; 1335 }; 1336 vin1csi40: endpoint@2 { 1337 reg = <2>; 1338 remote-endpoint = <&csi40vin1>; 1339 }; 1340 }; 1341 }; 1342 }; 1343 1344 vin2: video@e6ef2000 { 1345 compatible = "renesas,vin-r8a774a1"; 1346 reg = <0 0xe6ef2000 0 0x1000>; 1347 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&cpg CPG_MOD 809>; 1349 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1350 resets = <&cpg 809>; 1351 renesas,id = <2>; 1352 status = "disabled"; 1353 1354 ports { 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 1358 port@1 { 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 1362 reg = <1>; 1363 1364 vin2csi20: endpoint@0 { 1365 reg = <0>; 1366 remote-endpoint = <&csi20vin2>; 1367 }; 1368 vin2csi40: endpoint@2 { 1369 reg = <2>; 1370 remote-endpoint = <&csi40vin2>; 1371 }; 1372 }; 1373 }; 1374 }; 1375 1376 vin3: video@e6ef3000 { 1377 compatible = "renesas,vin-r8a774a1"; 1378 reg = <0 0xe6ef3000 0 0x1000>; 1379 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1380 clocks = <&cpg CPG_MOD 808>; 1381 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1382 resets = <&cpg 808>; 1383 renesas,id = <3>; 1384 status = "disabled"; 1385 1386 ports { 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 1390 port@1 { 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 1394 reg = <1>; 1395 1396 vin3csi20: endpoint@0 { 1397 reg = <0>; 1398 remote-endpoint = <&csi20vin3>; 1399 }; 1400 vin3csi40: endpoint@2 { 1401 reg = <2>; 1402 remote-endpoint = <&csi40vin3>; 1403 }; 1404 }; 1405 }; 1406 }; 1407 1408 vin4: video@e6ef4000 { 1409 compatible = "renesas,vin-r8a774a1"; 1410 reg = <0 0xe6ef4000 0 0x1000>; 1411 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cpg CPG_MOD 807>; 1413 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1414 resets = <&cpg 807>; 1415 renesas,id = <4>; 1416 status = "disabled"; 1417 1418 ports { 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 1422 port@1 { 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 reg = <1>; 1427 1428 vin4csi20: endpoint@0 { 1429 reg = <0>; 1430 remote-endpoint = <&csi20vin4>; 1431 }; 1432 vin4csi40: endpoint@2 { 1433 reg = <2>; 1434 remote-endpoint = <&csi40vin4>; 1435 }; 1436 }; 1437 }; 1438 }; 1439 1440 vin5: video@e6ef5000 { 1441 compatible = "renesas,vin-r8a774a1"; 1442 reg = <0 0xe6ef5000 0 0x1000>; 1443 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1444 clocks = <&cpg CPG_MOD 806>; 1445 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1446 resets = <&cpg 806>; 1447 renesas,id = <5>; 1448 status = "disabled"; 1449 1450 ports { 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 1454 port@1 { 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 1458 reg = <1>; 1459 1460 vin5csi20: endpoint@0 { 1461 reg = <0>; 1462 remote-endpoint = <&csi20vin5>; 1463 }; 1464 vin5csi40: endpoint@2 { 1465 reg = <2>; 1466 remote-endpoint = <&csi40vin5>; 1467 }; 1468 }; 1469 }; 1470 }; 1471 1472 vin6: video@e6ef6000 { 1473 compatible = "renesas,vin-r8a774a1"; 1474 reg = <0 0xe6ef6000 0 0x1000>; 1475 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&cpg CPG_MOD 805>; 1477 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1478 resets = <&cpg 805>; 1479 renesas,id = <6>; 1480 status = "disabled"; 1481 1482 ports { 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 1486 port@1 { 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 1490 reg = <1>; 1491 1492 vin6csi20: endpoint@0 { 1493 reg = <0>; 1494 remote-endpoint = <&csi20vin6>; 1495 }; 1496 vin6csi40: endpoint@2 { 1497 reg = <2>; 1498 remote-endpoint = <&csi40vin6>; 1499 }; 1500 }; 1501 }; 1502 }; 1503 1504 vin7: video@e6ef7000 { 1505 compatible = "renesas,vin-r8a774a1"; 1506 reg = <0 0xe6ef7000 0 0x1000>; 1507 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1508 clocks = <&cpg CPG_MOD 804>; 1509 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1510 resets = <&cpg 804>; 1511 renesas,id = <7>; 1512 status = "disabled"; 1513 1514 ports { 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 1518 port@1 { 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 1522 reg = <1>; 1523 1524 vin7csi20: endpoint@0 { 1525 reg = <0>; 1526 remote-endpoint = <&csi20vin7>; 1527 }; 1528 vin7csi40: endpoint@2 { 1529 reg = <2>; 1530 remote-endpoint = <&csi40vin7>; 1531 }; 1532 }; 1533 }; 1534 }; 1535 1536 rcar_sound: sound@ec500000 { 1537 /* 1538 * #sound-dai-cells is required 1539 * 1540 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1541 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1542 */ 1543 /* 1544 * #clock-cells is required for audio_clkout0/1/2/3 1545 * 1546 * clkout : #clock-cells = <0>; <&rcar_sound>; 1547 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1548 */ 1549 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1550 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1551 <0 0xec5a0000 0 0x100>, /* ADG */ 1552 <0 0xec540000 0 0x1000>, /* SSIU */ 1553 <0 0xec541000 0 0x280>, /* SSI */ 1554 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1555 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1556 1557 clocks = <&cpg CPG_MOD 1005>, 1558 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1559 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1560 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1561 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1562 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1563 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1564 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1565 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1566 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1567 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1568 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1569 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1570 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1571 <&audio_clk_a>, <&audio_clk_b>, 1572 <&audio_clk_c>, 1573 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1574 clock-names = "ssi-all", 1575 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1576 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1577 "ssi.1", "ssi.0", 1578 "src.9", "src.8", "src.7", "src.6", 1579 "src.5", "src.4", "src.3", "src.2", 1580 "src.1", "src.0", 1581 "mix.1", "mix.0", 1582 "ctu.1", "ctu.0", 1583 "dvc.0", "dvc.1", 1584 "clk_a", "clk_b", "clk_c", "clk_i"; 1585 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1586 resets = <&cpg 1005>, 1587 <&cpg 1006>, <&cpg 1007>, 1588 <&cpg 1008>, <&cpg 1009>, 1589 <&cpg 1010>, <&cpg 1011>, 1590 <&cpg 1012>, <&cpg 1013>, 1591 <&cpg 1014>, <&cpg 1015>; 1592 reset-names = "ssi-all", 1593 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1594 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1595 "ssi.1", "ssi.0"; 1596 status = "disabled"; 1597 1598 rcar_sound,dvc { 1599 dvc0: dvc-0 { 1600 dmas = <&audma1 0xbc>; 1601 dma-names = "tx"; 1602 }; 1603 dvc1: dvc-1 { 1604 dmas = <&audma1 0xbe>; 1605 dma-names = "tx"; 1606 }; 1607 }; 1608 1609 rcar_sound,mix { 1610 mix0: mix-0 { }; 1611 mix1: mix-1 { }; 1612 }; 1613 1614 rcar_sound,ctu { 1615 ctu00: ctu-0 { }; 1616 ctu01: ctu-1 { }; 1617 ctu02: ctu-2 { }; 1618 ctu03: ctu-3 { }; 1619 ctu10: ctu-4 { }; 1620 ctu11: ctu-5 { }; 1621 ctu12: ctu-6 { }; 1622 ctu13: ctu-7 { }; 1623 }; 1624 1625 rcar_sound,src { 1626 src0: src-0 { 1627 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1628 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1629 dma-names = "rx", "tx"; 1630 }; 1631 src1: src-1 { 1632 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1633 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1634 dma-names = "rx", "tx"; 1635 }; 1636 src2: src-2 { 1637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1638 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1639 dma-names = "rx", "tx"; 1640 }; 1641 src3: src-3 { 1642 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1643 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1644 dma-names = "rx", "tx"; 1645 }; 1646 src4: src-4 { 1647 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1648 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1649 dma-names = "rx", "tx"; 1650 }; 1651 src5: src-5 { 1652 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1653 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1654 dma-names = "rx", "tx"; 1655 }; 1656 src6: src-6 { 1657 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1658 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1659 dma-names = "rx", "tx"; 1660 }; 1661 src7: src-7 { 1662 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1663 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1664 dma-names = "rx", "tx"; 1665 }; 1666 src8: src-8 { 1667 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1668 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1669 dma-names = "rx", "tx"; 1670 }; 1671 src9: src-9 { 1672 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1673 dmas = <&audma0 0x97>, <&audma1 0xba>; 1674 dma-names = "rx", "tx"; 1675 }; 1676 }; 1677 1678 rcar_sound,ssi { 1679 ssi0: ssi-0 { 1680 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1681 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1682 dma-names = "rx", "tx", "rxu", "txu"; 1683 }; 1684 ssi1: ssi-1 { 1685 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1686 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1687 dma-names = "rx", "tx", "rxu", "txu"; 1688 }; 1689 ssi2: ssi-2 { 1690 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1691 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1692 dma-names = "rx", "tx", "rxu", "txu"; 1693 }; 1694 ssi3: ssi-3 { 1695 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1696 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1697 dma-names = "rx", "tx", "rxu", "txu"; 1698 }; 1699 ssi4: ssi-4 { 1700 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1701 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1702 dma-names = "rx", "tx", "rxu", "txu"; 1703 }; 1704 ssi5: ssi-5 { 1705 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1706 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1707 dma-names = "rx", "tx", "rxu", "txu"; 1708 }; 1709 ssi6: ssi-6 { 1710 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1711 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1712 dma-names = "rx", "tx", "rxu", "txu"; 1713 }; 1714 ssi7: ssi-7 { 1715 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1716 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1717 dma-names = "rx", "tx", "rxu", "txu"; 1718 }; 1719 ssi8: ssi-8 { 1720 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1721 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1722 dma-names = "rx", "tx", "rxu", "txu"; 1723 }; 1724 ssi9: ssi-9 { 1725 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1726 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1727 dma-names = "rx", "tx", "rxu", "txu"; 1728 }; 1729 }; 1730 1731 ports { 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 port@0 { 1735 reg = <0>; 1736 }; 1737 port@1 { 1738 reg = <1>; 1739 }; 1740 }; 1741 }; 1742 1743 audma0: dma-controller@ec700000 { 1744 compatible = "renesas,dmac-r8a774a1", 1745 "renesas,rcar-dmac"; 1746 reg = <0 0xec700000 0 0x10000>; 1747 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1748 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1749 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1750 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1751 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1752 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1753 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1754 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1755 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1756 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1757 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1758 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1759 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1760 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1761 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1762 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1763 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1764 interrupt-names = "error", 1765 "ch0", "ch1", "ch2", "ch3", 1766 "ch4", "ch5", "ch6", "ch7", 1767 "ch8", "ch9", "ch10", "ch11", 1768 "ch12", "ch13", "ch14", "ch15"; 1769 clocks = <&cpg CPG_MOD 502>; 1770 clock-names = "fck"; 1771 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1772 resets = <&cpg 502>; 1773 #dma-cells = <1>; 1774 dma-channels = <16>; 1775 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1776 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1777 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1778 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1779 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1780 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1781 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1782 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1783 }; 1784 1785 audma1: dma-controller@ec720000 { 1786 compatible = "renesas,dmac-r8a774a1", 1787 "renesas,rcar-dmac"; 1788 reg = <0 0xec720000 0 0x10000>; 1789 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1790 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1791 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1792 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1793 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1794 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1795 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1796 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1797 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1798 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1799 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1800 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1801 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1802 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1803 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1804 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1805 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1806 interrupt-names = "error", 1807 "ch0", "ch1", "ch2", "ch3", 1808 "ch4", "ch5", "ch6", "ch7", 1809 "ch8", "ch9", "ch10", "ch11", 1810 "ch12", "ch13", "ch14", "ch15"; 1811 clocks = <&cpg CPG_MOD 501>; 1812 clock-names = "fck"; 1813 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1814 resets = <&cpg 501>; 1815 #dma-cells = <1>; 1816 dma-channels = <16>; 1817 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1818 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1819 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1820 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1821 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1822 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1823 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1824 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1825 }; 1826 1827 xhci0: usb@ee000000 { 1828 compatible = "renesas,xhci-r8a774a1", 1829 "renesas,rcar-gen3-xhci"; 1830 reg = <0 0xee000000 0 0xc00>; 1831 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1832 clocks = <&cpg CPG_MOD 328>; 1833 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1834 resets = <&cpg 328>; 1835 status = "disabled"; 1836 }; 1837 1838 usb3_peri0: usb@ee020000 { 1839 compatible = "renesas,r8a774a1-usb3-peri", 1840 "renesas,rcar-gen3-usb3-peri"; 1841 reg = <0 0xee020000 0 0x400>; 1842 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1843 clocks = <&cpg CPG_MOD 328>; 1844 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1845 resets = <&cpg 328>; 1846 status = "disabled"; 1847 }; 1848 1849 ohci0: usb@ee080000 { 1850 compatible = "generic-ohci"; 1851 reg = <0 0xee080000 0 0x100>; 1852 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&cpg CPG_MOD 703>; 1854 phys = <&usb2_phy0 1>; 1855 phy-names = "usb"; 1856 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1857 resets = <&cpg 703>; 1858 status = "disabled"; 1859 }; 1860 1861 ohci1: usb@ee0a0000 { 1862 compatible = "generic-ohci"; 1863 reg = <0 0xee0a0000 0 0x100>; 1864 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&cpg CPG_MOD 702>; 1866 phys = <&usb2_phy1 1>; 1867 phy-names = "usb"; 1868 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1869 resets = <&cpg 702>; 1870 status = "disabled"; 1871 }; 1872 1873 ehci0: usb@ee080100 { 1874 compatible = "generic-ehci"; 1875 reg = <0 0xee080100 0 0x100>; 1876 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1877 clocks = <&cpg CPG_MOD 703>; 1878 phys = <&usb2_phy0 2>; 1879 phy-names = "usb"; 1880 companion = <&ohci0>; 1881 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1882 resets = <&cpg 703>; 1883 status = "disabled"; 1884 }; 1885 1886 ehci1: usb@ee0a0100 { 1887 compatible = "generic-ehci"; 1888 reg = <0 0xee0a0100 0 0x100>; 1889 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&cpg CPG_MOD 702>; 1891 phys = <&usb2_phy1 2>; 1892 phy-names = "usb"; 1893 companion = <&ohci1>; 1894 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1895 resets = <&cpg 702>; 1896 status = "disabled"; 1897 }; 1898 1899 usb2_phy0: usb-phy@ee080200 { 1900 compatible = "renesas,usb2-phy-r8a774a1", 1901 "renesas,rcar-gen3-usb2-phy"; 1902 reg = <0 0xee080200 0 0x700>; 1903 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&cpg CPG_MOD 703>; 1905 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1906 resets = <&cpg 703>; 1907 #phy-cells = <1>; 1908 status = "disabled"; 1909 }; 1910 1911 usb2_phy1: usb-phy@ee0a0200 { 1912 compatible = "renesas,usb2-phy-r8a774a1", 1913 "renesas,rcar-gen3-usb2-phy"; 1914 reg = <0 0xee0a0200 0 0x700>; 1915 clocks = <&cpg CPG_MOD 702>; 1916 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1917 resets = <&cpg 702>; 1918 #phy-cells = <1>; 1919 status = "disabled"; 1920 }; 1921 1922 sdhi0: sd@ee100000 { 1923 compatible = "renesas,sdhi-r8a774a1", 1924 "renesas,rcar-gen3-sdhi"; 1925 reg = <0 0xee100000 0 0x2000>; 1926 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1927 clocks = <&cpg CPG_MOD 314>; 1928 max-frequency = <200000000>; 1929 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1930 resets = <&cpg 314>; 1931 status = "disabled"; 1932 }; 1933 1934 sdhi1: sd@ee120000 { 1935 compatible = "renesas,sdhi-r8a774a1", 1936 "renesas,rcar-gen3-sdhi"; 1937 reg = <0 0xee120000 0 0x2000>; 1938 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1939 clocks = <&cpg CPG_MOD 313>; 1940 max-frequency = <200000000>; 1941 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1942 resets = <&cpg 313>; 1943 status = "disabled"; 1944 }; 1945 1946 sdhi2: sd@ee140000 { 1947 compatible = "renesas,sdhi-r8a774a1", 1948 "renesas,rcar-gen3-sdhi"; 1949 reg = <0 0xee140000 0 0x2000>; 1950 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1951 clocks = <&cpg CPG_MOD 312>; 1952 max-frequency = <200000000>; 1953 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1954 resets = <&cpg 312>; 1955 status = "disabled"; 1956 }; 1957 1958 sdhi3: sd@ee160000 { 1959 compatible = "renesas,sdhi-r8a774a1", 1960 "renesas,rcar-gen3-sdhi"; 1961 reg = <0 0xee160000 0 0x2000>; 1962 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1963 clocks = <&cpg CPG_MOD 311>; 1964 max-frequency = <200000000>; 1965 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1966 resets = <&cpg 311>; 1967 status = "disabled"; 1968 }; 1969 1970 gic: interrupt-controller@f1010000 { 1971 compatible = "arm,gic-400"; 1972 #interrupt-cells = <3>; 1973 #address-cells = <0>; 1974 interrupt-controller; 1975 reg = <0x0 0xf1010000 0 0x1000>, 1976 <0x0 0xf1020000 0 0x20000>, 1977 <0x0 0xf1040000 0 0x20000>, 1978 <0x0 0xf1060000 0 0x20000>; 1979 interrupts = <GIC_PPI 9 1980 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1981 clocks = <&cpg CPG_MOD 408>; 1982 clock-names = "clk"; 1983 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1984 resets = <&cpg 408>; 1985 }; 1986 1987 pciec0: pcie@fe000000 { 1988 compatible = "renesas,pcie-r8a774a1", 1989 "renesas,pcie-rcar-gen3"; 1990 reg = <0 0xfe000000 0 0x80000>; 1991 #address-cells = <3>; 1992 #size-cells = <2>; 1993 bus-range = <0x00 0xff>; 1994 device_type = "pci"; 1995 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1996 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1997 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1998 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1999 /* Map all possible DDR as inbound ranges */ 2000 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2001 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2004 #interrupt-cells = <1>; 2005 interrupt-map-mask = <0 0 0 0>; 2006 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2007 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2008 clock-names = "pcie", "pcie_bus"; 2009 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2010 resets = <&cpg 319>; 2011 status = "disabled"; 2012 }; 2013 2014 pciec1: pcie@ee800000 { 2015 compatible = "renesas,pcie-r8a774a1", 2016 "renesas,pcie-rcar-gen3"; 2017 reg = <0 0xee800000 0 0x80000>; 2018 #address-cells = <3>; 2019 #size-cells = <2>; 2020 bus-range = <0x00 0xff>; 2021 device_type = "pci"; 2022 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 2023 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 2024 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 2025 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2026 /* Map all possible DDR as inbound ranges */ 2027 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2028 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2031 #interrupt-cells = <1>; 2032 interrupt-map-mask = <0 0 0 0>; 2033 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2034 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2035 clock-names = "pcie", "pcie_bus"; 2036 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2037 resets = <&cpg 318>; 2038 status = "disabled"; 2039 }; 2040 2041 fdp1@fe940000 { 2042 compatible = "renesas,fdp1"; 2043 reg = <0 0xfe940000 0 0x2400>; 2044 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2045 clocks = <&cpg CPG_MOD 119>; 2046 power-domains = <&sysc R8A774A1_PD_A3VC>; 2047 resets = <&cpg 119>; 2048 renesas,fcp = <&fcpf0>; 2049 }; 2050 2051 fcpf0: fcp@fe950000 { 2052 compatible = "renesas,fcpf"; 2053 reg = <0 0xfe950000 0 0x200>; 2054 clocks = <&cpg CPG_MOD 615>; 2055 power-domains = <&sysc R8A774A1_PD_A3VC>; 2056 resets = <&cpg 615>; 2057 }; 2058 2059 fcpvb0: fcp@fe96f000 { 2060 compatible = "renesas,fcpv"; 2061 reg = <0 0xfe96f000 0 0x200>; 2062 clocks = <&cpg CPG_MOD 607>; 2063 power-domains = <&sysc R8A774A1_PD_A3VC>; 2064 resets = <&cpg 607>; 2065 }; 2066 2067 fcpvd0: fcp@fea27000 { 2068 compatible = "renesas,fcpv"; 2069 reg = <0 0xfea27000 0 0x200>; 2070 clocks = <&cpg CPG_MOD 603>; 2071 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2072 resets = <&cpg 603>; 2073 iommus = <&ipmmu_vi0 8>; 2074 }; 2075 2076 fcpvd1: fcp@fea2f000 { 2077 compatible = "renesas,fcpv"; 2078 reg = <0 0xfea2f000 0 0x200>; 2079 clocks = <&cpg CPG_MOD 602>; 2080 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2081 resets = <&cpg 602>; 2082 iommus = <&ipmmu_vi0 9>; 2083 }; 2084 2085 fcpvd2: fcp@fea37000 { 2086 compatible = "renesas,fcpv"; 2087 reg = <0 0xfea37000 0 0x200>; 2088 clocks = <&cpg CPG_MOD 601>; 2089 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2090 resets = <&cpg 601>; 2091 iommus = <&ipmmu_vi0 10>; 2092 }; 2093 2094 fcpvi0: fcp@fe9af000 { 2095 compatible = "renesas,fcpv"; 2096 reg = <0 0xfe9af000 0 0x200>; 2097 clocks = <&cpg CPG_MOD 611>; 2098 power-domains = <&sysc R8A774A1_PD_A3VC>; 2099 resets = <&cpg 611>; 2100 iommus = <&ipmmu_vc0 19>; 2101 }; 2102 2103 vspb: vsp@fe960000 { 2104 compatible = "renesas,vsp2"; 2105 reg = <0 0xfe960000 0 0x8000>; 2106 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2107 clocks = <&cpg CPG_MOD 626>; 2108 power-domains = <&sysc R8A774A1_PD_A3VC>; 2109 resets = <&cpg 626>; 2110 2111 renesas,fcp = <&fcpvb0>; 2112 }; 2113 2114 vspd0: vsp@fea20000 { 2115 compatible = "renesas,vsp2"; 2116 reg = <0 0xfea20000 0 0x5000>; 2117 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2118 clocks = <&cpg CPG_MOD 623>; 2119 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2120 resets = <&cpg 623>; 2121 2122 renesas,fcp = <&fcpvd0>; 2123 }; 2124 2125 vspd1: vsp@fea28000 { 2126 compatible = "renesas,vsp2"; 2127 reg = <0 0xfea28000 0 0x5000>; 2128 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2129 clocks = <&cpg CPG_MOD 622>; 2130 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2131 resets = <&cpg 622>; 2132 2133 renesas,fcp = <&fcpvd1>; 2134 }; 2135 2136 vspd2: vsp@fea30000 { 2137 compatible = "renesas,vsp2"; 2138 reg = <0 0xfea30000 0 0x5000>; 2139 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2140 clocks = <&cpg CPG_MOD 621>; 2141 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2142 resets = <&cpg 621>; 2143 2144 renesas,fcp = <&fcpvd2>; 2145 }; 2146 2147 vspi0: vsp@fe9a0000 { 2148 compatible = "renesas,vsp2"; 2149 reg = <0 0xfe9a0000 0 0x8000>; 2150 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2151 clocks = <&cpg CPG_MOD 631>; 2152 power-domains = <&sysc R8A774A1_PD_A3VC>; 2153 resets = <&cpg 631>; 2154 2155 renesas,fcp = <&fcpvi0>; 2156 }; 2157 2158 csi20: csi2@fea80000 { 2159 compatible = "renesas,r8a774a1-csi2"; 2160 reg = <0 0xfea80000 0 0x10000>; 2161 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&cpg CPG_MOD 714>; 2163 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2164 resets = <&cpg 714>; 2165 status = "disabled"; 2166 2167 ports { 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 2171 port@1 { 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 2175 reg = <1>; 2176 2177 csi20vin0: endpoint@0 { 2178 reg = <0>; 2179 remote-endpoint = <&vin0csi20>; 2180 }; 2181 csi20vin1: endpoint@1 { 2182 reg = <1>; 2183 remote-endpoint = <&vin1csi20>; 2184 }; 2185 csi20vin2: endpoint@2 { 2186 reg = <2>; 2187 remote-endpoint = <&vin2csi20>; 2188 }; 2189 csi20vin3: endpoint@3 { 2190 reg = <3>; 2191 remote-endpoint = <&vin3csi20>; 2192 }; 2193 csi20vin4: endpoint@4 { 2194 reg = <4>; 2195 remote-endpoint = <&vin4csi20>; 2196 }; 2197 csi20vin5: endpoint@5 { 2198 reg = <5>; 2199 remote-endpoint = <&vin5csi20>; 2200 }; 2201 csi20vin6: endpoint@6 { 2202 reg = <6>; 2203 remote-endpoint = <&vin6csi20>; 2204 }; 2205 csi20vin7: endpoint@7 { 2206 reg = <7>; 2207 remote-endpoint = <&vin7csi20>; 2208 }; 2209 }; 2210 }; 2211 }; 2212 2213 csi40: csi2@feaa0000 { 2214 compatible = "renesas,r8a774a1-csi2"; 2215 reg = <0 0xfeaa0000 0 0x10000>; 2216 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2217 clocks = <&cpg CPG_MOD 716>; 2218 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2219 resets = <&cpg 716>; 2220 status = "disabled"; 2221 2222 ports { 2223 #address-cells = <1>; 2224 #size-cells = <0>; 2225 2226 port@1 { 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 2230 reg = <1>; 2231 2232 csi40vin0: endpoint@0 { 2233 reg = <0>; 2234 remote-endpoint = <&vin0csi40>; 2235 }; 2236 csi40vin1: endpoint@1 { 2237 reg = <1>; 2238 remote-endpoint = <&vin1csi40>; 2239 }; 2240 csi40vin2: endpoint@2 { 2241 reg = <2>; 2242 remote-endpoint = <&vin2csi40>; 2243 }; 2244 csi40vin3: endpoint@3 { 2245 reg = <3>; 2246 remote-endpoint = <&vin3csi40>; 2247 }; 2248 csi40vin4: endpoint@4 { 2249 reg = <4>; 2250 remote-endpoint = <&vin4csi40>; 2251 }; 2252 csi40vin5: endpoint@5 { 2253 reg = <5>; 2254 remote-endpoint = <&vin5csi40>; 2255 }; 2256 csi40vin6: endpoint@6 { 2257 reg = <6>; 2258 remote-endpoint = <&vin6csi40>; 2259 }; 2260 csi40vin7: endpoint@7 { 2261 reg = <7>; 2262 remote-endpoint = <&vin7csi40>; 2263 }; 2264 }; 2265 2266 }; 2267 }; 2268 2269 du: display@feb00000 { 2270 compatible = "renesas,du-r8a774a1"; 2271 reg = <0 0xfeb00000 0 0x70000>; 2272 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2275 clocks = <&cpg CPG_MOD 724>, 2276 <&cpg CPG_MOD 723>, 2277 <&cpg CPG_MOD 722>; 2278 clock-names = "du.0", "du.1", "du.2"; 2279 status = "disabled"; 2280 2281 vsps = <&vspd0 &vspd1 &vspd2>; 2282 2283 ports { 2284 #address-cells = <1>; 2285 #size-cells = <0>; 2286 2287 port@0 { 2288 reg = <0>; 2289 du_out_rgb: endpoint { 2290 }; 2291 }; 2292 port@1 { 2293 reg = <1>; 2294 du_out_hdmi0: endpoint { 2295 }; 2296 }; 2297 port@2 { 2298 reg = <2>; 2299 du_out_lvds0: endpoint { 2300 remote-endpoint = <&lvds0_in>; 2301 }; 2302 }; 2303 }; 2304 }; 2305 2306 lvds0: lvds@feb90000 { 2307 compatible = "renesas,r8a774a1-lvds"; 2308 reg = <0 0xfeb90000 0 0x14>; 2309 clocks = <&cpg CPG_MOD 727>; 2310 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2311 resets = <&cpg 727>; 2312 status = "disabled"; 2313 2314 ports { 2315 #address-cells = <1>; 2316 #size-cells = <0>; 2317 2318 port@0 { 2319 reg = <0>; 2320 lvds0_in: endpoint { 2321 remote-endpoint = <&du_out_lvds0>; 2322 }; 2323 }; 2324 port@1 { 2325 reg = <1>; 2326 lvds0_out: endpoint { 2327 }; 2328 }; 2329 }; 2330 }; 2331 2332 prr: chipid@fff00044 { 2333 compatible = "renesas,prr"; 2334 reg = <0 0xfff00044 0 4>; 2335 }; 2336 }; 2337 2338 thermal-zones { 2339 sensor_thermal1: sensor-thermal1 { 2340 polling-delay-passive = <250>; 2341 polling-delay = <1000>; 2342 thermal-sensors = <&tsc 0>; 2343 2344 trips { 2345 sensor1_crit: sensor1-crit { 2346 temperature = <120000>; 2347 hysteresis = <1000>; 2348 type = "critical"; 2349 }; 2350 }; 2351 }; 2352 2353 sensor_thermal2: sensor-thermal2 { 2354 polling-delay-passive = <250>; 2355 polling-delay = <1000>; 2356 thermal-sensors = <&tsc 1>; 2357 2358 trips { 2359 sensor2_crit: sensor2-crit { 2360 temperature = <120000>; 2361 hysteresis = <1000>; 2362 type = "critical"; 2363 }; 2364 }; 2365 2366 }; 2367 2368 sensor_thermal3: sensor-thermal3 { 2369 polling-delay-passive = <250>; 2370 polling-delay = <1000>; 2371 thermal-sensors = <&tsc 2>; 2372 2373 trips { 2374 sensor3_crit: sensor3-crit { 2375 temperature = <120000>; 2376 hysteresis = <1000>; 2377 type = "critical"; 2378 }; 2379 }; 2380 }; 2381 }; 2382 2383 timer { 2384 compatible = "arm,armv8-timer"; 2385 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2386 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2387 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2388 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2389 }; 2390 2391 /* External USB clocks - can be overridden by the board */ 2392 usb3s0_clk: usb3s0 { 2393 compatible = "fixed-clock"; 2394 #clock-cells = <0>; 2395 clock-frequency = <0>; 2396 }; 2397 2398 usb_extal_clk: usb_extal { 2399 compatible = "fixed-clock"; 2400 #clock-cells = <0>; 2401 clock-frequency = <0>; 2402 }; 2403}; 2404