r8a774a1.dtsi (5f5249497bd7ed65d90cac36c3c3dabcda2903dd) r8a774a1.dtsi (06a928fb5805d1bb80a87c557ac487b916adc50d)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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133 reg = <0x0>;
134 device_type = "cpu";
135 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
136 next-level-cache = <&L2_CA57>;
137 enable-method = "psci";
138 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
139 operating-points-v2 = <&cluster0_opp>;
140 capacity-dmips-mhz = <1024>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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133 reg = <0x0>;
134 device_type = "cpu";
135 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
136 next-level-cache = <&L2_CA57>;
137 enable-method = "psci";
138 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
139 operating-points-v2 = <&cluster0_opp>;
140 capacity-dmips-mhz = <1024>;
141 #cooling-cells = <2>;
141 };
142
143 a57_1: cpu@1 {
144 compatible = "arm,cortex-a57";
145 reg = <0x1>;
146 device_type = "cpu";
147 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
148 next-level-cache = <&L2_CA57>;
149 enable-method = "psci";
150 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
151 operating-points-v2 = <&cluster0_opp>;
152 capacity-dmips-mhz = <1024>;
142 };
143
144 a57_1: cpu@1 {
145 compatible = "arm,cortex-a57";
146 reg = <0x1>;
147 device_type = "cpu";
148 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
149 next-level-cache = <&L2_CA57>;
150 enable-method = "psci";
151 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
152 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>;
153 };
154
155 a53_0: cpu@100 {
156 compatible = "arm,cortex-a53";
157 reg = <0x100>;
158 device_type = "cpu";
159 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
160 next-level-cache = <&L2_CA53>;
161 enable-method = "psci";
155 };
156
157 a53_0: cpu@100 {
158 compatible = "arm,cortex-a53";
159 reg = <0x100>;
160 device_type = "cpu";
161 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
162 next-level-cache = <&L2_CA53>;
163 enable-method = "psci";
164 #cooling-cells = <2>;
162 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
163 operating-points-v2 = <&cluster1_opp>;
164 capacity-dmips-mhz = <560>;
165 };
166
167 a53_1: cpu@101 {
168 compatible = "arm,cortex-a53";
169 reg = <0x101>;

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2432 };
2433 };
2434
2435 thermal-zones {
2436 sensor_thermal1: sensor-thermal1 {
2437 polling-delay-passive = <250>;
2438 polling-delay = <1000>;
2439 thermal-sensors = <&tsc 0>;
165 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
166 operating-points-v2 = <&cluster1_opp>;
167 capacity-dmips-mhz = <560>;
168 };
169
170 a53_1: cpu@101 {
171 compatible = "arm,cortex-a53";
172 reg = <0x101>;

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2435 };
2436 };
2437
2438 thermal-zones {
2439 sensor_thermal1: sensor-thermal1 {
2440 polling-delay-passive = <250>;
2441 polling-delay = <1000>;
2442 thermal-sensors = <&tsc 0>;
2443 sustainable-power = <3874>;
2440
2441 trips {
2442 sensor1_crit: sensor1-crit {
2443 temperature = <120000>;
2444 hysteresis = <1000>;
2445 type = "critical";
2446 };
2447 };
2448 };
2449
2450 sensor_thermal2: sensor-thermal2 {
2451 polling-delay-passive = <250>;
2452 polling-delay = <1000>;
2453 thermal-sensors = <&tsc 1>;
2444
2445 trips {
2446 sensor1_crit: sensor1-crit {
2447 temperature = <120000>;
2448 hysteresis = <1000>;
2449 type = "critical";
2450 };
2451 };
2452 };
2453
2454 sensor_thermal2: sensor-thermal2 {
2455 polling-delay-passive = <250>;
2456 polling-delay = <1000>;
2457 thermal-sensors = <&tsc 1>;
2458 sustainable-power = <3874>;
2454
2455 trips {
2456 sensor2_crit: sensor2-crit {
2457 temperature = <120000>;
2458 hysteresis = <1000>;
2459 type = "critical";
2460 };
2461 };
2459
2460 trips {
2461 sensor2_crit: sensor2-crit {
2462 temperature = <120000>;
2463 hysteresis = <1000>;
2464 type = "critical";
2465 };
2466 };
2462
2463 };
2464
2465 sensor_thermal3: sensor-thermal3 {
2466 polling-delay-passive = <250>;
2467 polling-delay = <1000>;
2468 thermal-sensors = <&tsc 2>;
2467 };
2468
2469 sensor_thermal3: sensor-thermal3 {
2470 polling-delay-passive = <250>;
2471 polling-delay = <1000>;
2472 thermal-sensors = <&tsc 2>;
2473 sustainable-power = <3874>;
2469
2470 trips {
2474
2475 trips {
2476 target: trip-point1 {
2477 temperature = <100000>;
2478 hysteresis = <1000>;
2479 type = "passive";
2480 };
2481
2471 sensor3_crit: sensor3-crit {
2472 temperature = <120000>;
2473 hysteresis = <1000>;
2474 type = "critical";
2475 };
2476 };
2482 sensor3_crit: sensor3-crit {
2483 temperature = <120000>;
2484 hysteresis = <1000>;
2485 type = "critical";
2486 };
2487 };
2488 cooling-maps {
2489 map0 {
2490 trip = <&target>;
2491 cooling-device = <&a57_0 0 2>;
2492 contribution = <1024>;
2493 };
2494 map1 {
2495 trip = <&target>;
2496 cooling-device = <&a53_0 0 2>;
2497 contribution = <1024>;
2498 };
2499 };
2477 };
2478 };
2479
2480 timer {
2481 compatible = "arm,armv8-timer";
2482 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2483 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2484 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

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2501 };
2502
2503 timer {
2504 compatible = "arm,armv8-timer";
2505 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2506 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
2507 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,

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