1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774a1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c_dvfs; 27 }; 28 29 /* 30 * The external audio clocks are configured as 0 Hz fixed frequency 31 * clocks by default. 32 * Boards that provide audio clocks should override them. 33 */ 34 audio_clk_a: audio_clk_a { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 audio_clk_b: audio_clk_b { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 }; 45 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock - to be overridden by boards that provide it */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 }; 58 59 cluster0_opp: opp_table0 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-500000000 { 64 opp-hz = /bits/ 64 <500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1500000000 { 74 opp-hz = /bits/ 64 <1500000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cluster1_opp: opp_table1 { 81 compatible = "operating-points-v2"; 82 opp-shared; 83 84 opp-800000000 { 85 opp-hz = /bits/ 64 <800000000>; 86 opp-microvolt = <820000>; 87 clock-latency-ns = <300000>; 88 }; 89 opp-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = <820000>; 92 clock-latency-ns = <300000>; 93 }; 94 opp-1200000000 { 95 opp-hz = /bits/ 64 <1200000000>; 96 opp-microvolt = <820000>; 97 clock-latency-ns = <300000>; 98 }; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 cpu-map { 106 cluster0 { 107 core0 { 108 cpu = <&a57_0>; 109 }; 110 core1 { 111 cpu = <&a57_1>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&a53_0>; 118 }; 119 core1 { 120 cpu = <&a53_1>; 121 }; 122 core2 { 123 cpu = <&a53_2>; 124 }; 125 core3 { 126 cpu = <&a53_3>; 127 }; 128 }; 129 }; 130 131 a57_0: cpu@0 { 132 compatible = "arm,cortex-a57"; 133 reg = <0x0>; 134 device_type = "cpu"; 135 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 136 next-level-cache = <&L2_CA57>; 137 enable-method = "psci"; 138 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 139 operating-points-v2 = <&cluster0_opp>; 140 capacity-dmips-mhz = <1024>; 141 #cooling-cells = <2>; 142 }; 143 144 a57_1: cpu@1 { 145 compatible = "arm,cortex-a57"; 146 reg = <0x1>; 147 device_type = "cpu"; 148 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 149 next-level-cache = <&L2_CA57>; 150 enable-method = "psci"; 151 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 152 operating-points-v2 = <&cluster0_opp>; 153 capacity-dmips-mhz = <1024>; 154 #cooling-cells = <2>; 155 }; 156 157 a53_0: cpu@100 { 158 compatible = "arm,cortex-a53"; 159 reg = <0x100>; 160 device_type = "cpu"; 161 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 162 next-level-cache = <&L2_CA53>; 163 enable-method = "psci"; 164 #cooling-cells = <2>; 165 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 166 operating-points-v2 = <&cluster1_opp>; 167 capacity-dmips-mhz = <560>; 168 }; 169 170 a53_1: cpu@101 { 171 compatible = "arm,cortex-a53"; 172 reg = <0x101>; 173 device_type = "cpu"; 174 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 175 next-level-cache = <&L2_CA53>; 176 enable-method = "psci"; 177 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 178 operating-points-v2 = <&cluster1_opp>; 179 capacity-dmips-mhz = <560>; 180 }; 181 182 a53_2: cpu@102 { 183 compatible = "arm,cortex-a53"; 184 reg = <0x102>; 185 device_type = "cpu"; 186 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 187 next-level-cache = <&L2_CA53>; 188 enable-method = "psci"; 189 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 190 operating-points-v2 = <&cluster1_opp>; 191 capacity-dmips-mhz = <560>; 192 }; 193 194 a53_3: cpu@103 { 195 compatible = "arm,cortex-a53"; 196 reg = <0x103>; 197 device_type = "cpu"; 198 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 199 next-level-cache = <&L2_CA53>; 200 enable-method = "psci"; 201 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 202 operating-points-v2 = <&cluster1_opp>; 203 capacity-dmips-mhz = <560>; 204 }; 205 206 L2_CA57: cache-controller-0 { 207 compatible = "cache"; 208 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 209 cache-unified; 210 cache-level = <2>; 211 }; 212 213 L2_CA53: cache-controller-1 { 214 compatible = "cache"; 215 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 216 cache-unified; 217 cache-level = <2>; 218 }; 219 }; 220 221 extal_clk: extal { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 /* This value must be overridden by the board */ 225 clock-frequency = <0>; 226 }; 227 228 extalr_clk: extalr { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 /* This value must be overridden by the board */ 232 clock-frequency = <0>; 233 }; 234 235 /* External PCIe clock - can be overridden by the board */ 236 pcie_bus_clk: pcie_bus { 237 compatible = "fixed-clock"; 238 #clock-cells = <0>; 239 clock-frequency = <0>; 240 }; 241 242 pmu_a53 { 243 compatible = "arm,cortex-a53-pmu"; 244 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 245 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 246 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 247 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 249 }; 250 251 pmu_a57 { 252 compatible = "arm,cortex-a57-pmu"; 253 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 254 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-affinity = <&a57_0>, <&a57_1>; 256 }; 257 258 psci { 259 compatible = "arm,psci-1.0", "arm,psci-0.2"; 260 method = "smc"; 261 }; 262 263 /* External SCIF clock - to be overridden by boards that provide it */ 264 scif_clk: scif { 265 compatible = "fixed-clock"; 266 #clock-cells = <0>; 267 clock-frequency = <0>; 268 }; 269 270 soc { 271 compatible = "simple-bus"; 272 interrupt-parent = <&gic>; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 rwdt: watchdog@e6020000 { 278 compatible = "renesas,r8a774a1-wdt", 279 "renesas,rcar-gen3-wdt"; 280 reg = <0 0xe6020000 0 0x0c>; 281 clocks = <&cpg CPG_MOD 402>; 282 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 283 resets = <&cpg 402>; 284 status = "disabled"; 285 }; 286 287 gpio0: gpio@e6050000 { 288 compatible = "renesas,gpio-r8a774a1", 289 "renesas,rcar-gen3-gpio"; 290 reg = <0 0xe6050000 0 0x50>; 291 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 292 #gpio-cells = <2>; 293 gpio-controller; 294 gpio-ranges = <&pfc 0 0 16>; 295 #interrupt-cells = <2>; 296 interrupt-controller; 297 clocks = <&cpg CPG_MOD 912>; 298 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 299 resets = <&cpg 912>; 300 }; 301 302 gpio1: gpio@e6051000 { 303 compatible = "renesas,gpio-r8a774a1", 304 "renesas,rcar-gen3-gpio"; 305 reg = <0 0xe6051000 0 0x50>; 306 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 307 #gpio-cells = <2>; 308 gpio-controller; 309 gpio-ranges = <&pfc 0 32 29>; 310 #interrupt-cells = <2>; 311 interrupt-controller; 312 clocks = <&cpg CPG_MOD 911>; 313 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 314 resets = <&cpg 911>; 315 }; 316 317 gpio2: gpio@e6052000 { 318 compatible = "renesas,gpio-r8a774a1", 319 "renesas,rcar-gen3-gpio"; 320 reg = <0 0xe6052000 0 0x50>; 321 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 322 #gpio-cells = <2>; 323 gpio-controller; 324 gpio-ranges = <&pfc 0 64 15>; 325 #interrupt-cells = <2>; 326 interrupt-controller; 327 clocks = <&cpg CPG_MOD 910>; 328 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 329 resets = <&cpg 910>; 330 }; 331 332 gpio3: gpio@e6053000 { 333 compatible = "renesas,gpio-r8a774a1", 334 "renesas,rcar-gen3-gpio"; 335 reg = <0 0xe6053000 0 0x50>; 336 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 337 #gpio-cells = <2>; 338 gpio-controller; 339 gpio-ranges = <&pfc 0 96 16>; 340 #interrupt-cells = <2>; 341 interrupt-controller; 342 clocks = <&cpg CPG_MOD 909>; 343 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 344 resets = <&cpg 909>; 345 }; 346 347 gpio4: gpio@e6054000 { 348 compatible = "renesas,gpio-r8a774a1", 349 "renesas,rcar-gen3-gpio"; 350 reg = <0 0xe6054000 0 0x50>; 351 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 352 #gpio-cells = <2>; 353 gpio-controller; 354 gpio-ranges = <&pfc 0 128 18>; 355 #interrupt-cells = <2>; 356 interrupt-controller; 357 clocks = <&cpg CPG_MOD 908>; 358 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 359 resets = <&cpg 908>; 360 }; 361 362 gpio5: gpio@e6055000 { 363 compatible = "renesas,gpio-r8a774a1", 364 "renesas,rcar-gen3-gpio"; 365 reg = <0 0xe6055000 0 0x50>; 366 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 367 #gpio-cells = <2>; 368 gpio-controller; 369 gpio-ranges = <&pfc 0 160 26>; 370 #interrupt-cells = <2>; 371 interrupt-controller; 372 clocks = <&cpg CPG_MOD 907>; 373 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 374 resets = <&cpg 907>; 375 }; 376 377 gpio6: gpio@e6055400 { 378 compatible = "renesas,gpio-r8a774a1", 379 "renesas,rcar-gen3-gpio"; 380 reg = <0 0xe6055400 0 0x50>; 381 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 382 #gpio-cells = <2>; 383 gpio-controller; 384 gpio-ranges = <&pfc 0 192 32>; 385 #interrupt-cells = <2>; 386 interrupt-controller; 387 clocks = <&cpg CPG_MOD 906>; 388 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 389 resets = <&cpg 906>; 390 }; 391 392 gpio7: gpio@e6055800 { 393 compatible = "renesas,gpio-r8a774a1", 394 "renesas,rcar-gen3-gpio"; 395 reg = <0 0xe6055800 0 0x50>; 396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 397 #gpio-cells = <2>; 398 gpio-controller; 399 gpio-ranges = <&pfc 0 224 4>; 400 #interrupt-cells = <2>; 401 interrupt-controller; 402 clocks = <&cpg CPG_MOD 905>; 403 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 404 resets = <&cpg 905>; 405 }; 406 407 pfc: pin-controller@e6060000 { 408 compatible = "renesas,pfc-r8a774a1"; 409 reg = <0 0xe6060000 0 0x50c>; 410 }; 411 412 cmt0: timer@e60f0000 { 413 compatible = "renesas,r8a774a1-cmt0", 414 "renesas,rcar-gen3-cmt0"; 415 reg = <0 0xe60f0000 0 0x1004>; 416 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cpg CPG_MOD 303>; 419 clock-names = "fck"; 420 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 421 resets = <&cpg 303>; 422 status = "disabled"; 423 }; 424 425 cmt1: timer@e6130000 { 426 compatible = "renesas,r8a774a1-cmt1", 427 "renesas,rcar-gen3-cmt1"; 428 reg = <0 0xe6130000 0 0x1004>; 429 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cpg CPG_MOD 302>; 438 clock-names = "fck"; 439 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 440 resets = <&cpg 302>; 441 status = "disabled"; 442 }; 443 444 cmt2: timer@e6140000 { 445 compatible = "renesas,r8a774a1-cmt1", 446 "renesas,rcar-gen3-cmt1"; 447 reg = <0 0xe6140000 0 0x1004>; 448 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 301>; 457 clock-names = "fck"; 458 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 459 resets = <&cpg 301>; 460 status = "disabled"; 461 }; 462 463 cmt3: timer@e6148000 { 464 compatible = "renesas,r8a774a1-cmt1", 465 "renesas,rcar-gen3-cmt1"; 466 reg = <0 0xe6148000 0 0x1004>; 467 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&cpg CPG_MOD 300>; 476 clock-names = "fck"; 477 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 478 resets = <&cpg 300>; 479 status = "disabled"; 480 }; 481 482 cpg: clock-controller@e6150000 { 483 compatible = "renesas,r8a774a1-cpg-mssr"; 484 reg = <0 0xe6150000 0 0x0bb0>; 485 clocks = <&extal_clk>, <&extalr_clk>; 486 clock-names = "extal", "extalr"; 487 #clock-cells = <2>; 488 #power-domain-cells = <0>; 489 #reset-cells = <1>; 490 }; 491 492 rst: reset-controller@e6160000 { 493 compatible = "renesas,r8a774a1-rst"; 494 reg = <0 0xe6160000 0 0x018c>; 495 }; 496 497 sysc: system-controller@e6180000 { 498 compatible = "renesas,r8a774a1-sysc"; 499 reg = <0 0xe6180000 0 0x0400>; 500 #power-domain-cells = <1>; 501 }; 502 503 tsc: thermal@e6198000 { 504 compatible = "renesas,r8a774a1-thermal"; 505 reg = <0 0xe6198000 0 0x100>, 506 <0 0xe61a0000 0 0x100>, 507 <0 0xe61a8000 0 0x100>; 508 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cpg CPG_MOD 522>; 512 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 513 resets = <&cpg 522>; 514 #thermal-sensor-cells = <1>; 515 }; 516 517 intc_ex: interrupt-controller@e61c0000 { 518 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 519 #interrupt-cells = <2>; 520 interrupt-controller; 521 reg = <0 0xe61c0000 0 0x200>; 522 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 523 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 524 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 525 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 526 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 527 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&cpg CPG_MOD 407>; 529 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 530 resets = <&cpg 407>; 531 }; 532 533 tmu0: timer@e61e0000 { 534 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 535 reg = <0 0xe61e0000 0 0x30>; 536 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 125>; 540 clock-names = "fck"; 541 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 542 resets = <&cpg 125>; 543 status = "disabled"; 544 }; 545 546 tmu1: timer@e6fc0000 { 547 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 548 reg = <0 0xe6fc0000 0 0x30>; 549 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cpg CPG_MOD 124>; 553 clock-names = "fck"; 554 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 555 resets = <&cpg 124>; 556 status = "disabled"; 557 }; 558 559 tmu2: timer@e6fd0000 { 560 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 561 reg = <0 0xe6fd0000 0 0x30>; 562 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 123>; 566 clock-names = "fck"; 567 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 568 resets = <&cpg 123>; 569 status = "disabled"; 570 }; 571 572 tmu3: timer@e6fe0000 { 573 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 574 reg = <0 0xe6fe0000 0 0x30>; 575 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cpg CPG_MOD 122>; 579 clock-names = "fck"; 580 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 581 resets = <&cpg 122>; 582 status = "disabled"; 583 }; 584 585 tmu4: timer@ffc00000 { 586 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 587 reg = <0 0xffc00000 0 0x30>; 588 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cpg CPG_MOD 121>; 592 clock-names = "fck"; 593 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 594 resets = <&cpg 121>; 595 status = "disabled"; 596 }; 597 598 i2c0: i2c@e6500000 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 compatible = "renesas,i2c-r8a774a1", 602 "renesas,rcar-gen3-i2c"; 603 reg = <0 0xe6500000 0 0x40>; 604 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cpg CPG_MOD 931>; 606 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 607 resets = <&cpg 931>; 608 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 609 <&dmac2 0x91>, <&dmac2 0x90>; 610 dma-names = "tx", "rx", "tx", "rx"; 611 i2c-scl-internal-delay-ns = <110>; 612 status = "disabled"; 613 }; 614 615 i2c1: i2c@e6508000 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 compatible = "renesas,i2c-r8a774a1", 619 "renesas,rcar-gen3-i2c"; 620 reg = <0 0xe6508000 0 0x40>; 621 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&cpg CPG_MOD 930>; 623 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 624 resets = <&cpg 930>; 625 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 626 <&dmac2 0x93>, <&dmac2 0x92>; 627 dma-names = "tx", "rx", "tx", "rx"; 628 i2c-scl-internal-delay-ns = <6>; 629 status = "disabled"; 630 }; 631 632 i2c2: i2c@e6510000 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 compatible = "renesas,i2c-r8a774a1", 636 "renesas,rcar-gen3-i2c"; 637 reg = <0 0xe6510000 0 0x40>; 638 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cpg CPG_MOD 929>; 640 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 641 resets = <&cpg 929>; 642 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 643 <&dmac2 0x95>, <&dmac2 0x94>; 644 dma-names = "tx", "rx", "tx", "rx"; 645 i2c-scl-internal-delay-ns = <6>; 646 status = "disabled"; 647 }; 648 649 i2c3: i2c@e66d0000 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 compatible = "renesas,i2c-r8a774a1", 653 "renesas,rcar-gen3-i2c"; 654 reg = <0 0xe66d0000 0 0x40>; 655 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&cpg CPG_MOD 928>; 657 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 658 resets = <&cpg 928>; 659 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 660 dma-names = "tx", "rx"; 661 i2c-scl-internal-delay-ns = <110>; 662 status = "disabled"; 663 }; 664 665 i2c4: i2c@e66d8000 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 compatible = "renesas,i2c-r8a774a1", 669 "renesas,rcar-gen3-i2c"; 670 reg = <0 0xe66d8000 0 0x40>; 671 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cpg CPG_MOD 927>; 673 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 674 resets = <&cpg 927>; 675 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 676 dma-names = "tx", "rx"; 677 i2c-scl-internal-delay-ns = <110>; 678 status = "disabled"; 679 }; 680 681 i2c5: i2c@e66e0000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "renesas,i2c-r8a774a1", 685 "renesas,rcar-gen3-i2c"; 686 reg = <0 0xe66e0000 0 0x40>; 687 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cpg CPG_MOD 919>; 689 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 690 resets = <&cpg 919>; 691 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 692 dma-names = "tx", "rx"; 693 i2c-scl-internal-delay-ns = <110>; 694 status = "disabled"; 695 }; 696 697 i2c6: i2c@e66e8000 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 compatible = "renesas,i2c-r8a774a1", 701 "renesas,rcar-gen3-i2c"; 702 reg = <0 0xe66e8000 0 0x40>; 703 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cpg CPG_MOD 918>; 705 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 706 resets = <&cpg 918>; 707 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 708 dma-names = "tx", "rx"; 709 i2c-scl-internal-delay-ns = <6>; 710 status = "disabled"; 711 }; 712 713 i2c_dvfs: i2c@e60b0000 { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 compatible = "renesas,iic-r8a774a1", 717 "renesas,rcar-gen3-iic", 718 "renesas,rmobile-iic"; 719 reg = <0 0xe60b0000 0 0x425>; 720 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cpg CPG_MOD 926>; 722 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 723 resets = <&cpg 926>; 724 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 725 dma-names = "tx", "rx"; 726 status = "disabled"; 727 }; 728 729 hscif0: serial@e6540000 { 730 compatible = "renesas,hscif-r8a774a1", 731 "renesas,rcar-gen3-hscif", 732 "renesas,hscif"; 733 reg = <0 0xe6540000 0 0x60>; 734 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cpg CPG_MOD 520>, 736 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 737 <&scif_clk>; 738 clock-names = "fck", "brg_int", "scif_clk"; 739 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 740 <&dmac2 0x31>, <&dmac2 0x30>; 741 dma-names = "tx", "rx", "tx", "rx"; 742 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 743 resets = <&cpg 520>; 744 status = "disabled"; 745 }; 746 747 hscif1: serial@e6550000 { 748 compatible = "renesas,hscif-r8a774a1", 749 "renesas,rcar-gen3-hscif", 750 "renesas,hscif"; 751 reg = <0 0xe6550000 0 0x60>; 752 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cpg CPG_MOD 519>, 754 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 755 <&scif_clk>; 756 clock-names = "fck", "brg_int", "scif_clk"; 757 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 758 <&dmac2 0x33>, <&dmac2 0x32>; 759 dma-names = "tx", "rx", "tx", "rx"; 760 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 761 resets = <&cpg 519>; 762 status = "disabled"; 763 }; 764 765 hscif2: serial@e6560000 { 766 compatible = "renesas,hscif-r8a774a1", 767 "renesas,rcar-gen3-hscif", 768 "renesas,hscif"; 769 reg = <0 0xe6560000 0 0x60>; 770 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cpg CPG_MOD 518>, 772 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 773 <&scif_clk>; 774 clock-names = "fck", "brg_int", "scif_clk"; 775 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 776 <&dmac2 0x35>, <&dmac2 0x34>; 777 dma-names = "tx", "rx", "tx", "rx"; 778 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 779 resets = <&cpg 518>; 780 status = "disabled"; 781 }; 782 783 hscif3: serial@e66a0000 { 784 compatible = "renesas,hscif-r8a774a1", 785 "renesas,rcar-gen3-hscif", 786 "renesas,hscif"; 787 reg = <0 0xe66a0000 0 0x60>; 788 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&cpg CPG_MOD 517>, 790 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 791 <&scif_clk>; 792 clock-names = "fck", "brg_int", "scif_clk"; 793 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 794 dma-names = "tx", "rx"; 795 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 796 resets = <&cpg 517>; 797 status = "disabled"; 798 }; 799 800 hscif4: serial@e66b0000 { 801 compatible = "renesas,hscif-r8a774a1", 802 "renesas,rcar-gen3-hscif", 803 "renesas,hscif"; 804 reg = <0 0xe66b0000 0 0x60>; 805 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 516>, 807 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 808 <&scif_clk>; 809 clock-names = "fck", "brg_int", "scif_clk"; 810 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 811 dma-names = "tx", "rx"; 812 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 813 resets = <&cpg 516>; 814 status = "disabled"; 815 }; 816 817 hsusb: usb@e6590000 { 818 compatible = "renesas,usbhs-r8a774a1", 819 "renesas,rcar-gen3-usbhs"; 820 reg = <0 0xe6590000 0 0x200>; 821 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 823 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 824 <&usb_dmac1 0>, <&usb_dmac1 1>; 825 dma-names = "ch0", "ch1", "ch2", "ch3"; 826 renesas,buswait = <11>; 827 phys = <&usb2_phy0 3>; 828 phy-names = "usb"; 829 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 830 resets = <&cpg 704>, <&cpg 703>; 831 status = "disabled"; 832 }; 833 834 usb_dmac0: dma-controller@e65a0000 { 835 compatible = "renesas,r8a774a1-usb-dmac", 836 "renesas,usb-dmac"; 837 reg = <0 0xe65a0000 0 0x100>; 838 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 839 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "ch0", "ch1"; 841 clocks = <&cpg CPG_MOD 330>; 842 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 843 resets = <&cpg 330>; 844 #dma-cells = <1>; 845 dma-channels = <2>; 846 }; 847 848 usb_dmac1: dma-controller@e65b0000 { 849 compatible = "renesas,r8a774a1-usb-dmac", 850 "renesas,usb-dmac"; 851 reg = <0 0xe65b0000 0 0x100>; 852 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 853 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 854 interrupt-names = "ch0", "ch1"; 855 clocks = <&cpg CPG_MOD 331>; 856 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 857 resets = <&cpg 331>; 858 #dma-cells = <1>; 859 dma-channels = <2>; 860 }; 861 862 usb3_phy0: usb-phy@e65ee000 { 863 compatible = "renesas,r8a774a1-usb3-phy", 864 "renesas,rcar-gen3-usb3-phy"; 865 reg = <0 0xe65ee000 0 0x90>; 866 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 867 <&usb_extal_clk>; 868 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 869 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 870 resets = <&cpg 328>; 871 #phy-cells = <0>; 872 status = "disabled"; 873 }; 874 875 dmac0: dma-controller@e6700000 { 876 compatible = "renesas,dmac-r8a774a1", 877 "renesas,rcar-dmac"; 878 reg = <0 0xe6700000 0 0x10000>; 879 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 880 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 881 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 882 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 883 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 884 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 885 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 886 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 887 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 888 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 889 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 890 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 891 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 892 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 893 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 894 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 895 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 896 interrupt-names = "error", 897 "ch0", "ch1", "ch2", "ch3", 898 "ch4", "ch5", "ch6", "ch7", 899 "ch8", "ch9", "ch10", "ch11", 900 "ch12", "ch13", "ch14", "ch15"; 901 clocks = <&cpg CPG_MOD 219>; 902 clock-names = "fck"; 903 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 904 resets = <&cpg 219>; 905 #dma-cells = <1>; 906 dma-channels = <16>; 907 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 908 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 909 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 910 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 911 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 912 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 913 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 914 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 915 }; 916 917 dmac1: dma-controller@e7300000 { 918 compatible = "renesas,dmac-r8a774a1", 919 "renesas,rcar-dmac"; 920 reg = <0 0xe7300000 0 0x10000>; 921 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 922 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 923 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 924 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 925 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 926 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 927 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 928 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 929 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 930 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 931 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 932 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 933 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 934 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 935 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 936 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 937 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 938 interrupt-names = "error", 939 "ch0", "ch1", "ch2", "ch3", 940 "ch4", "ch5", "ch6", "ch7", 941 "ch8", "ch9", "ch10", "ch11", 942 "ch12", "ch13", "ch14", "ch15"; 943 clocks = <&cpg CPG_MOD 218>; 944 clock-names = "fck"; 945 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 946 resets = <&cpg 218>; 947 #dma-cells = <1>; 948 dma-channels = <16>; 949 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 950 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 951 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 952 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 953 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 954 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 955 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 956 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 957 }; 958 959 dmac2: dma-controller@e7310000 { 960 compatible = "renesas,dmac-r8a774a1", 961 "renesas,rcar-dmac"; 962 reg = <0 0xe7310000 0 0x10000>; 963 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 964 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 965 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 966 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 967 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 968 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 969 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 970 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 971 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 972 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 973 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 974 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 975 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 976 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 977 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 978 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 979 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-names = "error", 981 "ch0", "ch1", "ch2", "ch3", 982 "ch4", "ch5", "ch6", "ch7", 983 "ch8", "ch9", "ch10", "ch11", 984 "ch12", "ch13", "ch14", "ch15"; 985 clocks = <&cpg CPG_MOD 217>; 986 clock-names = "fck"; 987 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 988 resets = <&cpg 217>; 989 #dma-cells = <1>; 990 dma-channels = <16>; 991 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 992 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 993 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 994 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 995 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 996 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 997 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 998 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 999 }; 1000 1001 ipmmu_ds0: mmu@e6740000 { 1002 compatible = "renesas,ipmmu-r8a774a1"; 1003 reg = <0 0xe6740000 0 0x1000>; 1004 renesas,ipmmu-main = <&ipmmu_mm 0>; 1005 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1006 #iommu-cells = <1>; 1007 }; 1008 1009 ipmmu_ds1: mmu@e7740000 { 1010 compatible = "renesas,ipmmu-r8a774a1"; 1011 reg = <0 0xe7740000 0 0x1000>; 1012 renesas,ipmmu-main = <&ipmmu_mm 1>; 1013 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1014 #iommu-cells = <1>; 1015 }; 1016 1017 ipmmu_hc: mmu@e6570000 { 1018 compatible = "renesas,ipmmu-r8a774a1"; 1019 reg = <0 0xe6570000 0 0x1000>; 1020 renesas,ipmmu-main = <&ipmmu_mm 2>; 1021 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1022 #iommu-cells = <1>; 1023 }; 1024 1025 ipmmu_mm: mmu@e67b0000 { 1026 compatible = "renesas,ipmmu-r8a774a1"; 1027 reg = <0 0xe67b0000 0 0x1000>; 1028 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1030 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1031 #iommu-cells = <1>; 1032 }; 1033 1034 ipmmu_mp: mmu@ec670000 { 1035 compatible = "renesas,ipmmu-r8a774a1"; 1036 reg = <0 0xec670000 0 0x1000>; 1037 renesas,ipmmu-main = <&ipmmu_mm 4>; 1038 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1039 #iommu-cells = <1>; 1040 }; 1041 1042 ipmmu_pv0: mmu@fd800000 { 1043 compatible = "renesas,ipmmu-r8a774a1"; 1044 reg = <0 0xfd800000 0 0x1000>; 1045 renesas,ipmmu-main = <&ipmmu_mm 5>; 1046 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1047 #iommu-cells = <1>; 1048 }; 1049 1050 ipmmu_pv1: mmu@fd950000 { 1051 compatible = "renesas,ipmmu-r8a774a1"; 1052 reg = <0 0xfd950000 0 0x1000>; 1053 renesas,ipmmu-main = <&ipmmu_mm 6>; 1054 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1055 #iommu-cells = <1>; 1056 }; 1057 1058 ipmmu_vc0: mmu@fe6b0000 { 1059 compatible = "renesas,ipmmu-r8a774a1"; 1060 reg = <0 0xfe6b0000 0 0x1000>; 1061 renesas,ipmmu-main = <&ipmmu_mm 8>; 1062 power-domains = <&sysc R8A774A1_PD_A3VC>; 1063 #iommu-cells = <1>; 1064 }; 1065 1066 ipmmu_vi0: mmu@febd0000 { 1067 compatible = "renesas,ipmmu-r8a774a1"; 1068 reg = <0 0xfebd0000 0 0x1000>; 1069 renesas,ipmmu-main = <&ipmmu_mm 9>; 1070 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1071 #iommu-cells = <1>; 1072 }; 1073 1074 avb: ethernet@e6800000 { 1075 compatible = "renesas,etheravb-r8a774a1", 1076 "renesas,etheravb-rcar-gen3"; 1077 reg = <0 0xe6800000 0 0x800>; 1078 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1103 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1104 "ch4", "ch5", "ch6", "ch7", 1105 "ch8", "ch9", "ch10", "ch11", 1106 "ch12", "ch13", "ch14", "ch15", 1107 "ch16", "ch17", "ch18", "ch19", 1108 "ch20", "ch21", "ch22", "ch23", 1109 "ch24"; 1110 clocks = <&cpg CPG_MOD 812>; 1111 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1112 resets = <&cpg 812>; 1113 phy-mode = "rgmii"; 1114 iommus = <&ipmmu_ds0 16>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 can0: can@e6c30000 { 1121 compatible = "renesas,can-r8a774a1", 1122 "renesas,rcar-gen3-can"; 1123 reg = <0 0xe6c30000 0 0x1000>; 1124 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cpg CPG_MOD 916>, 1126 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1127 <&can_clk>; 1128 clock-names = "clkp1", "clkp2", "can_clk"; 1129 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1130 resets = <&cpg 916>; 1131 status = "disabled"; 1132 }; 1133 1134 can1: can@e6c38000 { 1135 compatible = "renesas,can-r8a774a1", 1136 "renesas,rcar-gen3-can"; 1137 reg = <0 0xe6c38000 0 0x1000>; 1138 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&cpg CPG_MOD 915>, 1140 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1141 <&can_clk>; 1142 clock-names = "clkp1", "clkp2", "can_clk"; 1143 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1144 resets = <&cpg 915>; 1145 status = "disabled"; 1146 }; 1147 1148 pwm0: pwm@e6e30000 { 1149 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1150 reg = <0 0xe6e30000 0 0x8>; 1151 #pwm-cells = <2>; 1152 clocks = <&cpg CPG_MOD 523>; 1153 resets = <&cpg 523>; 1154 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1155 status = "disabled"; 1156 }; 1157 1158 pwm1: pwm@e6e31000 { 1159 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1160 reg = <0 0xe6e31000 0 0x8>; 1161 #pwm-cells = <2>; 1162 clocks = <&cpg CPG_MOD 523>; 1163 resets = <&cpg 523>; 1164 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1165 status = "disabled"; 1166 }; 1167 1168 pwm2: pwm@e6e32000 { 1169 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1170 reg = <0 0xe6e32000 0 0x8>; 1171 #pwm-cells = <2>; 1172 clocks = <&cpg CPG_MOD 523>; 1173 resets = <&cpg 523>; 1174 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1175 status = "disabled"; 1176 }; 1177 1178 pwm3: pwm@e6e33000 { 1179 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1180 reg = <0 0xe6e33000 0 0x8>; 1181 #pwm-cells = <2>; 1182 clocks = <&cpg CPG_MOD 523>; 1183 resets = <&cpg 523>; 1184 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1185 status = "disabled"; 1186 }; 1187 1188 pwm4: pwm@e6e34000 { 1189 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1190 reg = <0 0xe6e34000 0 0x8>; 1191 #pwm-cells = <2>; 1192 clocks = <&cpg CPG_MOD 523>; 1193 resets = <&cpg 523>; 1194 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1195 status = "disabled"; 1196 }; 1197 1198 pwm5: pwm@e6e35000 { 1199 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1200 reg = <0 0xe6e35000 0 0x8>; 1201 #pwm-cells = <2>; 1202 clocks = <&cpg CPG_MOD 523>; 1203 resets = <&cpg 523>; 1204 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1205 status = "disabled"; 1206 }; 1207 1208 pwm6: pwm@e6e36000 { 1209 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1210 reg = <0 0xe6e36000 0 0x8>; 1211 #pwm-cells = <2>; 1212 clocks = <&cpg CPG_MOD 523>; 1213 resets = <&cpg 523>; 1214 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1215 status = "disabled"; 1216 }; 1217 1218 scif0: serial@e6e60000 { 1219 compatible = "renesas,scif-r8a774a1", 1220 "renesas,rcar-gen3-scif", "renesas,scif"; 1221 reg = <0 0xe6e60000 0 0x40>; 1222 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&cpg CPG_MOD 207>, 1224 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1225 <&scif_clk>; 1226 clock-names = "fck", "brg_int", "scif_clk"; 1227 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1228 <&dmac2 0x51>, <&dmac2 0x50>; 1229 dma-names = "tx", "rx", "tx", "rx"; 1230 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1231 resets = <&cpg 207>; 1232 status = "disabled"; 1233 }; 1234 1235 scif1: serial@e6e68000 { 1236 compatible = "renesas,scif-r8a774a1", 1237 "renesas,rcar-gen3-scif", "renesas,scif"; 1238 reg = <0 0xe6e68000 0 0x40>; 1239 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&cpg CPG_MOD 206>, 1241 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1242 <&scif_clk>; 1243 clock-names = "fck", "brg_int", "scif_clk"; 1244 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1245 <&dmac2 0x53>, <&dmac2 0x52>; 1246 dma-names = "tx", "rx", "tx", "rx"; 1247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1248 resets = <&cpg 206>; 1249 status = "disabled"; 1250 }; 1251 1252 scif2: serial@e6e88000 { 1253 compatible = "renesas,scif-r8a774a1", 1254 "renesas,rcar-gen3-scif", "renesas,scif"; 1255 reg = <0 0xe6e88000 0 0x40>; 1256 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cpg CPG_MOD 310>, 1258 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1259 <&scif_clk>; 1260 clock-names = "fck", "brg_int", "scif_clk"; 1261 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1262 <&dmac2 0x13>, <&dmac2 0x12>; 1263 dma-names = "tx", "rx", "tx", "rx"; 1264 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1265 resets = <&cpg 310>; 1266 status = "disabled"; 1267 }; 1268 1269 scif3: serial@e6c50000 { 1270 compatible = "renesas,scif-r8a774a1", 1271 "renesas,rcar-gen3-scif", "renesas,scif"; 1272 reg = <0 0xe6c50000 0 0x40>; 1273 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&cpg CPG_MOD 204>, 1275 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1276 <&scif_clk>; 1277 clock-names = "fck", "brg_int", "scif_clk"; 1278 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1279 dma-names = "tx", "rx"; 1280 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1281 resets = <&cpg 204>; 1282 status = "disabled"; 1283 }; 1284 1285 scif4: serial@e6c40000 { 1286 compatible = "renesas,scif-r8a774a1", 1287 "renesas,rcar-gen3-scif", "renesas,scif"; 1288 reg = <0 0xe6c40000 0 0x40>; 1289 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1290 clocks = <&cpg CPG_MOD 203>, 1291 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1292 <&scif_clk>; 1293 clock-names = "fck", "brg_int", "scif_clk"; 1294 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1295 dma-names = "tx", "rx"; 1296 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1297 resets = <&cpg 203>; 1298 status = "disabled"; 1299 }; 1300 1301 scif5: serial@e6f30000 { 1302 compatible = "renesas,scif-r8a774a1", 1303 "renesas,rcar-gen3-scif", "renesas,scif"; 1304 reg = <0 0xe6f30000 0 0x40>; 1305 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&cpg CPG_MOD 202>, 1307 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1308 <&scif_clk>; 1309 clock-names = "fck", "brg_int", "scif_clk"; 1310 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1311 <&dmac2 0x5b>, <&dmac2 0x5a>; 1312 dma-names = "tx", "rx", "tx", "rx"; 1313 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1314 resets = <&cpg 202>; 1315 status = "disabled"; 1316 }; 1317 1318 msiof0: spi@e6e90000 { 1319 compatible = "renesas,msiof-r8a774a1", 1320 "renesas,rcar-gen3-msiof"; 1321 reg = <0 0xe6e90000 0 0x0064>; 1322 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&cpg CPG_MOD 211>; 1324 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1325 <&dmac2 0x41>, <&dmac2 0x40>; 1326 dma-names = "tx", "rx", "tx", "rx"; 1327 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1328 resets = <&cpg 211>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 msiof1: spi@e6ea0000 { 1335 compatible = "renesas,msiof-r8a774a1", 1336 "renesas,rcar-gen3-msiof"; 1337 reg = <0 0xe6ea0000 0 0x0064>; 1338 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&cpg CPG_MOD 210>; 1340 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1341 <&dmac2 0x43>, <&dmac2 0x42>; 1342 dma-names = "tx", "rx", "tx", "rx"; 1343 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1344 resets = <&cpg 210>; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 status = "disabled"; 1348 }; 1349 1350 msiof2: spi@e6c00000 { 1351 compatible = "renesas,msiof-r8a774a1", 1352 "renesas,rcar-gen3-msiof"; 1353 reg = <0 0xe6c00000 0 0x0064>; 1354 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&cpg CPG_MOD 209>; 1356 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1357 dma-names = "tx", "rx"; 1358 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1359 resets = <&cpg 209>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 msiof3: spi@e6c10000 { 1366 compatible = "renesas,msiof-r8a774a1", 1367 "renesas,rcar-gen3-msiof"; 1368 reg = <0 0xe6c10000 0 0x0064>; 1369 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&cpg CPG_MOD 208>; 1371 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1372 dma-names = "tx", "rx"; 1373 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1374 resets = <&cpg 208>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 vin0: video@e6ef0000 { 1381 compatible = "renesas,vin-r8a774a1"; 1382 reg = <0 0xe6ef0000 0 0x1000>; 1383 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&cpg CPG_MOD 811>; 1385 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1386 resets = <&cpg 811>; 1387 renesas,id = <0>; 1388 status = "disabled"; 1389 1390 ports { 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 1394 port@1 { 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 1398 reg = <1>; 1399 1400 vin0csi20: endpoint@0 { 1401 reg = <0>; 1402 remote-endpoint = <&csi20vin0>; 1403 }; 1404 vin0csi40: endpoint@2 { 1405 reg = <2>; 1406 remote-endpoint = <&csi40vin0>; 1407 }; 1408 }; 1409 }; 1410 }; 1411 1412 vin1: video@e6ef1000 { 1413 compatible = "renesas,vin-r8a774a1"; 1414 reg = <0 0xe6ef1000 0 0x1000>; 1415 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1416 clocks = <&cpg CPG_MOD 810>; 1417 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1418 resets = <&cpg 810>; 1419 renesas,id = <1>; 1420 status = "disabled"; 1421 1422 ports { 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 port@1 { 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 1430 reg = <1>; 1431 1432 vin1csi20: endpoint@0 { 1433 reg = <0>; 1434 remote-endpoint = <&csi20vin1>; 1435 }; 1436 vin1csi40: endpoint@2 { 1437 reg = <2>; 1438 remote-endpoint = <&csi40vin1>; 1439 }; 1440 }; 1441 }; 1442 }; 1443 1444 vin2: video@e6ef2000 { 1445 compatible = "renesas,vin-r8a774a1"; 1446 reg = <0 0xe6ef2000 0 0x1000>; 1447 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1448 clocks = <&cpg CPG_MOD 809>; 1449 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1450 resets = <&cpg 809>; 1451 renesas,id = <2>; 1452 status = "disabled"; 1453 1454 ports { 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 1458 port@1 { 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 1462 reg = <1>; 1463 1464 vin2csi20: endpoint@0 { 1465 reg = <0>; 1466 remote-endpoint = <&csi20vin2>; 1467 }; 1468 vin2csi40: endpoint@2 { 1469 reg = <2>; 1470 remote-endpoint = <&csi40vin2>; 1471 }; 1472 }; 1473 }; 1474 }; 1475 1476 vin3: video@e6ef3000 { 1477 compatible = "renesas,vin-r8a774a1"; 1478 reg = <0 0xe6ef3000 0 0x1000>; 1479 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1480 clocks = <&cpg CPG_MOD 808>; 1481 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1482 resets = <&cpg 808>; 1483 renesas,id = <3>; 1484 status = "disabled"; 1485 1486 ports { 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 1490 port@1 { 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 1494 reg = <1>; 1495 1496 vin3csi20: endpoint@0 { 1497 reg = <0>; 1498 remote-endpoint = <&csi20vin3>; 1499 }; 1500 vin3csi40: endpoint@2 { 1501 reg = <2>; 1502 remote-endpoint = <&csi40vin3>; 1503 }; 1504 }; 1505 }; 1506 }; 1507 1508 vin4: video@e6ef4000 { 1509 compatible = "renesas,vin-r8a774a1"; 1510 reg = <0 0xe6ef4000 0 0x1000>; 1511 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1512 clocks = <&cpg CPG_MOD 807>; 1513 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1514 resets = <&cpg 807>; 1515 renesas,id = <4>; 1516 status = "disabled"; 1517 1518 ports { 1519 #address-cells = <1>; 1520 #size-cells = <0>; 1521 1522 port@1 { 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 1526 reg = <1>; 1527 1528 vin4csi20: endpoint@0 { 1529 reg = <0>; 1530 remote-endpoint = <&csi20vin4>; 1531 }; 1532 vin4csi40: endpoint@2 { 1533 reg = <2>; 1534 remote-endpoint = <&csi40vin4>; 1535 }; 1536 }; 1537 }; 1538 }; 1539 1540 vin5: video@e6ef5000 { 1541 compatible = "renesas,vin-r8a774a1"; 1542 reg = <0 0xe6ef5000 0 0x1000>; 1543 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&cpg CPG_MOD 806>; 1545 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1546 resets = <&cpg 806>; 1547 renesas,id = <5>; 1548 status = "disabled"; 1549 1550 ports { 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 1554 port@1 { 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 1558 reg = <1>; 1559 1560 vin5csi20: endpoint@0 { 1561 reg = <0>; 1562 remote-endpoint = <&csi20vin5>; 1563 }; 1564 vin5csi40: endpoint@2 { 1565 reg = <2>; 1566 remote-endpoint = <&csi40vin5>; 1567 }; 1568 }; 1569 }; 1570 }; 1571 1572 vin6: video@e6ef6000 { 1573 compatible = "renesas,vin-r8a774a1"; 1574 reg = <0 0xe6ef6000 0 0x1000>; 1575 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1576 clocks = <&cpg CPG_MOD 805>; 1577 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1578 resets = <&cpg 805>; 1579 renesas,id = <6>; 1580 status = "disabled"; 1581 1582 ports { 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 1586 port@1 { 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 1590 reg = <1>; 1591 1592 vin6csi20: endpoint@0 { 1593 reg = <0>; 1594 remote-endpoint = <&csi20vin6>; 1595 }; 1596 vin6csi40: endpoint@2 { 1597 reg = <2>; 1598 remote-endpoint = <&csi40vin6>; 1599 }; 1600 }; 1601 }; 1602 }; 1603 1604 vin7: video@e6ef7000 { 1605 compatible = "renesas,vin-r8a774a1"; 1606 reg = <0 0xe6ef7000 0 0x1000>; 1607 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1608 clocks = <&cpg CPG_MOD 804>; 1609 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1610 resets = <&cpg 804>; 1611 renesas,id = <7>; 1612 status = "disabled"; 1613 1614 ports { 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 1618 port@1 { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 reg = <1>; 1623 1624 vin7csi20: endpoint@0 { 1625 reg = <0>; 1626 remote-endpoint = <&csi20vin7>; 1627 }; 1628 vin7csi40: endpoint@2 { 1629 reg = <2>; 1630 remote-endpoint = <&csi40vin7>; 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 rcar_sound: sound@ec500000 { 1637 /* 1638 * #sound-dai-cells is required 1639 * 1640 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1641 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1642 */ 1643 /* 1644 * #clock-cells is required for audio_clkout0/1/2/3 1645 * 1646 * clkout : #clock-cells = <0>; <&rcar_sound>; 1647 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1648 */ 1649 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1650 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1651 <0 0xec5a0000 0 0x100>, /* ADG */ 1652 <0 0xec540000 0 0x1000>, /* SSIU */ 1653 <0 0xec541000 0 0x280>, /* SSI */ 1654 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1655 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1656 1657 clocks = <&cpg CPG_MOD 1005>, 1658 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1659 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1660 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1661 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1662 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1663 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1664 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1665 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1666 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1667 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1668 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1669 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1670 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1671 <&audio_clk_a>, <&audio_clk_b>, 1672 <&audio_clk_c>, 1673 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1674 clock-names = "ssi-all", 1675 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1676 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1677 "ssi.1", "ssi.0", 1678 "src.9", "src.8", "src.7", "src.6", 1679 "src.5", "src.4", "src.3", "src.2", 1680 "src.1", "src.0", 1681 "mix.1", "mix.0", 1682 "ctu.1", "ctu.0", 1683 "dvc.0", "dvc.1", 1684 "clk_a", "clk_b", "clk_c", "clk_i"; 1685 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1686 resets = <&cpg 1005>, 1687 <&cpg 1006>, <&cpg 1007>, 1688 <&cpg 1008>, <&cpg 1009>, 1689 <&cpg 1010>, <&cpg 1011>, 1690 <&cpg 1012>, <&cpg 1013>, 1691 <&cpg 1014>, <&cpg 1015>; 1692 reset-names = "ssi-all", 1693 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1694 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1695 "ssi.1", "ssi.0"; 1696 status = "disabled"; 1697 1698 rcar_sound,dvc { 1699 dvc0: dvc-0 { 1700 dmas = <&audma1 0xbc>; 1701 dma-names = "tx"; 1702 }; 1703 dvc1: dvc-1 { 1704 dmas = <&audma1 0xbe>; 1705 dma-names = "tx"; 1706 }; 1707 }; 1708 1709 rcar_sound,mix { 1710 mix0: mix-0 { }; 1711 mix1: mix-1 { }; 1712 }; 1713 1714 rcar_sound,ctu { 1715 ctu00: ctu-0 { }; 1716 ctu01: ctu-1 { }; 1717 ctu02: ctu-2 { }; 1718 ctu03: ctu-3 { }; 1719 ctu10: ctu-4 { }; 1720 ctu11: ctu-5 { }; 1721 ctu12: ctu-6 { }; 1722 ctu13: ctu-7 { }; 1723 }; 1724 1725 rcar_sound,src { 1726 src0: src-0 { 1727 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1728 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1729 dma-names = "rx", "tx"; 1730 }; 1731 src1: src-1 { 1732 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1733 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1734 dma-names = "rx", "tx"; 1735 }; 1736 src2: src-2 { 1737 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1738 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1739 dma-names = "rx", "tx"; 1740 }; 1741 src3: src-3 { 1742 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1743 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1744 dma-names = "rx", "tx"; 1745 }; 1746 src4: src-4 { 1747 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1748 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1749 dma-names = "rx", "tx"; 1750 }; 1751 src5: src-5 { 1752 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1753 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1754 dma-names = "rx", "tx"; 1755 }; 1756 src6: src-6 { 1757 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1758 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1759 dma-names = "rx", "tx"; 1760 }; 1761 src7: src-7 { 1762 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1763 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1764 dma-names = "rx", "tx"; 1765 }; 1766 src8: src-8 { 1767 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1768 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1769 dma-names = "rx", "tx"; 1770 }; 1771 src9: src-9 { 1772 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1773 dmas = <&audma0 0x97>, <&audma1 0xba>; 1774 dma-names = "rx", "tx"; 1775 }; 1776 }; 1777 1778 rcar_sound,ssi { 1779 ssi0: ssi-0 { 1780 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1781 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1782 dma-names = "rx", "tx", "rxu", "txu"; 1783 }; 1784 ssi1: ssi-1 { 1785 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1786 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1787 dma-names = "rx", "tx", "rxu", "txu"; 1788 }; 1789 ssi2: ssi-2 { 1790 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1791 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1792 dma-names = "rx", "tx", "rxu", "txu"; 1793 }; 1794 ssi3: ssi-3 { 1795 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1796 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1797 dma-names = "rx", "tx", "rxu", "txu"; 1798 }; 1799 ssi4: ssi-4 { 1800 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1801 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1802 dma-names = "rx", "tx", "rxu", "txu"; 1803 }; 1804 ssi5: ssi-5 { 1805 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1806 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1807 dma-names = "rx", "tx", "rxu", "txu"; 1808 }; 1809 ssi6: ssi-6 { 1810 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1811 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1812 dma-names = "rx", "tx", "rxu", "txu"; 1813 }; 1814 ssi7: ssi-7 { 1815 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1816 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1817 dma-names = "rx", "tx", "rxu", "txu"; 1818 }; 1819 ssi8: ssi-8 { 1820 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1821 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1822 dma-names = "rx", "tx", "rxu", "txu"; 1823 }; 1824 ssi9: ssi-9 { 1825 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1826 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1827 dma-names = "rx", "tx", "rxu", "txu"; 1828 }; 1829 }; 1830 1831 ports { 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 port@0 { 1835 reg = <0>; 1836 }; 1837 port@1 { 1838 reg = <1>; 1839 }; 1840 }; 1841 }; 1842 1843 audma0: dma-controller@ec700000 { 1844 compatible = "renesas,dmac-r8a774a1", 1845 "renesas,rcar-dmac"; 1846 reg = <0 0xec700000 0 0x10000>; 1847 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1848 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1849 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1850 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1851 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1852 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1853 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1854 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1855 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1856 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1857 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1858 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1859 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1860 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1861 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1862 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1863 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1864 interrupt-names = "error", 1865 "ch0", "ch1", "ch2", "ch3", 1866 "ch4", "ch5", "ch6", "ch7", 1867 "ch8", "ch9", "ch10", "ch11", 1868 "ch12", "ch13", "ch14", "ch15"; 1869 clocks = <&cpg CPG_MOD 502>; 1870 clock-names = "fck"; 1871 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1872 resets = <&cpg 502>; 1873 #dma-cells = <1>; 1874 dma-channels = <16>; 1875 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1876 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1877 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1878 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1879 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1880 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1881 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1882 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1883 }; 1884 1885 audma1: dma-controller@ec720000 { 1886 compatible = "renesas,dmac-r8a774a1", 1887 "renesas,rcar-dmac"; 1888 reg = <0 0xec720000 0 0x10000>; 1889 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1890 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1891 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1892 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1893 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1894 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1895 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1896 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1897 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1898 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1899 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1900 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1901 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1902 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1903 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1904 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1905 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1906 interrupt-names = "error", 1907 "ch0", "ch1", "ch2", "ch3", 1908 "ch4", "ch5", "ch6", "ch7", 1909 "ch8", "ch9", "ch10", "ch11", 1910 "ch12", "ch13", "ch14", "ch15"; 1911 clocks = <&cpg CPG_MOD 501>; 1912 clock-names = "fck"; 1913 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1914 resets = <&cpg 501>; 1915 #dma-cells = <1>; 1916 dma-channels = <16>; 1917 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1918 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1919 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1920 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1921 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1922 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1923 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1924 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1925 }; 1926 1927 xhci0: usb@ee000000 { 1928 compatible = "renesas,xhci-r8a774a1", 1929 "renesas,rcar-gen3-xhci"; 1930 reg = <0 0xee000000 0 0xc00>; 1931 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1932 clocks = <&cpg CPG_MOD 328>; 1933 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1934 resets = <&cpg 328>; 1935 status = "disabled"; 1936 }; 1937 1938 usb3_peri0: usb@ee020000 { 1939 compatible = "renesas,r8a774a1-usb3-peri", 1940 "renesas,rcar-gen3-usb3-peri"; 1941 reg = <0 0xee020000 0 0x400>; 1942 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1943 clocks = <&cpg CPG_MOD 328>; 1944 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1945 resets = <&cpg 328>; 1946 status = "disabled"; 1947 }; 1948 1949 ohci0: usb@ee080000 { 1950 compatible = "generic-ohci"; 1951 reg = <0 0xee080000 0 0x100>; 1952 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1953 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1954 phys = <&usb2_phy0 1>; 1955 phy-names = "usb"; 1956 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1957 resets = <&cpg 703>, <&cpg 704>; 1958 status = "disabled"; 1959 }; 1960 1961 ohci1: usb@ee0a0000 { 1962 compatible = "generic-ohci"; 1963 reg = <0 0xee0a0000 0 0x100>; 1964 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1965 clocks = <&cpg CPG_MOD 702>; 1966 phys = <&usb2_phy1 1>; 1967 phy-names = "usb"; 1968 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1969 resets = <&cpg 702>; 1970 status = "disabled"; 1971 }; 1972 1973 ehci0: usb@ee080100 { 1974 compatible = "generic-ehci"; 1975 reg = <0 0xee080100 0 0x100>; 1976 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1977 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1978 phys = <&usb2_phy0 2>; 1979 phy-names = "usb"; 1980 companion = <&ohci0>; 1981 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1982 resets = <&cpg 703>, <&cpg 704>; 1983 status = "disabled"; 1984 }; 1985 1986 ehci1: usb@ee0a0100 { 1987 compatible = "generic-ehci"; 1988 reg = <0 0xee0a0100 0 0x100>; 1989 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1990 clocks = <&cpg CPG_MOD 702>; 1991 phys = <&usb2_phy1 2>; 1992 phy-names = "usb"; 1993 companion = <&ohci1>; 1994 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1995 resets = <&cpg 702>; 1996 status = "disabled"; 1997 }; 1998 1999 usb2_phy0: usb-phy@ee080200 { 2000 compatible = "renesas,usb2-phy-r8a774a1", 2001 "renesas,rcar-gen3-usb2-phy"; 2002 reg = <0 0xee080200 0 0x700>; 2003 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2004 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2005 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2006 resets = <&cpg 703>, <&cpg 704>; 2007 #phy-cells = <1>; 2008 status = "disabled"; 2009 }; 2010 2011 usb2_phy1: usb-phy@ee0a0200 { 2012 compatible = "renesas,usb2-phy-r8a774a1", 2013 "renesas,rcar-gen3-usb2-phy"; 2014 reg = <0 0xee0a0200 0 0x700>; 2015 clocks = <&cpg CPG_MOD 702>; 2016 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2017 resets = <&cpg 702>; 2018 #phy-cells = <1>; 2019 status = "disabled"; 2020 }; 2021 2022 sdhi0: sd@ee100000 { 2023 compatible = "renesas,sdhi-r8a774a1", 2024 "renesas,rcar-gen3-sdhi"; 2025 reg = <0 0xee100000 0 0x2000>; 2026 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2027 clocks = <&cpg CPG_MOD 314>; 2028 max-frequency = <200000000>; 2029 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2030 resets = <&cpg 314>; 2031 status = "disabled"; 2032 }; 2033 2034 sdhi1: sd@ee120000 { 2035 compatible = "renesas,sdhi-r8a774a1", 2036 "renesas,rcar-gen3-sdhi"; 2037 reg = <0 0xee120000 0 0x2000>; 2038 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2039 clocks = <&cpg CPG_MOD 313>; 2040 max-frequency = <200000000>; 2041 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2042 resets = <&cpg 313>; 2043 status = "disabled"; 2044 }; 2045 2046 sdhi2: sd@ee140000 { 2047 compatible = "renesas,sdhi-r8a774a1", 2048 "renesas,rcar-gen3-sdhi"; 2049 reg = <0 0xee140000 0 0x2000>; 2050 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2051 clocks = <&cpg CPG_MOD 312>; 2052 max-frequency = <200000000>; 2053 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2054 resets = <&cpg 312>; 2055 status = "disabled"; 2056 }; 2057 2058 sdhi3: sd@ee160000 { 2059 compatible = "renesas,sdhi-r8a774a1", 2060 "renesas,rcar-gen3-sdhi"; 2061 reg = <0 0xee160000 0 0x2000>; 2062 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2063 clocks = <&cpg CPG_MOD 311>; 2064 max-frequency = <200000000>; 2065 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2066 resets = <&cpg 311>; 2067 status = "disabled"; 2068 }; 2069 2070 gic: interrupt-controller@f1010000 { 2071 compatible = "arm,gic-400"; 2072 #interrupt-cells = <3>; 2073 #address-cells = <0>; 2074 interrupt-controller; 2075 reg = <0x0 0xf1010000 0 0x1000>, 2076 <0x0 0xf1020000 0 0x20000>, 2077 <0x0 0xf1040000 0 0x20000>, 2078 <0x0 0xf1060000 0 0x20000>; 2079 interrupts = <GIC_PPI 9 2080 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2081 clocks = <&cpg CPG_MOD 408>; 2082 clock-names = "clk"; 2083 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2084 resets = <&cpg 408>; 2085 }; 2086 2087 pciec0: pcie@fe000000 { 2088 compatible = "renesas,pcie-r8a774a1", 2089 "renesas,pcie-rcar-gen3"; 2090 reg = <0 0xfe000000 0 0x80000>; 2091 #address-cells = <3>; 2092 #size-cells = <2>; 2093 bus-range = <0x00 0xff>; 2094 device_type = "pci"; 2095 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 2096 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 2097 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 2098 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2099 /* Map all possible DDR as inbound ranges */ 2100 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2101 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2104 #interrupt-cells = <1>; 2105 interrupt-map-mask = <0 0 0 0>; 2106 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2107 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2108 clock-names = "pcie", "pcie_bus"; 2109 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2110 resets = <&cpg 319>; 2111 status = "disabled"; 2112 }; 2113 2114 pciec1: pcie@ee800000 { 2115 compatible = "renesas,pcie-r8a774a1", 2116 "renesas,pcie-rcar-gen3"; 2117 reg = <0 0xee800000 0 0x80000>; 2118 #address-cells = <3>; 2119 #size-cells = <2>; 2120 bus-range = <0x00 0xff>; 2121 device_type = "pci"; 2122 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 2123 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 2124 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 2125 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2126 /* Map all possible DDR as inbound ranges */ 2127 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2128 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2131 #interrupt-cells = <1>; 2132 interrupt-map-mask = <0 0 0 0>; 2133 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2134 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2135 clock-names = "pcie", "pcie_bus"; 2136 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2137 resets = <&cpg 318>; 2138 status = "disabled"; 2139 }; 2140 2141 fdp1@fe940000 { 2142 compatible = "renesas,fdp1"; 2143 reg = <0 0xfe940000 0 0x2400>; 2144 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2145 clocks = <&cpg CPG_MOD 119>; 2146 power-domains = <&sysc R8A774A1_PD_A3VC>; 2147 resets = <&cpg 119>; 2148 renesas,fcp = <&fcpf0>; 2149 }; 2150 2151 fcpf0: fcp@fe950000 { 2152 compatible = "renesas,fcpf"; 2153 reg = <0 0xfe950000 0 0x200>; 2154 clocks = <&cpg CPG_MOD 615>; 2155 power-domains = <&sysc R8A774A1_PD_A3VC>; 2156 resets = <&cpg 615>; 2157 }; 2158 2159 fcpvb0: fcp@fe96f000 { 2160 compatible = "renesas,fcpv"; 2161 reg = <0 0xfe96f000 0 0x200>; 2162 clocks = <&cpg CPG_MOD 607>; 2163 power-domains = <&sysc R8A774A1_PD_A3VC>; 2164 resets = <&cpg 607>; 2165 }; 2166 2167 fcpvd0: fcp@fea27000 { 2168 compatible = "renesas,fcpv"; 2169 reg = <0 0xfea27000 0 0x200>; 2170 clocks = <&cpg CPG_MOD 603>; 2171 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2172 resets = <&cpg 603>; 2173 iommus = <&ipmmu_vi0 8>; 2174 }; 2175 2176 fcpvd1: fcp@fea2f000 { 2177 compatible = "renesas,fcpv"; 2178 reg = <0 0xfea2f000 0 0x200>; 2179 clocks = <&cpg CPG_MOD 602>; 2180 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2181 resets = <&cpg 602>; 2182 iommus = <&ipmmu_vi0 9>; 2183 }; 2184 2185 fcpvd2: fcp@fea37000 { 2186 compatible = "renesas,fcpv"; 2187 reg = <0 0xfea37000 0 0x200>; 2188 clocks = <&cpg CPG_MOD 601>; 2189 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2190 resets = <&cpg 601>; 2191 iommus = <&ipmmu_vi0 10>; 2192 }; 2193 2194 fcpvi0: fcp@fe9af000 { 2195 compatible = "renesas,fcpv"; 2196 reg = <0 0xfe9af000 0 0x200>; 2197 clocks = <&cpg CPG_MOD 611>; 2198 power-domains = <&sysc R8A774A1_PD_A3VC>; 2199 resets = <&cpg 611>; 2200 iommus = <&ipmmu_vc0 19>; 2201 }; 2202 2203 vspb: vsp@fe960000 { 2204 compatible = "renesas,vsp2"; 2205 reg = <0 0xfe960000 0 0x8000>; 2206 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&cpg CPG_MOD 626>; 2208 power-domains = <&sysc R8A774A1_PD_A3VC>; 2209 resets = <&cpg 626>; 2210 2211 renesas,fcp = <&fcpvb0>; 2212 }; 2213 2214 vspd0: vsp@fea20000 { 2215 compatible = "renesas,vsp2"; 2216 reg = <0 0xfea20000 0 0x5000>; 2217 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2218 clocks = <&cpg CPG_MOD 623>; 2219 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2220 resets = <&cpg 623>; 2221 2222 renesas,fcp = <&fcpvd0>; 2223 }; 2224 2225 vspd1: vsp@fea28000 { 2226 compatible = "renesas,vsp2"; 2227 reg = <0 0xfea28000 0 0x5000>; 2228 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2229 clocks = <&cpg CPG_MOD 622>; 2230 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2231 resets = <&cpg 622>; 2232 2233 renesas,fcp = <&fcpvd1>; 2234 }; 2235 2236 vspd2: vsp@fea30000 { 2237 compatible = "renesas,vsp2"; 2238 reg = <0 0xfea30000 0 0x5000>; 2239 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2240 clocks = <&cpg CPG_MOD 621>; 2241 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2242 resets = <&cpg 621>; 2243 2244 renesas,fcp = <&fcpvd2>; 2245 }; 2246 2247 vspi0: vsp@fe9a0000 { 2248 compatible = "renesas,vsp2"; 2249 reg = <0 0xfe9a0000 0 0x8000>; 2250 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2251 clocks = <&cpg CPG_MOD 631>; 2252 power-domains = <&sysc R8A774A1_PD_A3VC>; 2253 resets = <&cpg 631>; 2254 2255 renesas,fcp = <&fcpvi0>; 2256 }; 2257 2258 csi20: csi2@fea80000 { 2259 compatible = "renesas,r8a774a1-csi2"; 2260 reg = <0 0xfea80000 0 0x10000>; 2261 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2262 clocks = <&cpg CPG_MOD 714>; 2263 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2264 resets = <&cpg 714>; 2265 status = "disabled"; 2266 2267 ports { 2268 #address-cells = <1>; 2269 #size-cells = <0>; 2270 2271 port@1 { 2272 #address-cells = <1>; 2273 #size-cells = <0>; 2274 2275 reg = <1>; 2276 2277 csi20vin0: endpoint@0 { 2278 reg = <0>; 2279 remote-endpoint = <&vin0csi20>; 2280 }; 2281 csi20vin1: endpoint@1 { 2282 reg = <1>; 2283 remote-endpoint = <&vin1csi20>; 2284 }; 2285 csi20vin2: endpoint@2 { 2286 reg = <2>; 2287 remote-endpoint = <&vin2csi20>; 2288 }; 2289 csi20vin3: endpoint@3 { 2290 reg = <3>; 2291 remote-endpoint = <&vin3csi20>; 2292 }; 2293 csi20vin4: endpoint@4 { 2294 reg = <4>; 2295 remote-endpoint = <&vin4csi20>; 2296 }; 2297 csi20vin5: endpoint@5 { 2298 reg = <5>; 2299 remote-endpoint = <&vin5csi20>; 2300 }; 2301 csi20vin6: endpoint@6 { 2302 reg = <6>; 2303 remote-endpoint = <&vin6csi20>; 2304 }; 2305 csi20vin7: endpoint@7 { 2306 reg = <7>; 2307 remote-endpoint = <&vin7csi20>; 2308 }; 2309 }; 2310 }; 2311 }; 2312 2313 csi40: csi2@feaa0000 { 2314 compatible = "renesas,r8a774a1-csi2"; 2315 reg = <0 0xfeaa0000 0 0x10000>; 2316 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2317 clocks = <&cpg CPG_MOD 716>; 2318 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2319 resets = <&cpg 716>; 2320 status = "disabled"; 2321 2322 ports { 2323 #address-cells = <1>; 2324 #size-cells = <0>; 2325 2326 port@1 { 2327 #address-cells = <1>; 2328 #size-cells = <0>; 2329 2330 reg = <1>; 2331 2332 csi40vin0: endpoint@0 { 2333 reg = <0>; 2334 remote-endpoint = <&vin0csi40>; 2335 }; 2336 csi40vin1: endpoint@1 { 2337 reg = <1>; 2338 remote-endpoint = <&vin1csi40>; 2339 }; 2340 csi40vin2: endpoint@2 { 2341 reg = <2>; 2342 remote-endpoint = <&vin2csi40>; 2343 }; 2344 csi40vin3: endpoint@3 { 2345 reg = <3>; 2346 remote-endpoint = <&vin3csi40>; 2347 }; 2348 csi40vin4: endpoint@4 { 2349 reg = <4>; 2350 remote-endpoint = <&vin4csi40>; 2351 }; 2352 csi40vin5: endpoint@5 { 2353 reg = <5>; 2354 remote-endpoint = <&vin5csi40>; 2355 }; 2356 csi40vin6: endpoint@6 { 2357 reg = <6>; 2358 remote-endpoint = <&vin6csi40>; 2359 }; 2360 csi40vin7: endpoint@7 { 2361 reg = <7>; 2362 remote-endpoint = <&vin7csi40>; 2363 }; 2364 }; 2365 2366 }; 2367 }; 2368 2369 du: display@feb00000 { 2370 compatible = "renesas,du-r8a774a1"; 2371 reg = <0 0xfeb00000 0 0x70000>; 2372 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2375 clocks = <&cpg CPG_MOD 724>, 2376 <&cpg CPG_MOD 723>, 2377 <&cpg CPG_MOD 722>; 2378 clock-names = "du.0", "du.1", "du.2"; 2379 status = "disabled"; 2380 2381 vsps = <&vspd0 &vspd1 &vspd2>; 2382 2383 ports { 2384 #address-cells = <1>; 2385 #size-cells = <0>; 2386 2387 port@0 { 2388 reg = <0>; 2389 du_out_rgb: endpoint { 2390 }; 2391 }; 2392 port@1 { 2393 reg = <1>; 2394 du_out_hdmi0: endpoint { 2395 }; 2396 }; 2397 port@2 { 2398 reg = <2>; 2399 du_out_lvds0: endpoint { 2400 remote-endpoint = <&lvds0_in>; 2401 }; 2402 }; 2403 }; 2404 }; 2405 2406 lvds0: lvds@feb90000 { 2407 compatible = "renesas,r8a774a1-lvds"; 2408 reg = <0 0xfeb90000 0 0x14>; 2409 clocks = <&cpg CPG_MOD 727>; 2410 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2411 resets = <&cpg 727>; 2412 status = "disabled"; 2413 2414 ports { 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 port@0 { 2419 reg = <0>; 2420 lvds0_in: endpoint { 2421 remote-endpoint = <&du_out_lvds0>; 2422 }; 2423 }; 2424 port@1 { 2425 reg = <1>; 2426 lvds0_out: endpoint { 2427 }; 2428 }; 2429 }; 2430 }; 2431 2432 prr: chipid@fff00044 { 2433 compatible = "renesas,prr"; 2434 reg = <0 0xfff00044 0 4>; 2435 }; 2436 }; 2437 2438 thermal-zones { 2439 sensor_thermal1: sensor-thermal1 { 2440 polling-delay-passive = <250>; 2441 polling-delay = <1000>; 2442 thermal-sensors = <&tsc 0>; 2443 sustainable-power = <3874>; 2444 2445 trips { 2446 sensor1_crit: sensor1-crit { 2447 temperature = <120000>; 2448 hysteresis = <1000>; 2449 type = "critical"; 2450 }; 2451 }; 2452 }; 2453 2454 sensor_thermal2: sensor-thermal2 { 2455 polling-delay-passive = <250>; 2456 polling-delay = <1000>; 2457 thermal-sensors = <&tsc 1>; 2458 sustainable-power = <3874>; 2459 2460 trips { 2461 sensor2_crit: sensor2-crit { 2462 temperature = <120000>; 2463 hysteresis = <1000>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 2469 sensor_thermal3: sensor-thermal3 { 2470 polling-delay-passive = <250>; 2471 polling-delay = <1000>; 2472 thermal-sensors = <&tsc 2>; 2473 sustainable-power = <3874>; 2474 2475 trips { 2476 target: trip-point1 { 2477 temperature = <100000>; 2478 hysteresis = <1000>; 2479 type = "passive"; 2480 }; 2481 2482 sensor3_crit: sensor3-crit { 2483 temperature = <120000>; 2484 hysteresis = <1000>; 2485 type = "critical"; 2486 }; 2487 }; 2488 cooling-maps { 2489 map0 { 2490 trip = <&target>; 2491 cooling-device = <&a57_0 0 2>; 2492 contribution = <1024>; 2493 }; 2494 map1 { 2495 trip = <&target>; 2496 cooling-device = <&a53_0 0 2>; 2497 contribution = <1024>; 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 timer { 2504 compatible = "arm,armv8-timer"; 2505 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2506 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2507 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2508 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2509 }; 2510 2511 /* External USB clocks - can be overridden by the board */ 2512 usb3s0_clk: usb3s0 { 2513 compatible = "fixed-clock"; 2514 #clock-cells = <0>; 2515 clock-frequency = <0>; 2516 }; 2517 2518 usb_extal_clk: usb_extal { 2519 compatible = "fixed-clock"; 2520 #clock-cells = <0>; 2521 clock-frequency = <0>; 2522 }; 2523}; 2524