r8a774a1.dtsi (426f0b95af0dfe4f33db6c5ef0a64b1ddcd27053) r8a774a1.dtsi (3698dbd02c93545f08dd309d159ef20956e07355)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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128 "renesas,rcar-gen3-wdt";
129 reg = <0 0xe6020000 0 0x0c>;
130 clocks = <&cpg CPG_MOD 402>;
131 power-domains = <&sysc 32>;
132 resets = <&cpg 402>;
133 status = "disabled";
134 };
135
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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128 "renesas,rcar-gen3-wdt";
129 reg = <0 0xe6020000 0 0x0c>;
130 clocks = <&cpg CPG_MOD 402>;
131 power-domains = <&sysc 32>;
132 resets = <&cpg 402>;
133 status = "disabled";
134 };
135
136 pfc: pin-controller@e6060000 {
137 compatible = "renesas,pfc-r8a774a1";
138 reg = <0 0xe6060000 0 0x50c>;
139 };
140
136 cpg: clock-controller@e6150000 {
137 compatible = "renesas,r8a774a1-cpg-mssr";
138 reg = <0 0xe6150000 0 0x0bb0>;
139 clocks = <&extal_clk>, <&extalr_clk>;
140 clock-names = "extal", "extalr";
141 #clock-cells = <2>;
142 #power-domain-cells = <0>;
143 #reset-cells = <1>;

--- 405 unchanged lines hidden --- 		141 cpg: clock-controller@e6150000 {
142 compatible = "renesas,r8a774a1-cpg-mssr";
143 reg = <0 0xe6150000 0 0x0bb0>;
144 clocks = <&extal_clk>, <&extalr_clk>;
145 clock-names = "extal", "extalr";
146 #clock-cells = <2>;
147 #power-domain-cells = <0>;
148 #reset-cells = <1>;

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